1 #include "r8192U.h" 2 #include "r8192U_hw.h" 3 #include "r819xU_phy.h" 4 #include "r819xU_phyreg.h" 5 #include "r8190_rtl8256.h" 6 #include "r8192U_dm.h" 7 #include "r819xU_firmware_img.h" 8 9 #include "dot11d.h" 10 #include <linux/bitops.h> 11 12 static u32 RF_CHANNEL_TABLE_ZEBRA[] = { 13 0, 14 0x085c, /* 2412 1 */ 15 0x08dc, /* 2417 2 */ 16 0x095c, /* 2422 3 */ 17 0x09dc, /* 2427 4 */ 18 0x0a5c, /* 2432 5 */ 19 0x0adc, /* 2437 6 */ 20 0x0b5c, /* 2442 7 */ 21 0x0bdc, /* 2447 8 */ 22 0x0c5c, /* 2452 9 */ 23 0x0cdc, /* 2457 10 */ 24 0x0d5c, /* 2462 11 */ 25 0x0ddc, /* 2467 12 */ 26 0x0e5c, /* 2472 13 */ 27 0x0f72, /* 2484 */ 28 }; 29 30 31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray 32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG 33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array 34 #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array 35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array 36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array 37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array 38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array 39 40 /****************************************************************************** 41 * function: This function checks different RF type to execute legal judgement. 42 * If RF Path is illegal, we will return false. 43 * input: net_device *dev 44 * u32 eRFPath 45 * output: none 46 * return: 0(illegal, false), 1(legal, true) 47 *****************************************************************************/ 48 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath) 49 { 50 u8 ret = 1; 51 struct r8192_priv *priv = ieee80211_priv(dev); 52 53 if (priv->rf_type == RF_2T4R) { 54 ret = 0; 55 } else if (priv->rf_type == RF_1T2R) { 56 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 57 ret = 1; 58 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) 59 ret = 0; 60 } 61 return ret; 62 } 63 64 /****************************************************************************** 65 * function: This function sets specific bits to BB register 66 * input: net_device *dev 67 * u32 reg_addr //target addr to be modified 68 * u32 bitmask //taget bit pos to be modified 69 * u32 data //value to be write 70 * output: none 71 * return: none 72 * notice: 73 ******************************************************************************/ 74 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask, 75 u32 data) 76 { 77 78 u32 reg, bitshift; 79 80 if (bitmask != bMaskDWord) { 81 read_nic_dword(dev, reg_addr, ®); 82 bitshift = ffs(bitmask) - 1; 83 reg &= ~bitmask; 84 reg |= data << bitshift; 85 write_nic_dword(dev, reg_addr, reg); 86 } else { 87 write_nic_dword(dev, reg_addr, data); 88 } 89 } 90 91 /****************************************************************************** 92 * function: This function reads specific bits from BB register 93 * input: net_device *dev 94 * u32 reg_addr //target addr to be readback 95 * u32 bitmask //taget bit pos to be readback 96 * output: none 97 * return: u32 data //the readback register value 98 * notice: 99 ******************************************************************************/ 100 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask) 101 { 102 u32 reg, bitshift; 103 104 read_nic_dword(dev, reg_addr, ®); 105 bitshift = ffs(bitmask) - 1; 106 107 return (reg & bitmask) >> bitshift; 108 } 109 110 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, 111 u32 offset); 112 113 static void phy_FwRFSerialWrite(struct net_device *dev, 114 RF90_RADIO_PATH_E eRFPath, u32 offset, 115 u32 data); 116 117 /****************************************************************************** 118 * function: This function reads register from RF chip 119 * input: net_device *dev 120 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D 121 * u32 offset //target address to be read 122 * output: none 123 * return: u32 readback value 124 * notice: There are three types of serial operations: 125 * (1) Software serial write. 126 * (2)Hardware LSSI-Low Speed Serial Interface. 127 * (3)Hardware HSSI-High speed serial write. 128 * Driver here need to implement (1) and (2) 129 * ---need more spec for this information. 130 ******************************************************************************/ 131 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, 132 RF90_RADIO_PATH_E eRFPath, u32 offset) 133 { 134 struct r8192_priv *priv = ieee80211_priv(dev); 135 u32 ret = 0; 136 u32 new_offset = 0; 137 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; 138 139 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); 140 /* Make sure RF register offset is correct */ 141 offset &= 0x3f; 142 143 /* Switch page for 8256 RF IC */ 144 if (priv->rf_chip == RF_8256) { 145 if (offset >= 31) { 146 priv->RfReg0Value[eRFPath] |= 0x140; 147 /* Switch to Reg_Mode2 for Reg 31-45 */ 148 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 149 bMaskDWord, 150 priv->RfReg0Value[eRFPath]<<16); 151 /* Modify offset */ 152 new_offset = offset - 30; 153 } else if (offset >= 16) { 154 priv->RfReg0Value[eRFPath] |= 0x100; 155 priv->RfReg0Value[eRFPath] &= (~0x40); 156 /* Switch to Reg_Mode1 for Reg16-30 */ 157 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 158 bMaskDWord, 159 priv->RfReg0Value[eRFPath]<<16); 160 161 new_offset = offset - 15; 162 } else { 163 new_offset = offset; 164 } 165 } else { 166 RT_TRACE((COMP_PHY|COMP_ERR), 167 "check RF type here, need to be 8256\n"); 168 new_offset = offset; 169 } 170 /* Put desired read addr to LSSI control Register */ 171 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, 172 new_offset); 173 /* Issue a posedge trigger */ 174 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); 175 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); 176 177 178 /* TODO: we should not delay such a long time. Ask for help from SD3 */ 179 usleep_range(1000, 1000); 180 181 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, 182 bLSSIReadBackData); 183 184 185 /* Switch back to Reg_Mode0 */ 186 if (priv->rf_chip == RF_8256) { 187 priv->RfReg0Value[eRFPath] &= 0xebf; 188 189 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, 190 priv->RfReg0Value[eRFPath] << 16); 191 } 192 193 return ret; 194 } 195 196 /****************************************************************************** 197 * function: This function writes data to RF register 198 * input: net_device *dev 199 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D 200 * u32 offset //target address to be written 201 * u32 data //the new register data to be written 202 * output: none 203 * return: none 204 * notice: For RF8256 only. 205 * =========================================================================== 206 * Reg Mode RegCTL[1] RegCTL[0] Note 207 * (Reg00[12]) (Reg00[10]) 208 * =========================================================================== 209 * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf) 210 * --------------------------------------------------------------------------- 211 * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf) 212 * --------------------------------------------------------------------------- 213 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) 214 * --------------------------------------------------------------------------- 215 *****************************************************************************/ 216 static void rtl8192_phy_RFSerialWrite(struct net_device *dev, 217 RF90_RADIO_PATH_E eRFPath, u32 offset, 218 u32 data) 219 { 220 struct r8192_priv *priv = ieee80211_priv(dev); 221 u32 DataAndAddr = 0, new_offset = 0; 222 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; 223 224 offset &= 0x3f; 225 if (priv->rf_chip == RF_8256) { 226 227 if (offset >= 31) { 228 priv->RfReg0Value[eRFPath] |= 0x140; 229 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 230 bMaskDWord, 231 priv->RfReg0Value[eRFPath] << 16); 232 new_offset = offset - 30; 233 } else if (offset >= 16) { 234 priv->RfReg0Value[eRFPath] |= 0x100; 235 priv->RfReg0Value[eRFPath] &= (~0x40); 236 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 237 bMaskDWord, 238 priv->RfReg0Value[eRFPath]<<16); 239 new_offset = offset - 15; 240 } else { 241 new_offset = offset; 242 } 243 } else { 244 RT_TRACE((COMP_PHY|COMP_ERR), 245 "check RF type here, need to be 8256\n"); 246 new_offset = offset; 247 } 248 249 /* Put write addr in [5:0] and write data in [31:16] */ 250 DataAndAddr = (data<<16) | (new_offset&0x3f); 251 252 /* Write operation */ 253 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 254 255 256 if (offset == 0x0) 257 priv->RfReg0Value[eRFPath] = data; 258 259 /* Switch back to Reg_Mode0 */ 260 if (priv->rf_chip == RF_8256) { 261 if (offset != 0) { 262 priv->RfReg0Value[eRFPath] &= 0xebf; 263 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 264 bMaskDWord, 265 priv->RfReg0Value[eRFPath] << 16); 266 } 267 } 268 } 269 270 /****************************************************************************** 271 * function: This function set specific bits to RF register 272 * input: net_device dev 273 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D 274 * u32 reg_addr //target addr to be modified 275 * u32 bitmask //taget bit pos to be modified 276 * u32 data //value to be written 277 * output: none 278 * return: none 279 * notice: 280 *****************************************************************************/ 281 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, 282 u32 reg_addr, u32 bitmask, u32 data) 283 { 284 struct r8192_priv *priv = ieee80211_priv(dev); 285 u32 reg, bitshift; 286 287 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 288 return; 289 290 if (priv->Rf_Mode == RF_OP_By_FW) { 291 if (bitmask != bMask12Bits) { 292 /* RF data is 12 bits only */ 293 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr); 294 bitshift = ffs(bitmask) - 1; 295 reg &= ~bitmask; 296 reg |= data << bitshift; 297 298 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, reg); 299 } else { 300 phy_FwRFSerialWrite(dev, eRFPath, reg_addr, data); 301 } 302 303 udelay(200); 304 305 } else { 306 if (bitmask != bMask12Bits) { 307 /* RF data is 12 bits only */ 308 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr); 309 bitshift = ffs(bitmask) - 1; 310 reg &= ~bitmask; 311 reg |= data << bitshift; 312 313 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, reg); 314 } else { 315 rtl8192_phy_RFSerialWrite(dev, eRFPath, reg_addr, data); 316 } 317 } 318 } 319 320 /****************************************************************************** 321 * function: This function reads specific bits from RF register 322 * input: net_device *dev 323 * u32 reg_addr //target addr to be readback 324 * u32 bitmask //taget bit pos to be readback 325 * output: none 326 * return: u32 data //the readback register value 327 * notice: 328 *****************************************************************************/ 329 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, 330 u32 reg_addr, u32 bitmask) 331 { 332 u32 reg, bitshift; 333 struct r8192_priv *priv = ieee80211_priv(dev); 334 335 336 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 337 return 0; 338 if (priv->Rf_Mode == RF_OP_By_FW) { 339 reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr); 340 udelay(200); 341 } else { 342 reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr); 343 } 344 bitshift = ffs(bitmask) - 1; 345 reg = (reg & bitmask) >> bitshift; 346 return reg; 347 348 } 349 350 /****************************************************************************** 351 * function: We support firmware to execute RF-R/W. 352 * input: net_device *dev 353 * RF90_RADIO_PATH_E eRFPath 354 * u32 offset 355 * output: none 356 * return: u32 357 * notice: 358 ****************************************************************************/ 359 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath, 360 u32 offset) 361 { 362 u32 reg = 0; 363 u32 data = 0; 364 u8 time = 0; 365 u32 tmp; 366 367 /* Firmware RF Write control. 368 * We can not execute the scheme in the initial step. 369 * Otherwise, RF-R/W will waste much time. 370 * This is only for site survey. */ 371 /* 1. Read operation need not insert data. bit 0-11 */ 372 /* 2. Write RF register address. bit 12-19 */ 373 data |= ((offset&0xFF)<<12); 374 /* 3. Write RF path. bit 20-21 */ 375 data |= ((eRFPath&0x3)<<20); 376 /* 4. Set RF read indicator. bit 22=0 */ 377 /* 5. Trigger Fw to operate the command. bit 31 */ 378 data |= 0x80000000; 379 /* 6. We can not execute read operation if bit 31 is 1. */ 380 read_nic_dword(dev, QPNR, &tmp); 381 while (tmp & 0x80000000) { 382 /* If FW can not finish RF-R/W for more than ?? times. 383 We must reset FW. */ 384 if (time++ < 100) { 385 udelay(10); 386 read_nic_dword(dev, QPNR, &tmp); 387 } else { 388 break; 389 } 390 } 391 /* 7. Execute read operation. */ 392 write_nic_dword(dev, QPNR, data); 393 /* 8. Check if firmware send back RF content. */ 394 read_nic_dword(dev, QPNR, &tmp); 395 while (tmp & 0x80000000) { 396 /* If FW can not finish RF-R/W for more than ?? times. 397 We must reset FW. */ 398 if (time++ < 100) { 399 udelay(10); 400 read_nic_dword(dev, QPNR, &tmp); 401 } else { 402 return 0; 403 } 404 } 405 read_nic_dword(dev, RF_DATA, ®); 406 407 return reg; 408 } 409 410 /****************************************************************************** 411 * function: We support firmware to execute RF-R/W. 412 * input: net_device *dev 413 * RF90_RADIO_PATH_E eRFPath 414 * u32 offset 415 * u32 data 416 * output: none 417 * return: none 418 * notice: 419 ****************************************************************************/ 420 static void phy_FwRFSerialWrite(struct net_device *dev, 421 RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data) 422 { 423 u8 time = 0; 424 u32 tmp; 425 426 /* Firmware RF Write control. 427 * We can not execute the scheme in the initial step. 428 * Otherwise, RF-R/W will waste much time. 429 * This is only for site survey. */ 430 431 /* 1. Set driver write bit and 12 bit data. bit 0-11 */ 432 /* 2. Write RF register address. bit 12-19 */ 433 data |= ((offset&0xFF)<<12); 434 /* 3. Write RF path. bit 20-21 */ 435 data |= ((eRFPath&0x3)<<20); 436 /* 4. Set RF write indicator. bit 22=1 */ 437 data |= 0x400000; 438 /* 5. Trigger Fw to operate the command. bit 31=1 */ 439 data |= 0x80000000; 440 441 /* 6. Write operation. We can not write if bit 31 is 1. */ 442 read_nic_dword(dev, QPNR, &tmp); 443 while (tmp & 0x80000000) { 444 /* If FW can not finish RF-R/W for more than ?? times. 445 We must reset FW. */ 446 if (time++ < 100) { 447 udelay(10); 448 read_nic_dword(dev, QPNR, &tmp); 449 } else { 450 break; 451 } 452 } 453 /* 7. No matter check bit. We always force the write. 454 Because FW will not accept the command. */ 455 write_nic_dword(dev, QPNR, data); 456 /* According to test, we must delay 20us to wait firmware 457 to finish RF write operation. */ 458 /* We support delay in firmware side now. */ 459 } 460 461 /****************************************************************************** 462 * function: This function reads BB parameters from header file we generate, 463 * and do register read/write 464 * input: net_device *dev 465 * output: none 466 * return: none 467 * notice: BB parameters may change all the time, so please make 468 * sure it has been synced with the newest. 469 *****************************************************************************/ 470 void rtl8192_phy_configmac(struct net_device *dev) 471 { 472 u32 dwArrayLen = 0, i; 473 u32 *pdwArray = NULL; 474 struct r8192_priv *priv = ieee80211_priv(dev); 475 476 if (priv->btxpowerdata_readfromEEPORM) { 477 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); 478 dwArrayLen = MACPHY_Array_PGLength; 479 pdwArray = rtl819XMACPHY_Array_PG; 480 481 } else { 482 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n"); 483 dwArrayLen = MACPHY_ArrayLength; 484 pdwArray = rtl819XMACPHY_Array; 485 } 486 for (i = 0; i < dwArrayLen; i = i+3) { 487 if (pdwArray[i] == 0x318) 488 pdwArray[i+2] = 0x00000800; 489 490 RT_TRACE(COMP_DBG, 491 "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n", 492 pdwArray[i], pdwArray[i+1], pdwArray[i+2]); 493 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], 494 pdwArray[i+2]); 495 } 496 } 497 498 /****************************************************************************** 499 * function: This function does dirty work 500 * input: net_device *dev 501 * u8 ConfigType 502 * output: none 503 * return: none 504 * notice: BB parameters may change all the time, so please make 505 * sure it has been synced with the newest. 506 *****************************************************************************/ 507 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType) 508 { 509 u32 i; 510 511 #ifdef TO_DO_LIST 512 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; 513 514 if (Adapter->bInHctTest) { 515 PHY_REGArrayLen = PHY_REGArrayLengthDTM; 516 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; 517 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; 518 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; 519 } 520 #endif 521 if (ConfigType == BaseBand_Config_PHY_REG) { 522 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) { 523 rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], 524 bMaskDWord, 525 rtl819XPHY_REG_1T2RArray[i+1]); 526 RT_TRACE(COMP_DBG, 527 "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n", 528 i, rtl819XPHY_REG_1T2RArray[i], 529 rtl819XPHY_REG_1T2RArray[i+1]); 530 } 531 } else if (ConfigType == BaseBand_Config_AGC_TAB) { 532 for (i = 0; i < AGCTAB_ArrayLength; i += 2) { 533 rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], 534 bMaskDWord, rtl819XAGCTAB_Array[i+1]); 535 RT_TRACE(COMP_DBG, 536 "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n", 537 i, rtl819XAGCTAB_Array[i], 538 rtl819XAGCTAB_Array[i+1]); 539 } 540 } 541 } 542 543 /****************************************************************************** 544 * function: This function initializes Register definition offset for 545 * Radio Path A/B/C/D 546 * input: net_device *dev 547 * output: none 548 * return: none 549 * notice: Initialization value here is constant and it should never 550 * be changed 551 *****************************************************************************/ 552 static void rtl8192_InitBBRFRegDef(struct net_device *dev) 553 { 554 struct r8192_priv *priv = ieee80211_priv(dev); 555 556 /* RF Interface Software Control */ 557 /* 16 LSBs if read 32-bit from 0x870 */ 558 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; 559 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ 560 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; 561 /* 16 LSBs if read 32-bit from 0x874 */ 562 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; 563 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ 564 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; 565 566 /* RF Interface Readback Value */ 567 /* 16 LSBs if read 32-bit from 0x8E0 */ 568 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; 569 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ 570 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; 571 /* 16 LSBs if read 32-bit from 0x8E4 */ 572 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; 573 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ 574 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; 575 576 /* RF Interface Output (and Enable) */ 577 /* 16 LSBs if read 32-bit from 0x860 */ 578 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; 579 /* 16 LSBs if read 32-bit from 0x864 */ 580 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; 581 /* 16 LSBs if read 32-bit from 0x868 */ 582 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; 583 /* 16 LSBs if read 32-bit from 0x86C */ 584 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; 585 586 /* RF Interface (Output and) Enable */ 587 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ 588 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; 589 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ 590 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; 591 /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */ 592 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; 593 /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */ 594 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; 595 596 /* Addr of LSSI. Write RF register by driver */ 597 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; 598 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 599 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; 600 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; 601 602 /* RF parameter */ 603 /* BB Band Select */ 604 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; 605 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; 606 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; 607 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; 608 609 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ 610 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; 611 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; 612 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; 613 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; 614 615 /* Tranceiver A~D HSSI Parameter-1 */ 616 /* wire control parameter1 */ 617 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; 618 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; 619 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; 620 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; 621 622 /* Tranceiver A~D HSSI Parameter-2 */ 623 /* wire control parameter2 */ 624 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; 625 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; 626 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; 627 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; 628 629 /* RF Switch Control */ 630 /* TR/Ant switch control */ 631 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; 632 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; 633 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; 634 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; 635 636 /* AGC control 1 */ 637 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 638 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; 639 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; 640 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; 641 642 /* AGC control 2 */ 643 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; 644 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; 645 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; 646 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; 647 648 /* RX AFE control 1 */ 649 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; 650 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; 651 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; 652 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; 653 654 /* RX AFE control 1 */ 655 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; 656 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; 657 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; 658 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; 659 660 /* Tx AFE control 1 */ 661 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; 662 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; 663 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; 664 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; 665 666 /* Tx AFE control 2 */ 667 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; 668 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; 669 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; 670 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; 671 672 /* Tranceiver LSSI Readback */ 673 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 674 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 675 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; 676 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; 677 } 678 679 /****************************************************************************** 680 * function: This function is to write register and then readback to make 681 * sure whether BB and RF is OK 682 * input: net_device *dev 683 * HW90_BLOCK_E CheckBlock 684 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is 685 * //HW90_BLOCK_RF 686 * output: none 687 * return: return whether BB and RF is ok (0:OK, 1:Fail) 688 * notice: This function may be removed in the ASIC 689 ******************************************************************************/ 690 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock, 691 RF90_RADIO_PATH_E eRFPath) 692 { 693 u8 ret = 0; 694 u32 i, CheckTimes = 4, reg = 0; 695 u32 WriteAddr[4]; 696 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; 697 698 /* Initialize register address offset to be checked */ 699 WriteAddr[HW90_BLOCK_MAC] = 0x100; 700 WriteAddr[HW90_BLOCK_PHY0] = 0x900; 701 WriteAddr[HW90_BLOCK_PHY1] = 0x800; 702 WriteAddr[HW90_BLOCK_RF] = 0x3; 703 RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock); 704 for (i = 0; i < CheckTimes; i++) { 705 706 /* Write data to register and readback */ 707 switch (CheckBlock) { 708 case HW90_BLOCK_MAC: 709 RT_TRACE(COMP_ERR, 710 "PHY_CheckBBRFOK(): Never Write 0x100 here!\n"); 711 break; 712 713 case HW90_BLOCK_PHY0: 714 case HW90_BLOCK_PHY1: 715 write_nic_dword(dev, WriteAddr[CheckBlock], 716 WriteData[i]); 717 read_nic_dword(dev, WriteAddr[CheckBlock], ®); 718 break; 719 720 case HW90_BLOCK_RF: 721 WriteData[i] &= 0xfff; 722 rtl8192_phy_SetRFReg(dev, eRFPath, 723 WriteAddr[HW90_BLOCK_RF], 724 bMask12Bits, WriteData[i]); 725 /* TODO: we should not delay for such a long time. 726 Ask SD3 */ 727 usleep_range(1000, 1000); 728 reg = rtl8192_phy_QueryRFReg(dev, eRFPath, 729 WriteAddr[HW90_BLOCK_RF], 730 bMask12Bits); 731 usleep_range(1000, 1000); 732 break; 733 734 default: 735 ret = 1; 736 break; 737 } 738 739 740 /* Check whether readback data is correct */ 741 if (reg != WriteData[i]) { 742 RT_TRACE((COMP_PHY|COMP_ERR), 743 "error reg: %x, WriteData: %x\n", 744 reg, WriteData[i]); 745 ret = 1; 746 break; 747 } 748 } 749 750 return ret; 751 } 752 753 /****************************************************************************** 754 * function: This function initializes BB&RF 755 * input: net_device *dev 756 * output: none 757 * return: none 758 * notice: Initialization value may change all the time, so please make 759 * sure it has been synced with the newest. 760 ******************************************************************************/ 761 static void rtl8192_BB_Config_ParaFile(struct net_device *dev) 762 { 763 struct r8192_priv *priv = ieee80211_priv(dev); 764 u8 reg_u8 = 0, eCheckItem = 0, status = 0; 765 u32 reg_u32 = 0; 766 767 /************************************** 768 * <1> Initialize BaseBand 769 *************************************/ 770 771 /* --set BB Global Reset-- */ 772 read_nic_byte(dev, BB_GLOBAL_RESET, ®_u8); 773 write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT)); 774 mdelay(50); 775 /* ---set BB reset Active--- */ 776 read_nic_dword(dev, CPU_GEN, ®_u32); 777 write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST))); 778 779 /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */ 780 /* TODO: this function should be removed on ASIC */ 781 for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0; 782 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { 783 /* don't care RF path */ 784 status = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, 785 (RF90_RADIO_PATH_E)0); 786 if (status != 0) { 787 RT_TRACE((COMP_ERR | COMP_PHY), 788 "PHY_RF8256_Config(): Check PHY%d Fail!!\n", 789 eCheckItem-1); 790 return; 791 } 792 } 793 /* ---- Set CCK and OFDM Block "OFF"---- */ 794 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); 795 /* ----BB Register Initilazation---- */ 796 /* ==m==>Set PHY REG From Header<==m== */ 797 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); 798 799 /* ----Set BB reset de-Active---- */ 800 read_nic_dword(dev, CPU_GEN, ®_u32); 801 write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST)); 802 803 /* ----BB AGC table Initialization---- */ 804 /* ==m==>Set PHY REG From Header<==m== */ 805 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); 806 807 /* ----Enable XSTAL ---- */ 808 write_nic_byte_E(dev, 0x5e, 0x00); 809 if (priv->card_8192_version == (u8)VERSION_819xU_A) { 810 /* Antenna gain offset from B/C/D to A */ 811 reg_u32 = priv->AntennaTxPwDiff[1]<<4 | 812 priv->AntennaTxPwDiff[0]; 813 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), 814 reg_u32); 815 816 /* XSTALLCap */ 817 reg_u32 = priv->CrystalCap & 0xf; 818 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, 819 reg_u32); 820 } 821 822 /* Check if the CCK HighPower is turned ON. 823 This is used to calculate PWDB. */ 824 priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev, 825 rFPGA0_XA_HSSIParameter2, 826 0x200); 827 } 828 829 /****************************************************************************** 830 * function: This function initializes BB&RF 831 * input: net_device *dev 832 * output: none 833 * return: none 834 * notice: Initialization value may change all the time, so please make 835 * sure it has been synced with the newest. 836 *****************************************************************************/ 837 void rtl8192_BBConfig(struct net_device *dev) 838 { 839 rtl8192_InitBBRFRegDef(dev); 840 /* config BB&RF. As hardCode based initialization has not been well 841 * implemented, so use file first. 842 * FIXME: should implement it for hardcode? */ 843 rtl8192_BB_Config_ParaFile(dev); 844 } 845 846 847 /****************************************************************************** 848 * function: This function obtains the initialization value of Tx power Level 849 * offset 850 * input: net_device *dev 851 * output: none 852 * return: none 853 *****************************************************************************/ 854 void rtl8192_phy_getTxPower(struct net_device *dev) 855 { 856 struct r8192_priv *priv = ieee80211_priv(dev); 857 u8 tmp; 858 859 read_nic_dword(dev, rTxAGC_Rate18_06, 860 &priv->MCSTxPowerLevelOriginalOffset[0]); 861 read_nic_dword(dev, rTxAGC_Rate54_24, 862 &priv->MCSTxPowerLevelOriginalOffset[1]); 863 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, 864 &priv->MCSTxPowerLevelOriginalOffset[2]); 865 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, 866 &priv->MCSTxPowerLevelOriginalOffset[3]); 867 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, 868 &priv->MCSTxPowerLevelOriginalOffset[4]); 869 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, 870 &priv->MCSTxPowerLevelOriginalOffset[5]); 871 872 /* Read rx initial gain */ 873 read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]); 874 read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]); 875 read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]); 876 read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]); 877 RT_TRACE(COMP_INIT, 878 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", 879 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], 880 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); 881 882 /* Read framesync */ 883 read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync); 884 read_nic_byte(dev, rOFDM0_RxDetector2, &tmp); 885 priv->framesyncC34 = tmp; 886 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", 887 rOFDM0_RxDetector3, priv->framesync); 888 889 /* Read SIFS (save the value read fome MACPHY_REG.txt) */ 890 read_nic_word(dev, SIFS, &priv->SifsTime); 891 } 892 893 /****************************************************************************** 894 * function: This function sets the initialization value of Tx power Level 895 * offset 896 * input: net_device *dev 897 * u8 channel 898 * output: none 899 * return: none 900 ******************************************************************************/ 901 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) 902 { 903 struct r8192_priv *priv = ieee80211_priv(dev); 904 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 905 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 906 907 switch (priv->rf_chip) { 908 case RF_8256: 909 /* need further implement */ 910 PHY_SetRF8256CCKTxPower(dev, powerlevel); 911 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); 912 break; 913 default: 914 RT_TRACE((COMP_PHY|COMP_ERR), 915 "error RF chipID(8225 or 8258) in function %s()\n", 916 __func__); 917 break; 918 } 919 } 920 921 /****************************************************************************** 922 * function: This function checks Rf chip to do RF config 923 * input: net_device *dev 924 * output: none 925 * return: only 8256 is supported 926 ******************************************************************************/ 927 void rtl8192_phy_RFConfig(struct net_device *dev) 928 { 929 struct r8192_priv *priv = ieee80211_priv(dev); 930 931 switch (priv->rf_chip) { 932 case RF_8256: 933 PHY_RF8256_Config(dev); 934 break; 935 default: 936 RT_TRACE(COMP_ERR, "error chip id\n"); 937 break; 938 } 939 } 940 941 /****************************************************************************** 942 * function: This function updates Initial gain 943 * input: net_device *dev 944 * output: none 945 * return: As Windows has not implemented this, wait for complement 946 ******************************************************************************/ 947 void rtl8192_phy_updateInitGain(struct net_device *dev) 948 { 949 } 950 951 /****************************************************************************** 952 * function: This function read RF parameters from general head file, 953 * and do RF 3-wire 954 * input: net_device *dev 955 * RF90_RADIO_PATH_E eRFPath 956 * output: none 957 * return: return code show if RF configuration is successful(0:pass, 1:fail) 958 * notice: Delay may be required for RF configuration 959 *****************************************************************************/ 960 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, 961 RF90_RADIO_PATH_E eRFPath) 962 { 963 964 int i; 965 966 switch (eRFPath) { 967 case RF90_PATH_A: 968 for (i = 0; i < RadioA_ArrayLength; i = i+2) { 969 970 if (rtl819XRadioA_Array[i] == 0xfe) { 971 mdelay(100); 972 continue; 973 } 974 rtl8192_phy_SetRFReg(dev, eRFPath, 975 rtl819XRadioA_Array[i], 976 bMask12Bits, 977 rtl819XRadioA_Array[i+1]); 978 mdelay(1); 979 980 } 981 break; 982 case RF90_PATH_B: 983 for (i = 0; i < RadioB_ArrayLength; i = i+2) { 984 985 if (rtl819XRadioB_Array[i] == 0xfe) { 986 mdelay(100); 987 continue; 988 } 989 rtl8192_phy_SetRFReg(dev, eRFPath, 990 rtl819XRadioB_Array[i], 991 bMask12Bits, 992 rtl819XRadioB_Array[i+1]); 993 mdelay(1); 994 995 } 996 break; 997 case RF90_PATH_C: 998 for (i = 0; i < RadioC_ArrayLength; i = i+2) { 999 1000 if (rtl819XRadioC_Array[i] == 0xfe) { 1001 mdelay(100); 1002 continue; 1003 } 1004 rtl8192_phy_SetRFReg(dev, eRFPath, 1005 rtl819XRadioC_Array[i], 1006 bMask12Bits, 1007 rtl819XRadioC_Array[i+1]); 1008 mdelay(1); 1009 1010 } 1011 break; 1012 case RF90_PATH_D: 1013 for (i = 0; i < RadioD_ArrayLength; i = i+2) { 1014 1015 if (rtl819XRadioD_Array[i] == 0xfe) { 1016 mdelay(100); 1017 continue; 1018 } 1019 rtl8192_phy_SetRFReg(dev, eRFPath, 1020 rtl819XRadioD_Array[i], 1021 bMask12Bits, 1022 rtl819XRadioD_Array[i+1]); 1023 mdelay(1); 1024 1025 } 1026 break; 1027 default: 1028 break; 1029 } 1030 1031 return 0; 1032 1033 } 1034 1035 /****************************************************************************** 1036 * function: This function sets Tx Power of the channel 1037 * input: net_device *dev 1038 * u8 channel 1039 * output: none 1040 * return: none 1041 * notice: 1042 ******************************************************************************/ 1043 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) 1044 { 1045 struct r8192_priv *priv = ieee80211_priv(dev); 1046 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 1047 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 1048 1049 switch (priv->rf_chip) { 1050 case RF_8225: 1051 #ifdef TO_DO_LIST 1052 PHY_SetRF8225CckTxPower(Adapter, powerlevel); 1053 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); 1054 #endif 1055 break; 1056 1057 case RF_8256: 1058 PHY_SetRF8256CCKTxPower(dev, powerlevel); 1059 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); 1060 break; 1061 1062 case RF_8258: 1063 break; 1064 default: 1065 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__); 1066 break; 1067 } 1068 } 1069 1070 /****************************************************************************** 1071 * function: This function sets RF state on or off 1072 * input: net_device *dev 1073 * RT_RF_POWER_STATE eRFPowerState //Power State to set 1074 * output: none 1075 * return: none 1076 * notice: 1077 *****************************************************************************/ 1078 bool rtl8192_SetRFPowerState(struct net_device *dev, 1079 RT_RF_POWER_STATE eRFPowerState) 1080 { 1081 bool bResult = true; 1082 struct r8192_priv *priv = ieee80211_priv(dev); 1083 1084 if (eRFPowerState == priv->ieee80211->eRFPowerState) 1085 return false; 1086 1087 if (priv->SetRFPowerStateInProgress) 1088 return false; 1089 1090 priv->SetRFPowerStateInProgress = true; 1091 1092 switch (priv->rf_chip) { 1093 case RF_8256: 1094 switch (eRFPowerState) { 1095 case eRfOn: 1096 /* RF-A, RF-B */ 1097 /* enable RF-Chip A/B - 0x860[4] */ 1098 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), 1099 0x1); 1100 /* analog to digital on - 0x88c[9:8] */ 1101 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 1102 0x3); 1103 /* digital to analog on - 0x880[4:3] */ 1104 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 1105 0x3); 1106 /* rx antenna on - 0xc04[1:0] */ 1107 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); 1108 /* rx antenna on - 0xd04[1:0] */ 1109 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); 1110 /* analog to digital part2 on - 0x880[6:5] */ 1111 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 1112 0x3); 1113 1114 break; 1115 1116 case eRfSleep: 1117 1118 break; 1119 1120 case eRfOff: 1121 /* RF-A, RF-B */ 1122 /* disable RF-Chip A/B - 0x860[4] */ 1123 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), 1124 0x0); 1125 /* analog to digital off, for power save */ 1126 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 1127 0x0); /* 0x88c[11:8] */ 1128 /* digital to analog off, for power save - 0x880[4:3] */ 1129 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 1130 0x0); 1131 /* rx antenna off - 0xc04[3:0] */ 1132 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); 1133 /* rx antenna off - 0xd04[3:0] */ 1134 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); 1135 /* analog to digital part2 off, for power save */ 1136 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 1137 0x0); /* 0x880[6:5] */ 1138 1139 break; 1140 1141 default: 1142 bResult = false; 1143 RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n", 1144 __func__, eRFPowerState); 1145 break; 1146 } 1147 break; 1148 default: 1149 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip); 1150 break; 1151 } 1152 #ifdef TO_DO_LIST 1153 if (bResult) { 1154 /* Update current RF state variable. */ 1155 pHalData->eRFPowerState = eRFPowerState; 1156 switch (pHalData->RFChipID) { 1157 case RF_8256: 1158 switch (pHalData->eRFPowerState) { 1159 case eRfOff: 1160 /* If Rf off reason is from IPS, 1161 LED should blink with no link */ 1162 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS) 1163 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); 1164 else 1165 /* Turn off LED if RF is not ON. */ 1166 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); 1167 break; 1168 1169 case eRfOn: 1170 /* Turn on RF we are still linked, which might 1171 happen when we quickly turn off and on HW RF. 1172 */ 1173 if (pMgntInfo->bMediaConnect) 1174 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); 1175 else 1176 /* Turn off LED if RF is not ON. */ 1177 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); 1178 break; 1179 1180 default: 1181 break; 1182 } 1183 break; 1184 1185 default: 1186 RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n", 1187 __func__); 1188 break; 1189 } 1190 1191 } 1192 #endif 1193 priv->SetRFPowerStateInProgress = false; 1194 1195 return bResult; 1196 } 1197 1198 /****************************************************************************** 1199 * function: This function sets command table variable (struct SwChnlCmd). 1200 * input: SwChnlCmd *CmdTable //table to be set 1201 * u32 CmdTableIdx //variable index in table to be set 1202 * u32 CmdTableSz //table size 1203 * SwChnlCmdID CmdID //command ID to set 1204 * u32 Para1 1205 * u32 Para2 1206 * u32 msDelay 1207 * output: 1208 * return: true if finished, false otherwise 1209 * notice: 1210 ******************************************************************************/ 1211 static u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx, 1212 u32 CmdTableSz, SwChnlCmdID CmdID, 1213 u32 Para1, u32 Para2, u32 msDelay) 1214 { 1215 SwChnlCmd *pCmd; 1216 1217 if (CmdTable == NULL) { 1218 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__); 1219 return false; 1220 } 1221 if (CmdTableIdx >= CmdTableSz) { 1222 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", 1223 __func__, CmdTableIdx, CmdTableSz); 1224 return false; 1225 } 1226 1227 pCmd = CmdTable + CmdTableIdx; 1228 pCmd->CmdID = CmdID; 1229 pCmd->Para1 = Para1; 1230 pCmd->Para2 = Para2; 1231 pCmd->msDelay = msDelay; 1232 1233 return true; 1234 } 1235 1236 /****************************************************************************** 1237 * function: This function sets channel step by step 1238 * input: net_device *dev 1239 * u8 channel 1240 * u8 *stage //3 stages 1241 * u8 *step 1242 * u32 *delay //whether need to delay 1243 * output: store new stage, step and delay for next step 1244 * (combine with function above) 1245 * return: true if finished, false otherwise 1246 * notice: Wait for simpler function to replace it 1247 *****************************************************************************/ 1248 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, 1249 u8 *stage, u8 *step, u32 *delay) 1250 { 1251 struct r8192_priv *priv = ieee80211_priv(dev); 1252 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; 1253 u32 PreCommonCmdCnt; 1254 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; 1255 u32 PostCommonCmdCnt; 1256 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; 1257 u32 RfDependCmdCnt; 1258 SwChnlCmd *CurrentCmd = NULL; 1259 u8 eRFPath; 1260 1261 RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n", 1262 __func__, *stage, *step, channel); 1263 if (!IsLegalChannel(priv->ieee80211, channel)) { 1264 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel); 1265 /* return true to tell upper caller function this channel 1266 setting is finished! Or it will in while loop. */ 1267 return true; 1268 } 1269 /* FIXME: need to check whether channel is legal or not here */ 1270 1271 1272 /* <1> Fill up pre common command. */ 1273 PreCommonCmdCnt = 0; 1274 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, 1275 MAX_PRECMD_CNT, CmdID_SetTxPowerLevel, 1276 0, 0, 0); 1277 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, 1278 MAX_PRECMD_CNT, CmdID_End, 0, 0, 0); 1279 1280 /* <2> Fill up post common command. */ 1281 PostCommonCmdCnt = 0; 1282 1283 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, 1284 MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0); 1285 1286 /* <3> Fill up RF dependent command. */ 1287 RfDependCmdCnt = 0; 1288 switch (priv->rf_chip) { 1289 case RF_8225: 1290 if (!(channel >= 1 && channel <= 14)) { 1291 RT_TRACE(COMP_ERR, 1292 "illegal channel for Zebra 8225: %d\n", 1293 channel); 1294 return true; 1295 } 1296 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1297 MAX_RFDEPENDCMD_CNT, 1298 CmdID_RF_WriteReg, 1299 rZebra1_Channel, 1300 RF_CHANNEL_TABLE_ZEBRA[channel], 1301 10); 1302 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1303 MAX_RFDEPENDCMD_CNT, 1304 CmdID_End, 0, 0, 0); 1305 break; 1306 1307 case RF_8256: 1308 /* TEST!! This is not the table for 8256!! */ 1309 if (!(channel >= 1 && channel <= 14)) { 1310 RT_TRACE(COMP_ERR, 1311 "illegal channel for Zebra 8256: %d\n", 1312 channel); 1313 return true; 1314 } 1315 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1316 MAX_RFDEPENDCMD_CNT, 1317 CmdID_RF_WriteReg, 1318 rZebra1_Channel, channel, 10); 1319 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1320 MAX_RFDEPENDCMD_CNT, 1321 CmdID_End, 0, 0, 0); 1322 break; 1323 1324 case RF_8258: 1325 break; 1326 1327 default: 1328 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); 1329 return true; 1330 } 1331 1332 1333 do { 1334 switch (*stage) { 1335 case 0: 1336 CurrentCmd = &PreCommonCmd[*step]; 1337 break; 1338 case 1: 1339 CurrentCmd = &RfDependCmd[*step]; 1340 break; 1341 case 2: 1342 CurrentCmd = &PostCommonCmd[*step]; 1343 break; 1344 } 1345 1346 if (CurrentCmd->CmdID == CmdID_End) { 1347 if ((*stage) == 2) { 1348 (*delay) = CurrentCmd->msDelay; 1349 return true; 1350 } 1351 (*stage)++; 1352 (*step) = 0; 1353 continue; 1354 } 1355 1356 switch (CurrentCmd->CmdID) { 1357 case CmdID_SetTxPowerLevel: 1358 if (priv->card_8192_version == (u8)VERSION_819xU_A) 1359 /* consider it later! */ 1360 rtl8192_SetTxPowerLevel(dev, channel); 1361 break; 1362 case CmdID_WritePortUlong: 1363 write_nic_dword(dev, CurrentCmd->Para1, 1364 CurrentCmd->Para2); 1365 break; 1366 case CmdID_WritePortUshort: 1367 write_nic_word(dev, CurrentCmd->Para1, 1368 (u16)CurrentCmd->Para2); 1369 break; 1370 case CmdID_WritePortUchar: 1371 write_nic_byte(dev, CurrentCmd->Para1, 1372 (u8)CurrentCmd->Para2); 1373 break; 1374 case CmdID_RF_WriteReg: 1375 for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) { 1376 rtl8192_phy_SetRFReg(dev, 1377 (RF90_RADIO_PATH_E)eRFPath, 1378 CurrentCmd->Para1, 1379 bZebra1_ChannelNum, 1380 CurrentCmd->Para2); 1381 } 1382 break; 1383 default: 1384 break; 1385 } 1386 1387 break; 1388 } while (true); 1389 1390 (*delay) = CurrentCmd->msDelay; 1391 (*step)++; 1392 return false; 1393 } 1394 1395 /****************************************************************************** 1396 * function: This function does actually set channel work 1397 * input: net_device *dev 1398 * u8 channel 1399 * output: none 1400 * return: none 1401 * notice: We should not call this function directly 1402 *****************************************************************************/ 1403 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) 1404 { 1405 struct r8192_priv *priv = ieee80211_priv(dev); 1406 u32 delay = 0; 1407 1408 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage, 1409 &priv->SwChnlStep, &delay)) { 1410 if (!priv->up) 1411 break; 1412 } 1413 } 1414 1415 /****************************************************************************** 1416 * function: Callback routine of the work item for switch channel. 1417 * input: net_device *dev 1418 * 1419 * output: none 1420 * return: none 1421 *****************************************************************************/ 1422 void rtl8192_SwChnl_WorkItem(struct net_device *dev) 1423 { 1424 1425 struct r8192_priv *priv = ieee80211_priv(dev); 1426 1427 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", 1428 priv->chan); 1429 1430 1431 rtl8192_phy_FinishSwChnlNow(dev, priv->chan); 1432 1433 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n"); 1434 } 1435 1436 /****************************************************************************** 1437 * function: This function scheduled actual work item to set channel 1438 * input: net_device *dev 1439 * u8 channel //channel to set 1440 * output: none 1441 * return: return code show if workitem is scheduled (1:pass, 0:fail) 1442 * notice: Delay may be required for RF configuration 1443 ******************************************************************************/ 1444 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) 1445 { 1446 struct r8192_priv *priv = ieee80211_priv(dev); 1447 1448 RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__, 1449 priv->SwChnlInProgress); 1450 if (!priv->up) 1451 return false; 1452 if (priv->SwChnlInProgress) 1453 return false; 1454 1455 /* -------------------------------------------- */ 1456 switch (priv->ieee80211->mode) { 1457 case WIRELESS_MODE_A: 1458 case WIRELESS_MODE_N_5G: 1459 if (channel <= 14) { 1460 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n"); 1461 return false; 1462 } 1463 break; 1464 case WIRELESS_MODE_B: 1465 if (channel > 14) { 1466 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n"); 1467 return false; 1468 } 1469 break; 1470 case WIRELESS_MODE_G: 1471 case WIRELESS_MODE_N_24G: 1472 if (channel > 14) { 1473 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n"); 1474 return false; 1475 } 1476 break; 1477 } 1478 /* -------------------------------------------- */ 1479 1480 priv->SwChnlInProgress = true; 1481 if (channel == 0) 1482 channel = 1; 1483 1484 priv->chan = channel; 1485 1486 priv->SwChnlStage = 0; 1487 priv->SwChnlStep = 0; 1488 if (priv->up) 1489 rtl8192_SwChnl_WorkItem(dev); 1490 1491 priv->SwChnlInProgress = false; 1492 return true; 1493 } 1494 1495 /****************************************************************************** 1496 * function: Callback routine of the work item for set bandwidth mode. 1497 * input: net_device *dev 1498 * output: none 1499 * return: none 1500 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can 1501 * test whether current work in the queue or not.//do I? 1502 *****************************************************************************/ 1503 void rtl8192_SetBWModeWorkItem(struct net_device *dev) 1504 { 1505 1506 struct r8192_priv *priv = ieee80211_priv(dev); 1507 u8 regBwOpMode; 1508 1509 RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__, 1510 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); 1511 1512 1513 if (priv->rf_chip == RF_PSEUDO_11N) { 1514 priv->SetBWModeInProgress = false; 1515 return; 1516 } 1517 1518 /* <1> Set MAC register */ 1519 read_nic_byte(dev, BW_OPMODE, ®BwOpMode); 1520 1521 switch (priv->CurrentChannelBW) { 1522 case HT_CHANNEL_WIDTH_20: 1523 regBwOpMode |= BW_OPMODE_20MHZ; 1524 /* We have not verify whether this register works */ 1525 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 1526 break; 1527 1528 case HT_CHANNEL_WIDTH_20_40: 1529 regBwOpMode &= ~BW_OPMODE_20MHZ; 1530 /* We have not verify whether this register works */ 1531 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 1532 break; 1533 1534 default: 1535 RT_TRACE(COMP_ERR, 1536 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", 1537 priv->CurrentChannelBW); 1538 break; 1539 } 1540 1541 /* <2> Set PHY related register */ 1542 switch (priv->CurrentChannelBW) { 1543 case HT_CHANNEL_WIDTH_20: 1544 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); 1545 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); 1546 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 1547 0x00100000, 1); 1548 1549 /* Correct the tx power for CCK rate in 20M. */ 1550 priv->cck_present_attentuation = 1551 priv->cck_present_attentuation_20Mdefault + 1552 priv->cck_present_attentuation_difference; 1553 1554 if (priv->cck_present_attentuation > 22) 1555 priv->cck_present_attentuation = 22; 1556 if (priv->cck_present_attentuation < 0) 1557 priv->cck_present_attentuation = 0; 1558 RT_TRACE(COMP_INIT, 1559 "20M, pHalData->CCKPresentAttentuation = %d\n", 1560 priv->cck_present_attentuation); 1561 1562 if (priv->chan == 14 && !priv->bcck_in_ch14) { 1563 priv->bcck_in_ch14 = true; 1564 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1565 } else if (priv->chan != 14 && priv->bcck_in_ch14) { 1566 priv->bcck_in_ch14 = false; 1567 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1568 } else { 1569 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1570 } 1571 1572 break; 1573 case HT_CHANNEL_WIDTH_20_40: 1574 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); 1575 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); 1576 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, 1577 priv->nCur40MhzPrimeSC>>1); 1578 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 1579 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, 1580 priv->nCur40MhzPrimeSC); 1581 priv->cck_present_attentuation = 1582 priv->cck_present_attentuation_40Mdefault + 1583 priv->cck_present_attentuation_difference; 1584 1585 if (priv->cck_present_attentuation > 22) 1586 priv->cck_present_attentuation = 22; 1587 if (priv->cck_present_attentuation < 0) 1588 priv->cck_present_attentuation = 0; 1589 1590 RT_TRACE(COMP_INIT, 1591 "40M, pHalData->CCKPresentAttentuation = %d\n", 1592 priv->cck_present_attentuation); 1593 if (priv->chan == 14 && !priv->bcck_in_ch14) { 1594 priv->bcck_in_ch14 = true; 1595 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1596 } else if (priv->chan != 14 && priv->bcck_in_ch14) { 1597 priv->bcck_in_ch14 = false; 1598 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1599 } else { 1600 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1601 } 1602 1603 break; 1604 default: 1605 RT_TRACE(COMP_ERR, 1606 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", 1607 priv->CurrentChannelBW); 1608 break; 1609 1610 } 1611 /* Skip over setting of J-mode in BB register here. 1612 Default value is "None J mode". */ 1613 1614 /* <3> Set RF related register */ 1615 switch (priv->rf_chip) { 1616 case RF_8225: 1617 #ifdef TO_DO_LIST 1618 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); 1619 #endif 1620 break; 1621 1622 case RF_8256: 1623 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); 1624 break; 1625 1626 case RF_8258: 1627 break; 1628 1629 case RF_PSEUDO_11N: 1630 break; 1631 1632 default: 1633 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); 1634 break; 1635 } 1636 priv->SetBWModeInProgress = false; 1637 1638 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n", 1639 atomic_read(&priv->ieee80211->atm_swbw)); 1640 } 1641 1642 /****************************************************************************** 1643 * function: This function schedules bandwidth switch work. 1644 * input: struct net_deviceq *dev 1645 * HT_CHANNEL_WIDTH bandwidth //20M or 40M 1646 * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care 1647 * output: none 1648 * return: none 1649 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can 1650 * test whether current work in the queue or not.//do I? 1651 *****************************************************************************/ 1652 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth, 1653 HT_EXTCHNL_OFFSET offset) 1654 { 1655 struct r8192_priv *priv = ieee80211_priv(dev); 1656 1657 if (priv->SetBWModeInProgress) 1658 return; 1659 priv->SetBWModeInProgress = true; 1660 1661 priv->CurrentChannelBW = bandwidth; 1662 1663 if (offset == HT_EXTCHNL_OFFSET_LOWER) 1664 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; 1665 else if (offset == HT_EXTCHNL_OFFSET_UPPER) 1666 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; 1667 else 1668 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; 1669 1670 rtl8192_SetBWModeWorkItem(dev); 1671 1672 } 1673 1674 void InitialGain819xUsb(struct net_device *dev, u8 Operation) 1675 { 1676 struct r8192_priv *priv = ieee80211_priv(dev); 1677 1678 priv->InitialGainOperateType = Operation; 1679 1680 if (priv->up) 1681 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0); 1682 } 1683 1684 void InitialGainOperateWorkItemCallBack(struct work_struct *work) 1685 { 1686 struct delayed_work *dwork = to_delayed_work(work); 1687 struct r8192_priv *priv = container_of(dwork, struct r8192_priv, 1688 initialgain_operate_wq); 1689 struct net_device *dev = priv->ieee80211->dev; 1690 #define SCAN_RX_INITIAL_GAIN 0x17 1691 #define POWER_DETECTION_TH 0x08 1692 u32 bitmask; 1693 u8 initial_gain; 1694 u8 Operation; 1695 1696 Operation = priv->InitialGainOperateType; 1697 1698 switch (Operation) { 1699 case IG_Backup: 1700 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); 1701 initial_gain = SCAN_RX_INITIAL_GAIN; 1702 bitmask = bMaskByte0; 1703 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1704 /* FW DIG OFF */ 1705 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); 1706 priv->initgain_backup.xaagccore1 = 1707 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask); 1708 priv->initgain_backup.xbagccore1 = 1709 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask); 1710 priv->initgain_backup.xcagccore1 = 1711 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask); 1712 priv->initgain_backup.xdagccore1 = 1713 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask); 1714 bitmask = bMaskByte2; 1715 priv->initgain_backup.cca = 1716 (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask); 1717 1718 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n", 1719 priv->initgain_backup.xaagccore1); 1720 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n", 1721 priv->initgain_backup.xbagccore1); 1722 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n", 1723 priv->initgain_backup.xcagccore1); 1724 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n", 1725 priv->initgain_backup.xdagccore1); 1726 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n", 1727 priv->initgain_backup.cca); 1728 1729 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", 1730 initial_gain); 1731 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 1732 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); 1733 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); 1734 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); 1735 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", 1736 POWER_DETECTION_TH); 1737 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); 1738 break; 1739 case IG_Restore: 1740 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); 1741 bitmask = 0x7f; /* Bit0 ~ Bit6 */ 1742 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1743 /* FW DIG OFF */ 1744 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); 1745 1746 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask, 1747 (u32)priv->initgain_backup.xaagccore1); 1748 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask, 1749 (u32)priv->initgain_backup.xbagccore1); 1750 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask, 1751 (u32)priv->initgain_backup.xcagccore1); 1752 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask, 1753 (u32)priv->initgain_backup.xdagccore1); 1754 bitmask = bMaskByte2; 1755 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask, 1756 (u32)priv->initgain_backup.cca); 1757 1758 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n", 1759 priv->initgain_backup.xaagccore1); 1760 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n", 1761 priv->initgain_backup.xbagccore1); 1762 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n", 1763 priv->initgain_backup.xcagccore1); 1764 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n", 1765 priv->initgain_backup.xdagccore1); 1766 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n", 1767 priv->initgain_backup.cca); 1768 1769 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel); 1770 1771 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1772 /* FW DIG ON */ 1773 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); 1774 break; 1775 default: 1776 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); 1777 break; 1778 } 1779 } 1780