1 /***************************************************************************** 2 * Copyright(c) 2007, RealTEK Technology Inc. All Right Reserved. 3 * 4 * Module: Hal819xUsbDM.h (RTL8192 Header H File) 5 * 6 * 7 * Note: For dynamic control definition constant structure. 8 * 9 * 10 * Export: 11 * 12 * Abbrev: 13 * 14 * History: 15 * Data Who Remark 16 * 10/04/2007 MHC Create initial version. 17 * 18 *****************************************************************************/ 19 /* Check to see if the file has been included already. */ 20 #ifndef __R8192UDM_H__ 21 #define __R8192UDM_H__ 22 23 24 /*--------------------------Define Parameters-------------------------------*/ 25 #define DM_DIG_THRESH_HIGH 40 26 #define DM_DIG_THRESH_LOW 35 27 28 #define DM_DIG_HIGH_PWR_THRESH_HIGH 75 29 #define DM_DIG_HIGH_PWR_THRESH_LOW 70 30 31 #define BW_AUTO_SWITCH_HIGH_LOW 25 32 #define BW_AUTO_SWITCH_LOW_HIGH 30 33 34 #define DM_check_fsync_time_interval 500 35 36 37 #define DM_DIG_BACKOFF 12 38 #define DM_DIG_MAX 0x36 39 #define DM_DIG_MIN 0x1c 40 #define DM_DIG_MIN_Netcore 0x12 41 42 #define RxPathSelection_SS_TH_low 30 43 #define RxPathSelection_diff_TH 18 44 45 #define RateAdaptiveTH_High 50 46 #define RateAdaptiveTH_Low_20M 30 47 #define RateAdaptiveTH_Low_40M 10 48 #define VeryLowRSSI 15 49 #define CTSToSelfTHVal 30 50 51 /* defined by vivi, for tx power track */ 52 #define E_FOR_TX_POWER_TRACK 300 53 /* Dynamic Tx Power Control Threshold */ 54 #define TX_POWER_NEAR_FIELD_THRESH_HIGH 68 55 #define TX_POWER_NEAR_FIELD_THRESH_LOW 62 56 /* added by amy for atheros AP */ 57 #define TX_POWER_ATHEROAP_THRESH_HIGH 78 58 #define TX_POWER_ATHEROAP_THRESH_LOW 72 59 60 /* defined by vivi, for showing on UI */ 61 #define Current_Tx_Rate_Reg 0x1b8 62 #define Initial_Tx_Rate_Reg 0x1b9 63 #define Tx_Retry_Count_Reg 0x1ac 64 #define RegC38_TH 20 65 /*--------------------------Define Parameters-------------------------------*/ 66 67 68 /*------------------------------Define structure----------------------------*/ 69 /* 2007/10/04 MH Define upper and lower threshold of DIG enable or disable. */ 70 struct dig { 71 u8 dig_enable_flag; 72 u8 dig_algorithm; 73 u8 dbg_mode; 74 u8 dig_algorithm_switch; 75 76 long rssi_low_thresh; 77 long rssi_high_thresh; 78 79 long rssi_high_power_lowthresh; 80 long rssi_high_power_highthresh; 81 82 u8 dig_state; 83 u8 dig_highpwr_state; 84 u8 cur_connect_state; 85 u8 pre_connect_state; 86 87 u8 curpd_thstate; 88 u8 prepd_thstate; 89 u8 curcs_ratio_state; 90 u8 precs_ratio_state; 91 92 u32 pre_ig_value; 93 u32 cur_ig_value; 94 95 u8 backoff_val; 96 u8 rx_gain_range_max; 97 u8 rx_gain_range_min; 98 bool initialgain_lowerbound_state; 99 100 long rssi_val; 101 }; 102 103 typedef enum tag_dynamic_init_gain_state_definition { 104 DM_STA_DIG_OFF = 0, 105 DM_STA_DIG_ON, 106 DM_STA_DIG_MAX 107 } dm_dig_sta_e; 108 109 110 /* 2007/10/08 MH Define RATR state. */ 111 typedef enum tag_dynamic_ratr_state_definition { 112 DM_RATR_STA_HIGH = 0, 113 DM_RATR_STA_MIDDLE = 1, 114 DM_RATR_STA_LOW = 2, 115 DM_RATR_STA_MAX 116 } dm_ratr_sta_e; 117 118 /* 2007/10/11 MH Define DIG operation type. */ 119 typedef enum tag_dynamic_init_gain_operation_type_definition { 120 DIG_TYPE_THRESH_HIGH = 0, 121 DIG_TYPE_THRESH_LOW = 1, 122 DIG_TYPE_THRESH_HIGHPWR_HIGH = 2, 123 DIG_TYPE_THRESH_HIGHPWR_LOW = 3, 124 DIG_TYPE_DBG_MODE = 4, 125 DIG_TYPE_RSSI = 5, 126 DIG_TYPE_ALGORITHM = 6, 127 DIG_TYPE_BACKOFF = 7, 128 DIG_TYPE_PWDB_FACTOR = 8, 129 DIG_TYPE_RX_GAIN_MIN = 9, 130 DIG_TYPE_RX_GAIN_MAX = 10, 131 DIG_TYPE_ENABLE = 20, 132 DIG_TYPE_DISABLE = 30, 133 DIG_OP_TYPE_MAX 134 } dm_dig_op_e; 135 136 typedef enum tag_dig_algorithm_definition { 137 DIG_ALGO_BY_FALSE_ALARM = 0, 138 DIG_ALGO_BY_RSSI = 1, 139 DIG_ALGO_MAX 140 } dm_dig_alg_e; 141 142 typedef enum tag_dig_dbgmode_definition { 143 DIG_DBG_OFF = 0, 144 DIG_DBG_ON = 1, 145 DIG_DBG_MAX 146 } dm_dig_dbg_e; 147 148 typedef enum tag_dig_connect_definition { 149 DIG_DISCONNECT = 0, 150 DIG_CONNECT = 1, 151 DIG_CONNECT_MAX 152 } dm_dig_connect_e; 153 154 typedef enum tag_dig_packetdetection_threshold_definition { 155 DIG_PD_AT_LOW_POWER = 0, 156 DIG_PD_AT_NORMAL_POWER = 1, 157 DIG_PD_AT_HIGH_POWER = 2, 158 DIG_PD_MAX 159 } dm_dig_pd_th_e; 160 161 typedef enum tag_dig_cck_cs_ratio_state_definition { 162 DIG_CS_RATIO_LOWER = 0, 163 DIG_CS_RATIO_HIGHER = 1, 164 DIG_CS_MAX 165 } dm_dig_cs_ratio_e; 166 struct dynamic_rx_path_sel { 167 u8 Enable; 168 u8 DbgMode; 169 u8 cck_method; 170 u8 cck_Rx_path; 171 172 u8 SS_TH_low; 173 u8 diff_TH; 174 u8 disabledRF; 175 u8 reserved; 176 177 u8 rf_rssi[4]; 178 u8 rf_enable_rssi_th[4]; 179 long cck_pwdb_sta[4]; 180 }; 181 182 typedef enum tag_CCK_Rx_Path_Method_Definition { 183 CCK_Rx_Version_1 = 0, 184 CCK_Rx_Version_2 = 1, 185 CCK_Rx_Version_MAX 186 } DM_CCK_Rx_Path_Method; 187 188 typedef enum tag_DM_DbgMode_Definition { 189 DM_DBG_OFF = 0, 190 DM_DBG_ON = 1, 191 DM_DBG_MAX 192 } DM_DBG_E; 193 194 typedef struct tag_Tx_Config_Cmd_Format { 195 u32 Op; /* Command packet type. */ 196 u32 Length; /* Command packet length. */ 197 u32 Value; 198 } DCMD_TXCMD_T, *PDCMD_TXCMD_T; 199 /*------------------------------Define structure----------------------------*/ 200 201 202 /*------------------------Export global variable----------------------------*/ 203 extern struct dig dm_digtable; 204 extern u8 dm_shadow[16][256]; 205 extern struct dynamic_rx_path_sel DM_RxPathSelTable; 206 /*------------------------Export global variable----------------------------*/ 207 208 209 /*------------------------Export Marco Definition---------------------------*/ 210 211 /*------------------------Export Marco Definition---------------------------*/ 212 213 214 /*--------------------------Exported Function prototype---------------------*/ 215 void init_hal_dm(struct net_device *dev); 216 void deinit_hal_dm(struct net_device *dev); 217 void hal_dm_watchdog(struct net_device *dev); 218 void init_rate_adaptive(struct net_device *dev); 219 void dm_txpower_trackingcallback(struct work_struct *work); 220 void dm_restore_dynamic_mechanism_state(struct net_device *dev); 221 void dm_backup_dynamic_mechanism_state(struct net_device *dev); 222 void dm_change_dynamic_initgain_thresh(struct net_device *dev, 223 u32 dm_type, u32 dm_value); 224 void dm_force_tx_fw_info(struct net_device *dev, 225 u32 force_type, u32 force_value); 226 void dm_init_edca_turbo(struct net_device *dev); 227 void dm_rf_operation_test_callback(unsigned long data); 228 void dm_rf_pathcheck_workitemcallback(struct work_struct *work); 229 void dm_fsync_timer_callback(unsigned long data); 230 void dm_cck_txpower_adjust(struct net_device *dev, bool binch14); 231 void dm_shadow_init(struct net_device *dev); 232 void dm_initialize_txpower_tracking(struct net_device *dev); 233 /*--------------------------Exported Function prototype---------------------*/ 234 235 236 #endif /*__R8192UDM_H__ */ 237 238 239 /* End of r8192U_dm.h */ 240