1 /* 2 * This is part of rtl8187 OpenSource driver. 3 * Copyright (C) Andrea Merello 2004-2005 <andrea.merello@gmail.com> 4 * Released under the terms of GPL (General Public Licence) 5 * 6 * Parts of this driver are based on the GPL part of the 7 * official realtek driver 8 * 9 * Parts of this driver are based on the rtl8192 driver skeleton 10 * from Patric Schenke & Andres Salomon 11 * 12 * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver 13 * 14 * We want to thank the Authors of those projects and the Ndiswrapper 15 * project Authors. 16 */ 17 18 #ifndef R819xU_H 19 #define R819xU_H 20 21 #include <linux/module.h> 22 #include <linux/kernel.h> 23 #include <linux/ioport.h> 24 #include <linux/sched.h> 25 #include <linux/types.h> 26 #include <linux/slab.h> 27 #include <linux/netdevice.h> 28 #include <linux/usb.h> 29 #include <linux/etherdevice.h> 30 #include <linux/delay.h> 31 #include <linux/rtnetlink.h> 32 #include <linux/wireless.h> 33 #include <linux/timer.h> 34 #include <linux/proc_fs.h> 35 #include <linux/if_arp.h> 36 #include <linux/random.h> 37 #include <asm/io.h> 38 #include "ieee80211/ieee80211.h" 39 40 #define RTL8192U 41 #define RTL819xU_MODULE_NAME "rtl819xU" 42 /* HW security */ 43 #define FALSE 0 44 #define TRUE 1 45 #define MAX_KEY_LEN 61 46 #define KEY_BUF_SIZE 5 47 48 #define BIT0 0x00000001 49 #define BIT1 0x00000002 50 #define BIT2 0x00000004 51 #define BIT3 0x00000008 52 #define BIT4 0x00000010 53 #define BIT5 0x00000020 54 #define BIT6 0x00000040 55 #define BIT7 0x00000080 56 #define BIT8 0x00000100 57 #define BIT9 0x00000200 58 #define BIT10 0x00000400 59 #define BIT11 0x00000800 60 #define BIT12 0x00001000 61 #define BIT13 0x00002000 62 #define BIT14 0x00004000 63 #define BIT15 0x00008000 64 #define BIT16 0x00010000 65 #define BIT17 0x00020000 66 #define BIT18 0x00040000 67 #define BIT19 0x00080000 68 #define BIT20 0x00100000 69 #define BIT21 0x00200000 70 #define BIT22 0x00400000 71 #define BIT23 0x00800000 72 #define BIT24 0x01000000 73 #define BIT25 0x02000000 74 #define BIT26 0x04000000 75 #define BIT27 0x08000000 76 #define BIT28 0x10000000 77 #define BIT29 0x20000000 78 #define BIT30 0x40000000 79 #define BIT31 0x80000000 80 81 #define Rx_Smooth_Factor 20 82 #define DMESG(x, a...) 83 #define DMESGW(x, a...) 84 #define DMESGE(x, a...) 85 extern u32 rt_global_debug_component; 86 #define RT_TRACE(component, x, args...) \ 87 do { \ 88 if (rt_global_debug_component & component) \ 89 pr_debug("RTL8192U: " x "\n", ##args); \ 90 } while (0) 91 92 #define COMP_TRACE BIT0 /* Function call tracing. */ 93 #define COMP_DBG BIT1 94 #define COMP_INIT BIT2 /* Driver initialization/halt/reset. */ 95 96 97 #define COMP_RECV BIT3 /* Receive data path. */ 98 #define COMP_SEND BIT4 /* Send data path. */ 99 #define COMP_IO BIT5 100 /* 802.11 Power Save mode or System/Device Power state. */ 101 #define COMP_POWER BIT6 102 /* 802.11 link related: join/start BSS, leave BSS. */ 103 #define COMP_EPROM BIT7 104 #define COMP_SWBW BIT8 /* Bandwidth switch. */ 105 #define COMP_POWER_TRACKING BIT9 /* 8190 TX Power Tracking */ 106 #define COMP_TURBO BIT10 /* Turbo Mode */ 107 #define COMP_QOS BIT11 108 #define COMP_RATE BIT12 /* Rate Adaptive mechanism */ 109 #define COMP_RM BIT13 /* Radio Measurement */ 110 #define COMP_DIG BIT14 111 #define COMP_PHY BIT15 112 #define COMP_CH BIT16 /* Channel setting debug */ 113 #define COMP_TXAGC BIT17 /* Tx power */ 114 #define COMP_HIPWR BIT18 /* High Power Mechanism */ 115 #define COMP_HALDM BIT19 /* HW Dynamic Mechanism */ 116 #define COMP_SEC BIT20 /* Event handling */ 117 #define COMP_LED BIT21 118 #define COMP_RF BIT22 119 #define COMP_RXDESC BIT23 /* Rx desc information for SD3 debug */ 120 121 /* 11n or 8190 specific code */ 122 123 #define COMP_FIRMWARE BIT24 /* Firmware downloading */ 124 #define COMP_HT BIT25 /* 802.11n HT related information */ 125 #define COMP_AMSDU BIT26 /* A-MSDU Debugging */ 126 #define COMP_SCAN BIT27 127 #define COMP_DOWN BIT29 /* rm driver module */ 128 #define COMP_RESET BIT30 /* Silent reset */ 129 #define COMP_ERR BIT31 /* Error out, always on */ 130 131 #define RTL819x_DEBUG 132 #ifdef RTL819x_DEBUG 133 #define RTL8192U_ASSERT(expr) \ 134 do { \ 135 if (!(expr)) { \ 136 pr_debug("Assertion failed! %s, %s, %s, line = %d\n", \ 137 #expr, __FILE__, __func__, __LINE__); \ 138 } \ 139 } while (0) 140 /* 141 * Debug out data buf. 142 * If you want to print DATA buffer related BA, 143 * please set ieee80211_debug_level to DATA|BA 144 */ 145 #define RT_DEBUG_DATA(level, data, datalen) \ 146 do { \ 147 if ((rt_global_debug_component & (level)) == (level)) { \ 148 int i; \ 149 u8 *pdata = (u8 *) data; \ 150 pr_debug("RTL8192U: %s()\n", __func__); \ 151 for (i = 0; i < (int)(datalen); i++) { \ 152 printk("%2x ", pdata[i]); \ 153 if ((i+1)%16 == 0) \ 154 printk("\n"); \ 155 } \ 156 printk("\n"); \ 157 } \ 158 } while (0) 159 #else 160 #define RTL8192U_ASSERT(expr) do {} while (0) 161 #define RT_DEBUG_DATA(level, data, datalen) do {} while (0) 162 #endif /* RTL8169_DEBUG */ 163 164 165 /* Queue Select Value in TxDesc */ 166 #define QSLT_BK 0x1 167 #define QSLT_BE 0x0 168 #define QSLT_VI 0x4 169 #define QSLT_VO 0x6 170 #define QSLT_BEACON 0x10 171 #define QSLT_HIGH 0x11 172 #define QSLT_MGNT 0x12 173 #define QSLT_CMD 0x13 174 175 #define DESC90_RATE1M 0x00 176 #define DESC90_RATE2M 0x01 177 #define DESC90_RATE5_5M 0x02 178 #define DESC90_RATE11M 0x03 179 #define DESC90_RATE6M 0x04 180 #define DESC90_RATE9M 0x05 181 #define DESC90_RATE12M 0x06 182 #define DESC90_RATE18M 0x07 183 #define DESC90_RATE24M 0x08 184 #define DESC90_RATE36M 0x09 185 #define DESC90_RATE48M 0x0a 186 #define DESC90_RATE54M 0x0b 187 #define DESC90_RATEMCS0 0x00 188 #define DESC90_RATEMCS1 0x01 189 #define DESC90_RATEMCS2 0x02 190 #define DESC90_RATEMCS3 0x03 191 #define DESC90_RATEMCS4 0x04 192 #define DESC90_RATEMCS5 0x05 193 #define DESC90_RATEMCS6 0x06 194 #define DESC90_RATEMCS7 0x07 195 #define DESC90_RATEMCS8 0x08 196 #define DESC90_RATEMCS9 0x09 197 #define DESC90_RATEMCS10 0x0a 198 #define DESC90_RATEMCS11 0x0b 199 #define DESC90_RATEMCS12 0x0c 200 #define DESC90_RATEMCS13 0x0d 201 #define DESC90_RATEMCS14 0x0e 202 #define DESC90_RATEMCS15 0x0f 203 #define DESC90_RATEMCS32 0x20 204 205 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R 206 207 #define IEEE80211_WATCH_DOG_TIME 2000 208 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10 209 /* For Tx Power Tracking */ 210 #define OFDM_Table_Length 19 211 #define CCK_Table_length 12 212 213 /* For rtl819x */ 214 typedef struct _tx_desc_819x_usb { 215 /* DWORD 0 */ 216 u16 PktSize; 217 u8 Offset; 218 u8 Reserved0:3; 219 u8 CmdInit:1; 220 u8 LastSeg:1; 221 u8 FirstSeg:1; 222 u8 LINIP:1; 223 u8 OWN:1; 224 225 /* DWORD 1 */ 226 u8 TxFWInfoSize; 227 u8 RATid:3; 228 u8 DISFB:1; 229 u8 USERATE:1; 230 u8 MOREFRAG:1; 231 u8 NoEnc:1; 232 u8 PIFS:1; 233 u8 QueueSelect:5; 234 u8 NoACM:1; 235 u8 Reserved1:2; 236 u8 SecCAMID:5; 237 u8 SecDescAssign:1; 238 u8 SecType:2; 239 240 /* DWORD 2 */ 241 u16 TxBufferSize; 242 u8 ResvForPaddingLen:7; 243 u8 Reserved3:1; 244 u8 Reserved4; 245 246 /* DWORD 3, 4, 5 */ 247 u32 Reserved5; 248 u32 Reserved6; 249 u32 Reserved7; 250 } tx_desc_819x_usb, *ptx_desc_819x_usb; 251 252 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE 253 typedef struct _tx_desc_819x_usb_aggr_subframe { 254 /* DWORD 0 */ 255 u16 PktSize; 256 u8 Offset; 257 u8 TxFWInfoSize; 258 259 /* DWORD 1 */ 260 u8 RATid:3; 261 u8 DISFB:1; 262 u8 USERATE:1; 263 u8 MOREFRAG:1; 264 u8 NoEnc:1; 265 u8 PIFS:1; 266 u8 QueueSelect:5; 267 u8 NoACM:1; 268 u8 Reserved1:2; 269 u8 SecCAMID:5; 270 u8 SecDescAssign:1; 271 u8 SecType:2; 272 u8 PacketID:7; 273 u8 OWN:1; 274 } tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe; 275 #endif 276 277 278 279 typedef struct _tx_desc_cmd_819x_usb { 280 /* DWORD 0 */ 281 u16 Reserved0; 282 u8 Reserved1; 283 u8 Reserved2:3; 284 u8 CmdInit:1; 285 u8 LastSeg:1; 286 u8 FirstSeg:1; 287 u8 LINIP:1; 288 u8 OWN:1; 289 290 /* DOWRD 1 */ 291 u8 TxFWInfoSize; 292 u8 Reserved3; 293 u8 QueueSelect; 294 u8 Reserved4; 295 296 /* DOWRD 2 */ 297 u16 TxBufferSize; 298 u16 Reserved5; 299 300 /* DWORD 3, 4, 5 */ 301 u32 Reserved6; 302 u32 Reserved7; 303 u32 Reserved8; 304 } tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb; 305 306 307 typedef struct _tx_fwinfo_819x_usb { 308 /* DOWRD 0 */ 309 u8 TxRate:7; 310 u8 CtsEnable:1; 311 u8 RtsRate:7; 312 u8 RtsEnable:1; 313 u8 TxHT:1; 314 u8 Short:1; /* Error out, always on */ 315 u8 TxBandwidth:1; /* Used for HT MCS rate only */ 316 u8 TxSubCarrier:2; /* Used for legacy OFDM rate only */ 317 u8 STBC:2; 318 u8 AllowAggregation:1; 319 /* Interpret RtsRate field as high throughput data rate */ 320 u8 RtsHT:1; 321 u8 RtsShort:1; /* Short PLCP for CCK or short GI for 11n MCS */ 322 u8 RtsBandwidth:1; /* Used for HT MCS rate only */ 323 u8 RtsSubcarrier:2;/* Used for legacy OFDM rate only */ 324 u8 RtsSTBC:2; 325 /* Enable firmware to recalculate and assign packet duration */ 326 u8 EnableCPUDur:1; 327 328 /* DWORD 1 */ 329 u32 RxMF:2; 330 u32 RxAMD:3; 331 /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */ 332 u32 TxPerPktInfoFeedback:1; 333 u32 Reserved1:2; 334 u32 TxAGCOffSet:4; 335 u32 TxAGCSign:1; 336 u32 Tx_INFO_RSVD:6; 337 u32 PacketID:13; 338 } tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb; 339 340 typedef struct rtl8192_rx_info { 341 struct urb *urb; 342 struct net_device *dev; 343 u8 out_pipe; 344 } rtl8192_rx_info ; 345 346 typedef struct rx_desc_819x_usb { 347 /* DOWRD 0 */ 348 u16 Length:14; 349 u16 CRC32:1; 350 u16 ICV:1; 351 u8 RxDrvInfoSize; 352 u8 Shift:2; 353 u8 PHYStatus:1; 354 u8 SWDec:1; 355 u8 Reserved1:4; 356 357 /* DWORD 1 */ 358 u32 Reserved2; 359 } rx_desc_819x_usb, *prx_desc_819x_usb; 360 361 #ifdef USB_RX_AGGREGATION_SUPPORT 362 typedef struct _rx_desc_819x_usb_aggr_subframe { 363 /* DOWRD 0 */ 364 u16 Length:14; 365 u16 CRC32:1; 366 u16 ICV:1; 367 u8 Offset; 368 u8 RxDrvInfoSize; 369 /* DOWRD 1 */ 370 u8 Shift:2; 371 u8 PHYStatus:1; 372 u8 SWDec:1; 373 u8 Reserved1:4; 374 u8 Reserved2; 375 u16 Reserved3; 376 } rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe; 377 #endif 378 379 typedef struct rx_drvinfo_819x_usb { 380 /* DWORD 0 */ 381 u16 Reserved1:12; 382 u16 PartAggr:1; 383 u16 FirstAGGR:1; 384 u16 Reserved2:2; 385 386 u8 RxRate:7; 387 u8 RxHT:1; 388 389 u8 BW:1; 390 u8 SPLCP:1; 391 u8 Reserved3:2; 392 u8 PAM:1; 393 u8 Mcast:1; 394 u8 Bcast:1; 395 u8 Reserved4:1; 396 397 /* DWORD 1 */ 398 u32 TSFL; 399 400 } rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb; 401 402 /* Support till 64 bit bus width OS */ 403 #define MAX_DEV_ADDR_SIZE 8 404 /* For RTL8190 */ 405 #define MAX_FIRMWARE_INFORMATION_SIZE 32 406 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE) 407 #define ENCRYPTION_MAX_OVERHEAD 128 408 #define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb) 409 #define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb)) 410 #define MAX_FRAGMENT_COUNT 8 411 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE 412 #define MAX_TRANSMIT_BUFFER_SIZE 32000 413 #else 414 #define MAX_TRANSMIT_BUFFER_SIZE 8000 415 #endif 416 #ifdef USB_TX_DRIVER_AGGREGATION_ENABLE 417 #define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb)) 418 #endif 419 /* Octets for crc32 (FCS, ICV) */ 420 #define scrclng 4 421 422 typedef enum rf_optype { 423 RF_OP_By_SW_3wire = 0, 424 RF_OP_By_FW, 425 RF_OP_MAX 426 } rf_op_type; 427 /* 8190 Loopback Mode definition */ 428 typedef enum _rtl819xUsb_loopback { 429 RTL819xU_NO_LOOPBACK = 0, 430 RTL819xU_MAC_LOOPBACK = 1, 431 RTL819xU_DMA_LOOPBACK = 2, 432 RTL819xU_CCK_LOOPBACK = 3, 433 } rtl819xUsb_loopback_e; 434 435 /* due to rtl8192 firmware */ 436 typedef enum _desc_packet_type_e { 437 DESC_PACKET_TYPE_INIT = 0, 438 DESC_PACKET_TYPE_NORMAL = 1, 439 } desc_packet_type_e; 440 441 typedef enum _firmware_status { 442 FW_STATUS_0_INIT = 0, 443 FW_STATUS_1_MOVE_BOOT_CODE = 1, 444 FW_STATUS_2_MOVE_MAIN_CODE = 2, 445 FW_STATUS_3_TURNON_CPU = 3, 446 FW_STATUS_4_MOVE_DATA_CODE = 4, 447 FW_STATUS_5_READY = 5, 448 } firmware_status_e; 449 450 typedef struct _rt_firmare_seg_container { 451 u16 seg_size; 452 u8 *seg_ptr; 453 } fw_seg_container, *pfw_seg_container; 454 typedef struct _rt_firmware { 455 firmware_status_e firmware_status; 456 u16 cmdpacket_frag_thresold; 457 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 458 u8 firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE]; 459 u16 firmware_buf_size; 460 } rt_firmware, *prt_firmware; 461 462 /* Add this to 9100 bytes to receive A-MSDU from RT-AP */ 463 #define MAX_RECEIVE_BUFFER_SIZE 9100 464 465 typedef struct _rt_firmware_info_819xUsb { 466 u8 sz_info[16]; 467 } rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb; 468 469 /* Firmware Queue Layout */ 470 #define NUM_OF_FIRMWARE_QUEUE 10 471 #define NUM_OF_PAGES_IN_FW 0x100 472 473 #ifdef USE_ONE_PIPE 474 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x000 475 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x000 476 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x0ff 477 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x000 478 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0 479 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x0 480 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x00 481 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0 482 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x0 483 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x00 484 #else 485 486 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x020 487 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x020 488 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x040 489 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x040 490 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0 491 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x4 492 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x20 493 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0 494 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4 495 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0x18 496 497 #endif 498 499 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000 500 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00 501 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08 502 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10 503 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18 504 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10 505 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08 506 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00 507 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08 508 509 /* 510 * ================================================================= 511 * ================================================================= 512 */ 513 514 #define EPROM_93c46 0 515 #define EPROM_93c56 1 516 517 #define DEFAULT_FRAG_THRESHOLD 2342U 518 #define MIN_FRAG_THRESHOLD 256U 519 #define DEFAULT_BEACONINTERVAL 0x64U 520 #define DEFAULT_BEACON_ESSID "Rtl819xU" 521 522 #define DEFAULT_SSID "" 523 #define DEFAULT_RETRY_RTS 7 524 #define DEFAULT_RETRY_DATA 7 525 #define PRISM_HDR_SIZE 64 526 527 #define PHY_RSSI_SLID_WIN_MAX 100 528 529 530 typedef enum _WIRELESS_MODE { 531 WIRELESS_MODE_UNKNOWN = 0x00, 532 WIRELESS_MODE_A = 0x01, 533 WIRELESS_MODE_B = 0x02, 534 WIRELESS_MODE_G = 0x04, 535 WIRELESS_MODE_AUTO = 0x08, 536 WIRELESS_MODE_N_24G = 0x10, 537 WIRELESS_MODE_N_5G = 0x20 538 } WIRELESS_MODE; 539 540 541 #define RTL_IOCTL_WPA_SUPPLICANT (SIOCIWFIRSTPRIV + 30) 542 543 typedef struct buffer { 544 struct buffer *next; 545 u32 *buf; 546 547 } buffer; 548 549 typedef struct rtl_reg_debug { 550 unsigned int cmd; 551 struct { 552 unsigned char type; 553 unsigned char addr; 554 unsigned char page; 555 unsigned char length; 556 } head; 557 unsigned char buf[0xff]; 558 } rtl_reg_debug; 559 560 561 562 563 564 565 typedef struct _rt_9x_tx_rate_history { 566 u32 cck[4]; 567 u32 ofdm[8]; 568 u32 ht_mcs[4][16]; 569 } rt_tx_rahis_t, *prt_tx_rahis_t; 570 typedef struct _RT_SMOOTH_DATA_4RF { 571 char elements[4][100]; /* array to store values */ 572 u32 index; /* index to current array to store */ 573 u32 TotalNum; /* num of valid elements */ 574 u32 TotalVal[4]; /* sum of valid elements */ 575 } RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF; 576 577 /* This maybe changed for D-cut larger aggregation size */ 578 #define MAX_8192U_RX_SIZE 8192 579 /* Stats seems messed up, clean it ASAP */ 580 typedef struct Stats { 581 unsigned long txrdu; 582 unsigned long rxok; 583 unsigned long rxframgment; 584 unsigned long rxurberr; 585 unsigned long rxstaterr; 586 /* 0: Total, 1: OK, 2: CRC, 3: ICV */ 587 unsigned long received_rate_histogram[4][32]; 588 /* 0: Long preamble/GI, 1: Short preamble/GI */ 589 unsigned long received_preamble_GI[2][32]; 590 /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */ 591 unsigned long rx_AMPDUsize_histogram[5]; 592 /* level: (<5), (5~10), (10~20), (20~40), (>40) */ 593 unsigned long rx_AMPDUnum_histogram[5]; 594 unsigned long numpacket_matchbssid; 595 unsigned long numpacket_toself; 596 unsigned long num_process_phyinfo; 597 unsigned long numqry_phystatus; 598 unsigned long numqry_phystatusCCK; 599 unsigned long numqry_phystatusHT; 600 /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */ 601 unsigned long received_bwtype[5]; 602 unsigned long txnperr; 603 unsigned long txnpdrop; 604 unsigned long txresumed; 605 unsigned long txnpokint; 606 unsigned long txoverflow; 607 unsigned long txlpokint; 608 unsigned long txlpdrop; 609 unsigned long txlperr; 610 unsigned long txbeokint; 611 unsigned long txbedrop; 612 unsigned long txbeerr; 613 unsigned long txbkokint; 614 unsigned long txbkdrop; 615 unsigned long txbkerr; 616 unsigned long txviokint; 617 unsigned long txvidrop; 618 unsigned long txvierr; 619 unsigned long txvookint; 620 unsigned long txvodrop; 621 unsigned long txvoerr; 622 unsigned long txbeaconokint; 623 unsigned long txbeacondrop; 624 unsigned long txbeaconerr; 625 unsigned long txmanageokint; 626 unsigned long txmanagedrop; 627 unsigned long txmanageerr; 628 unsigned long txdatapkt; 629 unsigned long txfeedback; 630 unsigned long txfeedbackok; 631 632 unsigned long txoktotal; 633 unsigned long txokbytestotal; 634 unsigned long txokinperiod; 635 unsigned long txmulticast; 636 unsigned long txbytesmulticast; 637 unsigned long txbroadcast; 638 unsigned long txbytesbroadcast; 639 unsigned long txunicast; 640 unsigned long txbytesunicast; 641 642 unsigned long rxoktotal; 643 unsigned long rxbytesunicast; 644 unsigned long txfeedbackfail; 645 unsigned long txerrtotal; 646 unsigned long txerrbytestotal; 647 unsigned long txerrmulticast; 648 unsigned long txerrbroadcast; 649 unsigned long txerrunicast; 650 unsigned long txretrycount; 651 unsigned long txfeedbackretry; 652 u8 last_packet_rate; 653 unsigned long slide_signal_strength[100]; 654 unsigned long slide_evm[100]; 655 /* For recording sliding window's RSSI value */ 656 unsigned long slide_rssi_total; 657 /* For recording sliding window's EVM value */ 658 unsigned long slide_evm_total; 659 /* Transformed in dbm. Beautified signal strength for UI, not correct */ 660 long signal_strength; 661 long signal_quality; 662 long last_signal_strength_inpercent; 663 /* Correct smoothed ss in dbm, only used in driver 664 * to report real power now */ 665 long recv_signal_power; 666 u8 rx_rssi_percentage[4]; 667 u8 rx_evm_percentage[2]; 668 long rxSNRdB[4]; 669 rt_tx_rahis_t txrate; 670 /* For beacon RSSI */ 671 u32 Slide_Beacon_pwdb[100]; 672 u32 Slide_Beacon_Total; 673 RT_SMOOTH_DATA_4RF cck_adc_pwdb; 674 675 u32 CurrentShowTxate; 676 } Stats; 677 678 679 /* Bandwidth Offset */ 680 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 681 #define HAL_PRIME_CHNL_OFFSET_LOWER 1 682 #define HAL_PRIME_CHNL_OFFSET_UPPER 2 683 684 685 typedef struct ChnlAccessSetting { 686 u16 SIFS_Timer; 687 u16 DIFS_Timer; 688 u16 SlotTimeTimer; 689 u16 EIFS_Timer; 690 u16 CWminIndex; 691 u16 CWmaxIndex; 692 } *PCHANNEL_ACCESS_SETTING, CHANNEL_ACCESS_SETTING; 693 694 typedef struct _BB_REGISTER_DEFINITION { 695 /* set software control: 0x870~0x877 [8 bytes] */ 696 u32 rfintfs; 697 /* readback data: 0x8e0~0x8e7 [8 bytes] */ 698 u32 rfintfi; 699 /* output data: 0x860~0x86f [16 bytes] */ 700 u32 rfintfo; 701 /* output enable: 0x860~0x86f [16 bytes] */ 702 u32 rfintfe; 703 /* LSSI data: 0x840~0x84f [16 bytes] */ 704 u32 rf3wireOffset; 705 /* BB Band Select: 0x878~0x87f [8 bytes] */ 706 u32 rfLSSI_Select; 707 /* Tx gain stage: 0x80c~0x80f [4 bytes] */ 708 u32 rfTxGainStage; 709 /* wire parameter control1: 0x820~0x823, 0x828~0x82b, 710 * 0x830~0x833, 0x838~0x83b [16 bytes] */ 711 u32 rfHSSIPara1; 712 /* wire parameter control2: 0x824~0x827, 0x82c~0x82f, 713 * 0x834~0x837, 0x83c~0x83f [16 bytes] */ 714 u32 rfHSSIPara2; 715 /* Tx Rx antenna control: 0x858~0x85f [16 bytes] */ 716 u32 rfSwitchControl; 717 /* AGC parameter control1: 0xc50~0xc53, 0xc58~0xc5b, 718 * 0xc60~0xc63, 0xc68~0xc6b [16 bytes] */ 719 u32 rfAGCControl1; 720 /* AGC parameter control2: 0xc54~0xc57, 0xc5c~0xc5f, 721 * 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] */ 722 u32 rfAGCControl2; 723 /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f, 724 * 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] */ 725 u32 rfRxIQImbalance; 726 /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter: 727 * 0xc10~0xc13, 0xc18~0xc1b, 728 * 0xc20~0xc23, 0xc28~0xc2b [16 bytes] */ 729 u32 rfRxAFE; 730 /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b, 731 * 0xc90~0xc93, 0xc98~0xc9b [16 bytes] */ 732 u32 rfTxIQImbalance; 733 /* Tx IQ DC Offset and Tx DFIR type: 734 * 0xc84~0xc87, 0xc8c~0xc8f, 735 * 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] */ 736 u32 rfTxAFE; 737 /* LSSI RF readback data: 0x8a0~0x8af [16 bytes] */ 738 u32 rfLSSIReadBack; 739 } BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; 740 741 typedef enum _RT_RF_TYPE_819xU { 742 RF_TYPE_MIN = 0, 743 RF_8225, 744 RF_8256, 745 RF_8258, 746 RF_PSEUDO_11N = 4, 747 } RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU; 748 749 typedef struct _rate_adaptive { 750 u8 rate_adaptive_disabled; 751 u8 ratr_state; 752 u16 reserve; 753 754 u32 high_rssi_thresh_for_ra; 755 u32 high2low_rssi_thresh_for_ra; 756 u8 low2high_rssi_thresh_for_ra40M; 757 u32 low_rssi_thresh_for_ra40M; 758 u8 low2high_rssi_thresh_for_ra20M; 759 u32 low_rssi_thresh_for_ra20M; 760 u32 upper_rssi_threshold_ratr; 761 u32 middle_rssi_threshold_ratr; 762 u32 low_rssi_threshold_ratr; 763 u32 low_rssi_threshold_ratr_40M; 764 u32 low_rssi_threshold_ratr_20M; 765 u8 ping_rssi_enable; 766 u32 ping_rssi_ratr; 767 u32 ping_rssi_thresh_for_ra; 768 u32 last_ratr; 769 770 } rate_adaptive, *prate_adaptive; 771 772 #define TxBBGainTableLength 37 773 #define CCKTxBBGainTableLength 23 774 775 typedef struct _txbbgain_struct { 776 long txbb_iq_amplifygain; 777 u32 txbbgain_value; 778 } txbbgain_struct, *ptxbbgain_struct; 779 780 typedef struct _ccktxbbgain_struct { 781 /* The value is from a22 to a29, one byte one time is much safer */ 782 u8 ccktxbb_valuearray[8]; 783 } ccktxbbgain_struct, *pccktxbbgain_struct; 784 785 786 typedef struct _init_gain { 787 u8 xaagccore1; 788 u8 xbagccore1; 789 u8 xcagccore1; 790 u8 xdagccore1; 791 u8 cca; 792 793 } init_gain, *pinit_gain; 794 795 typedef struct _phy_ofdm_rx_status_report_819xusb { 796 u8 trsw_gain_X[4]; 797 u8 pwdb_all; 798 u8 cfosho_X[4]; 799 u8 cfotail_X[4]; 800 u8 rxevm_X[2]; 801 u8 rxsnr_X[4]; 802 u8 pdsnr_X[2]; 803 u8 csi_current_X[2]; 804 u8 csi_target_X[2]; 805 u8 sigevm; 806 u8 max_ex_pwr; 807 u8 sgi_en; 808 u8 rxsc_sgien_exflg; 809 } phy_sts_ofdm_819xusb_t; 810 811 typedef struct _phy_cck_rx_status_report_819xusb { 812 /* For CCK rate descriptor. This is an unsigned 8:1 variable. 813 * LSB bit presend 0.5. And MSB 7 bts presend a signed value. 814 * Range from -64~+63.5. */ 815 u8 adc_pwdb_X[4]; 816 u8 sq_rpt; 817 u8 cck_agc_rpt; 818 } phy_sts_cck_819xusb_t; 819 820 821 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag { 822 u8 reserved:4; 823 u8 rxsc:2; 824 u8 sgi_en:1; 825 u8 ex_intf_flag:1; 826 } phy_ofdm_rx_status_rxsc_sgien_exintfflag; 827 828 typedef enum _RT_CUSTOMER_ID { 829 RT_CID_DEFAULT = 0, 830 RT_CID_8187_ALPHA0 = 1, 831 RT_CID_8187_SERCOMM_PS = 2, 832 RT_CID_8187_HW_LED = 3, 833 RT_CID_8187_NETGEAR = 4, 834 RT_CID_WHQL = 5, 835 RT_CID_819x_CAMEO = 6, 836 RT_CID_819x_RUNTOP = 7, 837 RT_CID_819x_Senao = 8, 838 RT_CID_TOSHIBA = 9, 839 RT_CID_819x_Netcore = 10, 840 RT_CID_Nettronix = 11, 841 RT_CID_DLINK = 12, 842 RT_CID_PRONET = 13, 843 } RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; 844 845 /* 846 * ========================================================================== 847 * LED customization. 848 * ========================================================================== 849 */ 850 851 typedef enum _LED_STRATEGY_8190 { 852 SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */ 853 SW_LED_MODE1, /* SW control for PCI Express */ 854 SW_LED_MODE2, /* SW control for Cameo. */ 855 SW_LED_MODE3, /* SW control for RunTop. */ 856 SW_LED_MODE4, /* SW control for Netcore. */ 857 /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */ 858 HW_LED, 859 } LED_STRATEGY_8190, *PLED_STRATEGY_8190; 860 861 typedef enum _RESET_TYPE { 862 RESET_TYPE_NORESET = 0x00, 863 RESET_TYPE_NORMAL = 0x01, 864 RESET_TYPE_SILENT = 0x02 865 } RESET_TYPE; 866 867 /* The simple tx command OP code. */ 868 typedef enum _tag_TxCmd_Config_Index { 869 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000, 870 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001, 871 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002, 872 TXCMD_SET_TX_DURATION = 0xFF900003, 873 TXCMD_SET_RX_RSSI = 0xFF900004, 874 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005, 875 TXCMD_XXXX_CTRL, 876 } DCMD_TXCMD_OP; 877 878 typedef struct r8192_priv { 879 struct usb_device *udev; 880 /* For maintain info from eeprom */ 881 short epromtype; 882 u16 eeprom_vid; 883 u16 eeprom_pid; 884 u8 eeprom_CustomerID; 885 u8 eeprom_ChannelPlan; 886 RT_CUSTOMER_ID CustomerID; 887 LED_STRATEGY_8190 LedStrategy; 888 u8 txqueue_to_outpipemap[9]; 889 int irq; 890 struct ieee80211_device *ieee80211; 891 892 /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */ 893 short card_8192; 894 /* If TCR reports card V B/C, this discriminates */ 895 u8 card_8192_version; 896 short enable_gpio0; 897 enum card_type { 898 PCI, MINIPCI, CARDBUS, USB 899 } card_type; 900 short hw_plcp_len; 901 short plcp_preamble_mode; 902 903 spinlock_t irq_lock; 904 spinlock_t tx_lock; 905 struct mutex mutex; 906 907 u16 irq_mask; 908 short chan; 909 short sens; 910 short max_sens; 911 912 913 short up; 914 /* If 1, allow bad crc frame, reception in monitor mode */ 915 short crcmon; 916 917 struct semaphore wx_sem; 918 struct semaphore rf_sem; /* Used to lock rf write operation */ 919 920 u8 rf_type; /* 0: 1T2R, 1: 2T4R */ 921 RT_RF_TYPE_819xU rf_chip; 922 923 short (*rf_set_sens)(struct net_device *dev, short sens); 924 u8 (*rf_set_chan)(struct net_device *dev, u8 ch); 925 void (*rf_close)(struct net_device *dev); 926 void (*rf_init)(struct net_device *dev); 927 short promisc; 928 /* Stats */ 929 struct Stats stats; 930 struct iw_statistics wstats; 931 932 /* RX stuff */ 933 struct urb **rx_urb; 934 struct urb **rx_cmd_urb; 935 #ifdef THOMAS_BEACON 936 u32 *oldaddr; 937 #endif 938 #ifdef THOMAS_TASKLET 939 atomic_t irt_counter; /* count for irq_rx_tasklet */ 940 #endif 941 #ifdef JACKSON_NEW_RX 942 struct sk_buff **pp_rxskb; 943 int rx_inx; 944 #endif 945 946 struct sk_buff_head rx_queue; 947 struct sk_buff_head skb_queue; 948 struct work_struct qos_activate; 949 short tx_urb_index; 950 atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */ 951 952 953 struct tasklet_struct irq_rx_tasklet; 954 struct urb *rxurb_task; 955 956 /* Tx Related variables */ 957 u16 ShortRetryLimit; 958 u16 LongRetryLimit; 959 u32 TransmitConfig; 960 u8 RegCWinMin; /* For turbo mode CW adaptive */ 961 962 u32 LastRxDescTSFHigh; 963 u32 LastRxDescTSFLow; 964 965 966 /* Rx Related variables */ 967 u16 EarlyRxThreshold; 968 u32 ReceiveConfig; 969 u8 AcmControl; 970 971 u8 RFProgType; 972 973 u8 retry_data; 974 u8 retry_rts; 975 u16 rts; 976 977 struct ChnlAccessSetting ChannelAccessSetting; 978 struct work_struct reset_wq; 979 980 /**********************************************************/ 981 /* For rtl819xUsb */ 982 u16 basic_rate; 983 u8 short_preamble; 984 u8 slot_time; 985 bool bDcut; 986 bool bCurrentRxAggrEnable; 987 u8 Rf_Mode; /* For Firmware RF -R/W switch */ 988 prt_firmware pFirmware; 989 rtl819xUsb_loopback_e LoopbackMode; 990 u16 EEPROMTxPowerDiff; 991 u8 EEPROMThermalMeter; 992 u8 EEPROMPwDiff; 993 u8 EEPROMCrystalCap; 994 u8 EEPROM_Def_Ver; 995 u8 EEPROMTxPowerLevelCCK; /* CCK channel 1~14 */ 996 u8 EEPROMTxPowerLevelCCK_V1[3]; 997 u8 EEPROMTxPowerLevelOFDM24G[3]; /* OFDM 2.4G channel 1~14 */ 998 u8 EEPROMTxPowerLevelOFDM5G[24]; /* OFDM 5G */ 999 1000 /* PHY related */ 1001 BB_REGISTER_DEFINITION_T PHYRegDef[4]; /* Radio A/B/C/D */ 1002 /* Read/write are allow for following hardware information variables */ 1003 u32 MCSTxPowerLevelOriginalOffset[6]; 1004 u32 CCKTxPowerLevelOriginalOffset; 1005 u8 TxPowerLevelCCK[14]; /* CCK channel 1~14 */ 1006 u8 TxPowerLevelOFDM24G[14]; /* OFDM 2.4G channel 1~14 */ 1007 u8 TxPowerLevelOFDM5G[14]; /* OFDM 5G */ 1008 u32 Pwr_Track; 1009 u8 TxPowerDiff; 1010 u8 AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */ 1011 u8 CrystalCap; 1012 u8 ThermalMeter[2]; /* index 0: RFIC0, index 1: RFIC1 */ 1013 1014 u8 CckPwEnl; 1015 /* Use to calculate PWBD */ 1016 u8 bCckHighPower; 1017 long undecorated_smoothed_pwdb; 1018 1019 /* For set channel */ 1020 u8 SwChnlInProgress; 1021 u8 SwChnlStage; 1022 u8 SwChnlStep; 1023 u8 SetBWModeInProgress; 1024 HT_CHANNEL_WIDTH CurrentChannelBW; 1025 u8 ChannelPlan; 1026 /* 8190 40MHz mode */ 1027 /* Control channel sub-carrier */ 1028 u8 nCur40MhzPrimeSC; 1029 /* Test for shorten RF configuration time. 1030 * We save RF reg0 in this variable to reduce RF reading. */ 1031 u32 RfReg0Value[4]; 1032 u8 NumTotalRFPath; 1033 bool brfpath_rxenable[4]; 1034 /* RF set related */ 1035 bool SetRFPowerStateInProgress; 1036 struct timer_list watch_dog_timer; 1037 1038 /* For dynamic mechanism */ 1039 /* Tx Power Control for Near/Far Range */ 1040 bool bdynamic_txpower; 1041 bool bDynamicTxHighPower; 1042 bool bDynamicTxLowPower; 1043 bool bLastDTPFlag_High; 1044 bool bLastDTPFlag_Low; 1045 1046 bool bstore_last_dtpflag; 1047 /* Define to discriminate on High power State or 1048 * on sitesurvey to change Tx gain index */ 1049 bool bstart_txctrl_bydtp; 1050 rate_adaptive rate_adaptive; 1051 /* TX power tracking 1052 * OPEN/CLOSE TX POWER TRACKING */ 1053 txbbgain_struct txbbgain_table[TxBBGainTableLength]; 1054 u8 txpower_count; /* For 6 sec do tracking again */ 1055 bool btxpower_trackingInit; 1056 u8 OFDM_index; 1057 u8 CCK_index; 1058 /* CCK TX Power Tracking */ 1059 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength]; 1060 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength]; 1061 u8 rfa_txpowertrackingindex; 1062 u8 rfa_txpowertrackingindex_real; 1063 u8 rfa_txpowertracking_default; 1064 u8 rfc_txpowertrackingindex; 1065 u8 rfc_txpowertrackingindex_real; 1066 1067 s8 cck_present_attentuation; 1068 u8 cck_present_attentuation_20Mdefault; 1069 u8 cck_present_attentuation_40Mdefault; 1070 char cck_present_attentuation_difference; 1071 bool btxpower_tracking; 1072 bool bcck_in_ch14; 1073 bool btxpowerdata_readfromEEPORM; 1074 u16 TSSI_13dBm; 1075 init_gain initgain_backup; 1076 u8 DefaultInitialGain[4]; 1077 /* For EDCA Turbo mode */ 1078 bool bis_any_nonbepkts; 1079 bool bcurrent_turbo_EDCA; 1080 bool bis_cur_rdlstate; 1081 struct timer_list fsync_timer; 1082 bool bfsync_processing; /* 500ms Fsync timer is active or not */ 1083 u32 rate_record; 1084 u32 rateCountDiffRecord; 1085 u32 ContinueDiffCount; 1086 bool bswitch_fsync; 1087 1088 u8 framesync; 1089 u32 framesyncC34; 1090 u8 framesyncMonitor; 1091 u16 nrxAMPDU_size; 1092 u8 nrxAMPDU_aggr_num; 1093 1094 /* For gpio */ 1095 bool bHwRadioOff; 1096 1097 u32 reset_count; 1098 bool bpbc_pressed; 1099 u32 txpower_checkcnt; 1100 u32 txpower_tracking_callback_cnt; 1101 u8 thermal_read_val[40]; 1102 u8 thermal_readback_index; 1103 u32 ccktxpower_adjustcnt_not_ch14; 1104 u32 ccktxpower_adjustcnt_ch14; 1105 u8 tx_fwinfo_force_subcarriermode; 1106 u8 tx_fwinfo_force_subcarrierval; 1107 /* For silent reset */ 1108 RESET_TYPE ResetProgress; 1109 bool bForcedSilentReset; 1110 bool bDisableNormalResetCheck; 1111 u16 TxCounter; 1112 u16 RxCounter; 1113 int IrpPendingCount; 1114 bool bResetInProgress; 1115 bool force_reset; 1116 u8 InitialGainOperateType; 1117 1118 u16 SifsTime; 1119 1120 /* Define work item */ 1121 1122 struct delayed_work update_beacon_wq; 1123 struct delayed_work watch_dog_wq; 1124 struct delayed_work txpower_tracking_wq; 1125 struct delayed_work rfpath_check_wq; 1126 struct delayed_work gpio_change_rf_wq; 1127 struct delayed_work initialgain_operate_wq; 1128 struct workqueue_struct *priv_wq; 1129 } r8192_priv; 1130 1131 /* For rtl8187B */ 1132 typedef enum{ 1133 BULK_PRIORITY = 0x01, 1134 LOW_PRIORITY, 1135 NORM_PRIORITY, 1136 VO_PRIORITY, 1137 VI_PRIORITY, 1138 BE_PRIORITY, 1139 BK_PRIORITY, 1140 RSVD2, 1141 RSVD3, 1142 BEACON_PRIORITY, 1143 HIGH_PRIORITY, 1144 MANAGE_PRIORITY, 1145 RSVD4, 1146 RSVD5, 1147 UART_PRIORITY 1148 } priority_t; 1149 1150 typedef enum { 1151 NIC_8192U = 1, 1152 NIC_8190P = 2, 1153 NIC_8192E = 3, 1154 } nic_t; 1155 1156 bool init_firmware(struct net_device *dev); 1157 short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb); 1158 short rtl8192_tx(struct net_device *dev, struct sk_buff *skb); 1159 1160 u32 read_cam(struct net_device *dev, u8 addr); 1161 void write_cam(struct net_device *dev, u8 addr, u32 data); 1162 1163 int read_nic_byte(struct net_device *dev, int x, u8 *data); 1164 int read_nic_byte_E(struct net_device *dev, int x, u8 *data); 1165 int read_nic_dword(struct net_device *dev, int x, u32 *data); 1166 int read_nic_word(struct net_device *dev, int x, u16 *data); 1167 void write_nic_byte(struct net_device *dev, int x, u8 y); 1168 void write_nic_byte_E(struct net_device *dev, int x, u8 y); 1169 void write_nic_word(struct net_device *dev, int x, u16 y); 1170 void write_nic_dword(struct net_device *dev, int x, u32 y); 1171 void force_pci_posting(struct net_device *dev); 1172 1173 void rtl8192_rtx_disable(struct net_device *); 1174 void rtl8192_rx_enable(struct net_device *); 1175 void rtl8192_tx_enable(struct net_device *); 1176 1177 void rtl8192_disassociate(struct net_device *dev); 1178 void rtl8185_set_rf_pins_enable(struct net_device *dev, u32 a); 1179 1180 void rtl8192_set_anaparam(struct net_device *dev, u32 a); 1181 void rtl8185_set_anaparam2(struct net_device *dev, u32 a); 1182 void rtl8192_update_msr(struct net_device *dev); 1183 int rtl8192_down(struct net_device *dev); 1184 int rtl8192_up(struct net_device *dev); 1185 void rtl8192_commit(struct net_device *dev); 1186 void rtl8192_set_chan(struct net_device *dev, short ch); 1187 void write_phy(struct net_device *dev, u8 adr, u8 data); 1188 void write_phy_cck(struct net_device *dev, u8 adr, u32 data); 1189 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data); 1190 void rtl8185_tx_antenna(struct net_device *dev, u8 ant); 1191 void rtl8192_set_rxconf(struct net_device *dev); 1192 extern void rtl819xusb_beacon_tx(struct net_device *dev, u16 tx_rate); 1193 1194 void EnableHWSecurityConfig8192(struct net_device *dev); 1195 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent); 1196 1197 1198 #endif 1199