18fc8598eSJerry Chuang /* 28fc8598eSJerry Chuang This is part of the rtl8192 driver 38fc8598eSJerry Chuang released under the GPL (See file COPYING for details). 48fc8598eSJerry Chuang 58fc8598eSJerry Chuang This files contains programming code for the rtl8256 68fc8598eSJerry Chuang radio frontend. 78fc8598eSJerry Chuang 88fc8598eSJerry Chuang *Many* thanks to Realtek Corp. for their great support! 98fc8598eSJerry Chuang 108fc8598eSJerry Chuang */ 118fc8598eSJerry Chuang 128fc8598eSJerry Chuang #include "r8192U.h" 138fc8598eSJerry Chuang #include "r8192U_hw.h" 148fc8598eSJerry Chuang #include "r819xU_phyreg.h" 158fc8598eSJerry Chuang #include "r819xU_phy.h" 168fc8598eSJerry Chuang #include "r8190_rtl8256.h" 178fc8598eSJerry Chuang 188fc8598eSJerry Chuang /*-------------------------------------------------------------------------- 198fc8598eSJerry Chuang * Overview: set RF band width (20M or 40M) 208fc8598eSJerry Chuang * Input: struct net_device* dev 218fc8598eSJerry Chuang * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M 228fc8598eSJerry Chuang * Output: NONE 238fc8598eSJerry Chuang * Return: NONE 248fc8598eSJerry Chuang * Note: 8226 support both 20M and 40 MHz 258fc8598eSJerry Chuang *---------------------------------------------------------------------------*/ 26104cb5c0SSanjeev Sharma void PHY_SetRF8256Bandwidth(struct net_device *dev , HT_CHANNEL_WIDTH Bandwidth) 278fc8598eSJerry Chuang { 288fc8598eSJerry Chuang u8 eRFPath; 298fc8598eSJerry Chuang struct r8192_priv *priv = ieee80211_priv(dev); 308fc8598eSJerry Chuang 31104cb5c0SSanjeev Sharma /* for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; 32104cb5c0SSanjeev Sharma * eRFPath++) 33104cb5c0SSanjeev Sharma */ 34104cb5c0SSanjeev Sharma for (eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) { 358fc8598eSJerry Chuang if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 368fc8598eSJerry Chuang continue; 378fc8598eSJerry Chuang 38104cb5c0SSanjeev Sharma switch (Bandwidth) { 398fc8598eSJerry Chuang case HT_CHANNEL_WIDTH_20: 40104cb5c0SSanjeev Sharma if (priv->card_8192_version == VERSION_819xU_A 41104cb5c0SSanjeev Sharma || priv->card_8192_version 42104cb5c0SSanjeev Sharma == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */ 43104cb5c0SSanjeev Sharma rtl8192_phy_SetRFReg(dev, 44104cb5c0SSanjeev Sharma (RF90_RADIO_PATH_E)eRFPath, 45104cb5c0SSanjeev Sharma 0x0b, bMask12Bits, 0x100); /* phy para:1ba */ 46104cb5c0SSanjeev Sharma rtl8192_phy_SetRFReg(dev, 47104cb5c0SSanjeev Sharma (RF90_RADIO_PATH_E)eRFPath, 48104cb5c0SSanjeev Sharma 0x2c, bMask12Bits, 0x3d7); 49104cb5c0SSanjeev Sharma rtl8192_phy_SetRFReg(dev, 50104cb5c0SSanjeev Sharma (RF90_RADIO_PATH_E)eRFPath, 51104cb5c0SSanjeev Sharma 0x0e, bMask12Bits, 0x021); 528fc8598eSJerry Chuang 53104cb5c0SSanjeev Sharma /* cosa add for sd3's request 01/23/2008 54104cb5c0SSanjeev Sharma */ 55104cb5c0SSanjeev Sharma rtl8192_phy_SetRFReg(dev, 56104cb5c0SSanjeev Sharma (RF90_RADIO_PATH_E)eRFPath, 57104cb5c0SSanjeev Sharma 0x14, bMask12Bits, 0x5ab); 58104cb5c0SSanjeev Sharma } else { 598fc8598eSJerry Chuang RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); 608fc8598eSJerry Chuang } 618fc8598eSJerry Chuang break; 628fc8598eSJerry Chuang case HT_CHANNEL_WIDTH_20_40: 63104cb5c0SSanjeev Sharma if (priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B) { /* 8256 D-cut, E-cut, xiong: consider it later! */ 648fc8598eSJerry Chuang rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba 658fc8598eSJerry Chuang rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df); 668fc8598eSJerry Chuang rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1); 678fc8598eSJerry Chuang 688fc8598eSJerry Chuang //cosa add for sd3's request 01/23/2008 69104cb5c0SSanjeev Sharma if (priv->chan == 3 || priv->chan == 9) 70104cb5c0SSanjeev Sharma //I need to set priv->chan whenever current channel changes 718fc8598eSJerry Chuang rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b); 728fc8598eSJerry Chuang else 738fc8598eSJerry Chuang rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab); 74104cb5c0SSanjeev Sharma } else { 758fc8598eSJerry Chuang RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n"); 768fc8598eSJerry Chuang } 778fc8598eSJerry Chuang break; 788fc8598eSJerry Chuang default: 798fc8598eSJerry Chuang RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n", Bandwidth); 808fc8598eSJerry Chuang break; 818fc8598eSJerry Chuang 828fc8598eSJerry Chuang } 838fc8598eSJerry Chuang } 848fc8598eSJerry Chuang } 858fc8598eSJerry Chuang /*-------------------------------------------------------------------------- 868fc8598eSJerry Chuang * Overview: Interface to config 8256 878fc8598eSJerry Chuang * Input: struct net_device* dev 888fc8598eSJerry Chuang * Output: NONE 898fc8598eSJerry Chuang * Return: NONE 908fc8598eSJerry Chuang *---------------------------------------------------------------------------*/ 918fc8598eSJerry Chuang void PHY_RF8256_Config(struct net_device *dev) 928fc8598eSJerry Chuang { 938fc8598eSJerry Chuang struct r8192_priv *priv = ieee80211_priv(dev); 948fc8598eSJerry Chuang // Initialize general global value 958fc8598eSJerry Chuang // 968fc8598eSJerry Chuang // TODO: Extend RF_PATH_C and RF_PATH_D in the future 978fc8598eSJerry Chuang priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH; 988fc8598eSJerry Chuang // Config BB and RF 998fc8598eSJerry Chuang phy_RF8256_Config_ParaFile(dev); 1008fc8598eSJerry Chuang } 1018fc8598eSJerry Chuang /*-------------------------------------------------------------------------- 1028fc8598eSJerry Chuang * Overview: Interface to config 8256 1038fc8598eSJerry Chuang * Input: struct net_device* dev 1048fc8598eSJerry Chuang * Output: NONE 1058fc8598eSJerry Chuang * Return: NONE 1068fc8598eSJerry Chuang *---------------------------------------------------------------------------*/ 1078fc8598eSJerry Chuang void phy_RF8256_Config_ParaFile(struct net_device *dev) 1088fc8598eSJerry Chuang { 1098fc8598eSJerry Chuang u32 u4RegValue = 0; 1108fc8598eSJerry Chuang //static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A; 1118fc8598eSJerry Chuang //static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B; 1128fc8598eSJerry Chuang //static s1Byte szRadioCFile[] = RTL819X_PHY_RADIO_C; 1138fc8598eSJerry Chuang //static s1Byte szRadioDFile[] = RTL819X_PHY_RADIO_D; 1148fc8598eSJerry Chuang u8 eRFPath; 1158fc8598eSJerry Chuang BB_REGISTER_DEFINITION_T *pPhyReg; 1168fc8598eSJerry Chuang struct r8192_priv *priv = ieee80211_priv(dev); 1178fc8598eSJerry Chuang u32 RegOffSetToBeCheck = 0x3; 1188fc8598eSJerry Chuang u32 RegValueToBeCheck = 0x7f1; 1198fc8598eSJerry Chuang u32 RF3_Final_Value = 0; 1208fc8598eSJerry Chuang u8 ConstRetryTimes = 5, RetryTimes = 5; 1218fc8598eSJerry Chuang u8 ret = 0; 1228fc8598eSJerry Chuang //3//----------------------------------------------------------------- 1238fc8598eSJerry Chuang //3// <2> Initialize RF 1248fc8598eSJerry Chuang //3//----------------------------------------------------------------- 125104cb5c0SSanjeev Sharma for (eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath < priv->NumTotalRFPath; eRFPath++) { 1268fc8598eSJerry Chuang if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 1278fc8598eSJerry Chuang continue; 1288fc8598eSJerry Chuang 1298fc8598eSJerry Chuang pPhyReg = &priv->PHYRegDef[eRFPath]; 1308fc8598eSJerry Chuang 1318fc8598eSJerry Chuang // Joseph test for shorten RF config 1328fc8598eSJerry Chuang // pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord); 1338fc8598eSJerry Chuang 1348fc8598eSJerry Chuang /*----Store original RFENV control type----*/ 135104cb5c0SSanjeev Sharma switch (eRFPath) { 1368fc8598eSJerry Chuang case RF90_PATH_A: 1378fc8598eSJerry Chuang case RF90_PATH_C: 1388fc8598eSJerry Chuang u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV); 1398fc8598eSJerry Chuang break; 1408fc8598eSJerry Chuang case RF90_PATH_B: 1418fc8598eSJerry Chuang case RF90_PATH_D: 1428fc8598eSJerry Chuang u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16); 1438fc8598eSJerry Chuang break; 1448fc8598eSJerry Chuang } 1458fc8598eSJerry Chuang 1468fc8598eSJerry Chuang /*----Set RF_ENV enable----*/ 1478fc8598eSJerry Chuang rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); 1488fc8598eSJerry Chuang 1498fc8598eSJerry Chuang /*----Set RF_ENV output high----*/ 1508fc8598eSJerry Chuang rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); 1518fc8598eSJerry Chuang 1528fc8598eSJerry Chuang /* Set bit number of Address and Data for RF register */ 1538fc8598eSJerry Chuang rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258 1548fc8598eSJerry Chuang rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ??? 1558fc8598eSJerry Chuang 1568fc8598eSJerry Chuang rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf); 1578fc8598eSJerry Chuang 1588fc8598eSJerry Chuang /*----Check RF block (for FPGA platform only)----*/ 1598fc8598eSJerry Chuang // TODO: this function should be removed on ASIC , Emily 2007.2.2 160104cb5c0SSanjeev Sharma if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath)) { 1618fc8598eSJerry Chuang RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath); 1628fc8598eSJerry Chuang goto phy_RF8256_Config_ParaFile_Fail; 1638fc8598eSJerry Chuang } 1648fc8598eSJerry Chuang 1658fc8598eSJerry Chuang RetryTimes = ConstRetryTimes; 1668fc8598eSJerry Chuang RF3_Final_Value = 0; 1678fc8598eSJerry Chuang /*----Initialize RF fom connfiguration file----*/ 168104cb5c0SSanjeev Sharma switch (eRFPath) { 1698fc8598eSJerry Chuang case RF90_PATH_A: 170104cb5c0SSanjeev Sharma while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { 1718fc8598eSJerry Chuang ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath); 1728fc8598eSJerry Chuang RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); 1738fc8598eSJerry Chuang RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); 1748fc8598eSJerry Chuang RetryTimes--; 1758fc8598eSJerry Chuang } 1768fc8598eSJerry Chuang break; 1778fc8598eSJerry Chuang case RF90_PATH_B: 178104cb5c0SSanjeev Sharma while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { 1798fc8598eSJerry Chuang ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath); 1808fc8598eSJerry Chuang RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); 1818fc8598eSJerry Chuang RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); 1828fc8598eSJerry Chuang RetryTimes--; 1838fc8598eSJerry Chuang } 1848fc8598eSJerry Chuang break; 1858fc8598eSJerry Chuang case RF90_PATH_C: 186104cb5c0SSanjeev Sharma while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { 1878fc8598eSJerry Chuang ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath); 1888fc8598eSJerry Chuang RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); 1898fc8598eSJerry Chuang RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); 1908fc8598eSJerry Chuang RetryTimes--; 1918fc8598eSJerry Chuang } 1928fc8598eSJerry Chuang break; 1938fc8598eSJerry Chuang case RF90_PATH_D: 194104cb5c0SSanjeev Sharma while (RF3_Final_Value != RegValueToBeCheck && RetryTimes != 0) { 1958fc8598eSJerry Chuang ret = rtl8192_phy_ConfigRFWithHeaderFile(dev, (RF90_RADIO_PATH_E)eRFPath); 1968fc8598eSJerry Chuang RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits); 1978fc8598eSJerry Chuang RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value); 1988fc8598eSJerry Chuang RetryTimes--; 1998fc8598eSJerry Chuang } 2008fc8598eSJerry Chuang break; 2018fc8598eSJerry Chuang } 2028fc8598eSJerry Chuang 2038fc8598eSJerry Chuang /*----Restore RFENV control type----*/; 204104cb5c0SSanjeev Sharma switch (eRFPath) { 2058fc8598eSJerry Chuang case RF90_PATH_A: 2068fc8598eSJerry Chuang case RF90_PATH_C: 2078fc8598eSJerry Chuang rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); 2088fc8598eSJerry Chuang break; 2098fc8598eSJerry Chuang case RF90_PATH_B: 2108fc8598eSJerry Chuang case RF90_PATH_D: 2118fc8598eSJerry Chuang rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); 2128fc8598eSJerry Chuang break; 2138fc8598eSJerry Chuang } 2148fc8598eSJerry Chuang 2158fc8598eSJerry Chuang if (ret) { 2168fc8598eSJerry Chuang RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath); 2178fc8598eSJerry Chuang goto phy_RF8256_Config_ParaFile_Fail; 2188fc8598eSJerry Chuang } 2198fc8598eSJerry Chuang 2208fc8598eSJerry Chuang } 2218fc8598eSJerry Chuang 2228fc8598eSJerry Chuang RT_TRACE(COMP_PHY, "PHY Initialization Success\n"); 2238fc8598eSJerry Chuang return; 2248fc8598eSJerry Chuang 2258fc8598eSJerry Chuang phy_RF8256_Config_ParaFile_Fail: 2268fc8598eSJerry Chuang RT_TRACE(COMP_ERR, "PHY Initialization failed\n"); 2278fc8598eSJerry Chuang } 2288fc8598eSJerry Chuang 2298fc8598eSJerry Chuang 2308fc8598eSJerry Chuang void PHY_SetRF8256CCKTxPower(struct net_device *dev, u8 powerlevel) 2318fc8598eSJerry Chuang { 2328fc8598eSJerry Chuang u32 TxAGC = 0; 2338fc8598eSJerry Chuang struct r8192_priv *priv = ieee80211_priv(dev); 2348fc8598eSJerry Chuang //modified by vivi, 20080109 2358fc8598eSJerry Chuang TxAGC = powerlevel; 2368fc8598eSJerry Chuang 237104cb5c0SSanjeev Sharma if (priv->bDynamicTxLowPower == TRUE) { 238104cb5c0SSanjeev Sharma //cosa 05/22/2008 for scan 2398fc8598eSJerry Chuang if (priv->CustomerID == RT_CID_819x_Netcore) 2408fc8598eSJerry Chuang TxAGC = 0x22; 2418fc8598eSJerry Chuang else 2428fc8598eSJerry Chuang TxAGC += priv->CckPwEnl; 2438fc8598eSJerry Chuang } 2448fc8598eSJerry Chuang 2458fc8598eSJerry Chuang if (TxAGC > 0x24) 2468fc8598eSJerry Chuang TxAGC = 0x24; 2478fc8598eSJerry Chuang rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); 2488fc8598eSJerry Chuang } 2498fc8598eSJerry Chuang 2508fc8598eSJerry Chuang 2518fc8598eSJerry Chuang void PHY_SetRF8256OFDMTxPower(struct net_device *dev, u8 powerlevel) 2528fc8598eSJerry Chuang { 2538fc8598eSJerry Chuang struct r8192_priv *priv = ieee80211_priv(dev); 2548fc8598eSJerry Chuang //Joseph TxPower for 8192 testing 2558fc8598eSJerry Chuang u32 writeVal, powerBase0, powerBase1, writeVal_tmp; 2568fc8598eSJerry Chuang u8 index = 0; 2578fc8598eSJerry Chuang u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; 2588fc8598eSJerry Chuang u8 byte0, byte1, byte2, byte3; 2598fc8598eSJerry Chuang 2608fc8598eSJerry Chuang powerBase0 = powerlevel + priv->TxPowerDiff; //OFDM rates 2618fc8598eSJerry Chuang powerBase0 = (powerBase0<<24) | (powerBase0<<16) | (powerBase0<<8) | powerBase0; 2628fc8598eSJerry Chuang powerBase1 = powerlevel; //MCS rates 2638fc8598eSJerry Chuang powerBase1 = (powerBase1<<24) | (powerBase1<<16) | (powerBase1<<8) | powerBase1; 2648fc8598eSJerry Chuang 265104cb5c0SSanjeev Sharma for (index = 0; index < 6; index++) { 2668fc8598eSJerry Chuang writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index < 2)?powerBase0:powerBase1); 2678fc8598eSJerry Chuang byte0 = (u8)(writeVal & 0x7f); 2688fc8598eSJerry Chuang byte1 = (u8)((writeVal & 0x7f00)>>8); 2698fc8598eSJerry Chuang byte2 = (u8)((writeVal & 0x7f0000)>>16); 2708fc8598eSJerry Chuang byte3 = (u8)((writeVal & 0x7f000000)>>24); 271104cb5c0SSanjeev Sharma 272104cb5c0SSanjeev Sharma if (byte0 > 0x24) 273104cb5c0SSanjeev Sharma /* Max power index = 0x24 */ 2748fc8598eSJerry Chuang byte0 = 0x24; 2758fc8598eSJerry Chuang if (byte1 > 0x24) 2768fc8598eSJerry Chuang byte1 = 0x24; 2778fc8598eSJerry Chuang if (byte2 > 0x24) 2788fc8598eSJerry Chuang byte2 = 0x24; 2798fc8598eSJerry Chuang if (byte3 > 0x24) 2808fc8598eSJerry Chuang byte3 = 0x24; 2818fc8598eSJerry Chuang 2828fc8598eSJerry Chuang //for tx power track 283104cb5c0SSanjeev Sharma if (index == 3) { 2848fc8598eSJerry Chuang writeVal_tmp = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0; 2858fc8598eSJerry Chuang priv->Pwr_Track = writeVal_tmp; 2868fc8598eSJerry Chuang } 2878fc8598eSJerry Chuang 288104cb5c0SSanjeev Sharma if (priv->bDynamicTxHighPower == TRUE) { 289104cb5c0SSanjeev Sharma /*Add by Jacken 2008/03/06 290104cb5c0SSanjeev Sharma *Emily, 20080613. Set low tx power for both MCS and legacy OFDM 291104cb5c0SSanjeev Sharma */ 2928fc8598eSJerry Chuang writeVal = 0x03030303; 293104cb5c0SSanjeev Sharma } else { 2948fc8598eSJerry Chuang writeVal = (byte3<<24) | (byte2<<16) | (byte1<<8) | byte0; 2958fc8598eSJerry Chuang } 2968fc8598eSJerry Chuang rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); 2978fc8598eSJerry Chuang } 2988fc8598eSJerry Chuang return; 2998fc8598eSJerry Chuang 3008fc8598eSJerry Chuang } 301