1 /****************************************************************************** 2 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 3 * 4 * This program is distributed in the hope that it will be useful, but WITHOUT 5 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 6 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 7 * more details. 8 * 9 * The full GNU General Public License is included in this distribution in the 10 * file called LICENSE. 11 * 12 * Contact Information: 13 * wlanfae <wlanfae@realtek.com> 14 *****************************************************************************/ 15 #ifndef _RTL819XU_HTTYPE_H_ 16 #define _RTL819XU_HTTYPE_H_ 17 18 #define MIMO_PS_STATIC 0 19 20 #define sHTCLng 4 21 22 enum ht_channel_width { 23 HT_CHANNEL_WIDTH_20 = 0, 24 HT_CHANNEL_WIDTH_20_40 = 1, 25 }; 26 27 enum ht_extchnl_offset { 28 HT_EXTCHNL_OFFSET_NO_EXT = 0, 29 HT_EXTCHNL_OFFSET_UPPER = 1, 30 HT_EXTCHNL_OFFSET_NO_DEF = 2, 31 HT_EXTCHNL_OFFSET_LOWER = 3, 32 }; 33 34 struct ht_capab_ele { 35 36 u8 AdvCoding:1; 37 u8 ChlWidth:1; 38 u8 MimoPwrSave:2; 39 u8 GreenField:1; 40 u8 ShortGI20Mhz:1; 41 u8 ShortGI40Mhz:1; 42 u8 TxSTBC:1; 43 u8 RxSTBC:2; 44 u8 DelayBA:1; 45 u8 MaxAMSDUSize:1; 46 u8 DssCCk:1; 47 u8 PSMP:1; 48 u8 Rsvd1:1; 49 u8 LSigTxopProtect:1; 50 51 u8 MaxRxAMPDUFactor:2; 52 u8 MPDUDensity:3; 53 u8 Rsvd2:3; 54 55 u8 MCS[16]; 56 57 58 u16 ExtHTCapInfo; 59 60 u8 TxBFCap[4]; 61 62 u8 ASCap; 63 64 } __packed; 65 66 67 struct ht_info_ele { 68 u8 ControlChl; 69 70 u8 ExtChlOffset:2; 71 u8 RecommemdedTxWidth:1; 72 u8 RIFS:1; 73 u8 PSMPAccessOnly:1; 74 u8 SrvIntGranularity:3; 75 76 u8 OptMode:2; 77 u8 NonGFDevPresent:1; 78 u8 Revd1:5; 79 u8 Revd2:8; 80 81 u8 Rsvd3:6; 82 u8 DualBeacon:1; 83 u8 DualCTSProtect:1; 84 85 u8 SecondaryBeacon:1; 86 u8 LSigTxopProtectFull:1; 87 u8 PcoActive:1; 88 u8 PcoPhase:1; 89 u8 Rsvd4:4; 90 91 u8 BasicMSC[16]; 92 } __packed; 93 94 enum ht_spec_ver { 95 HT_SPEC_VER_IEEE = 0, 96 HT_SPEC_VER_EWC = 1, 97 }; 98 99 enum ht_aggre_mode { 100 HT_AGG_AUTO = 0, 101 HT_AGG_FORCE_ENABLE = 1, 102 HT_AGG_FORCE_DISABLE = 2, 103 }; 104 105 106 struct rt_hi_throughput { 107 u8 bEnableHT; 108 u8 bCurrentHTSupport; 109 110 u8 bRegBW40MHz; 111 u8 bCurBW40MHz; 112 113 u8 bRegShortGI40MHz; 114 u8 bCurShortGI40MHz; 115 116 u8 bRegShortGI20MHz; 117 u8 bCurShortGI20MHz; 118 119 u8 bRegSuppCCK; 120 u8 bCurSuppCCK; 121 122 enum ht_spec_ver ePeerHTSpecVer; 123 124 125 struct ht_capab_ele SelfHTCap; 126 struct ht_info_ele SelfHTInfo; 127 128 u8 PeerHTCapBuf[32]; 129 u8 PeerHTInfoBuf[32]; 130 131 132 u8 bAMSDU_Support; 133 u16 nAMSDU_MaxSize; 134 u8 bCurrent_AMSDU_Support; 135 u16 nCurrent_AMSDU_MaxSize; 136 137 u8 bAMPDUEnable; 138 u8 bCurrentAMPDUEnable; 139 u8 AMPDU_Factor; 140 u8 CurrentAMPDUFactor; 141 u8 MPDU_Density; 142 u8 CurrentMPDUDensity; 143 144 enum ht_aggre_mode ForcedAMPDUMode; 145 u8 ForcedAMPDUFactor; 146 u8 ForcedMPDUDensity; 147 148 enum ht_aggre_mode ForcedAMSDUMode; 149 u16 ForcedAMSDUMaxSize; 150 151 u8 bForcedShortGI; 152 153 u8 CurrentOpMode; 154 155 u8 SelfMimoPs; 156 u8 PeerMimoPs; 157 158 enum ht_extchnl_offset CurSTAExtChnlOffset; 159 u8 bCurTxBW40MHz; 160 u8 PeerBandwidth; 161 162 u8 bSwBwInProgress; 163 u8 SwBwStep; 164 165 u8 bRegRT2RTAggregation; 166 u8 RT2RT_HT_Mode; 167 u8 bCurrentRT2RTAggregation; 168 u8 bCurrentRT2RTLongSlotTime; 169 u8 szRT2RTAggBuffer[10]; 170 171 u8 bRegRxReorderEnable; 172 u8 bCurRxReorderEnable; 173 u8 RxReorderWinSize; 174 u8 RxReorderPendingTime; 175 u16 RxReorderDropCounter; 176 177 u8 bIsPeerBcm; 178 179 u8 IOTPeer; 180 u32 IOTAction; 181 u8 IOTRaFunc; 182 183 u8 bWAIotBroadcom; 184 u8 WAIotTH; 185 186 u8 bAcceptAddbaReq; 187 } __packed; 188 189 struct bss_ht { 190 191 u8 bdSupportHT; 192 193 u8 bdHTCapBuf[32]; 194 u16 bdHTCapLen; 195 u8 bdHTInfoBuf[32]; 196 u16 bdHTInfoLen; 197 198 enum ht_spec_ver bdHTSpecVer; 199 enum ht_channel_width bdBandWidth; 200 201 u8 bdRT2RTAggregation; 202 u8 bdRT2RTLongSlotTime; 203 u8 RT2RT_HT_Mode; 204 u8 bdHT1R; 205 }; 206 207 extern u8 MCS_FILTER_ALL[16]; 208 extern u8 MCS_FILTER_1SS[16]; 209 210 #define RATE_ADPT_1SS_MASK 0xFF 211 #define RATE_ADPT_2SS_MASK 0xF0 212 #define RATE_ADPT_MCS32_MASK 0x01 213 214 enum ht_aggre_size { 215 HT_AGG_SIZE_8K = 0, 216 HT_AGG_SIZE_16K = 1, 217 HT_AGG_SIZE_32K = 2, 218 HT_AGG_SIZE_64K = 3, 219 }; 220 221 enum ht_iot_peer { 222 HT_IOT_PEER_UNKNOWN = 0, 223 HT_IOT_PEER_REALTEK = 1, 224 HT_IOT_PEER_REALTEK_92SE = 2, 225 HT_IOT_PEER_BROADCOM = 3, 226 HT_IOT_PEER_RALINK = 4, 227 HT_IOT_PEER_ATHEROS = 5, 228 HT_IOT_PEER_CISCO = 6, 229 HT_IOT_PEER_MARVELL = 7, 230 HT_IOT_PEER_92U_SOFTAP = 8, 231 HT_IOT_PEER_SELF_SOFTAP = 9, 232 HT_IOT_PEER_AIRGO = 10, 233 HT_IOT_PEER_MAX = 11, 234 }; 235 236 enum ht_iot_action { 237 HT_IOT_ACT_TX_USE_AMSDU_4K = 0x00000001, 238 HT_IOT_ACT_TX_USE_AMSDU_8K = 0x00000002, 239 HT_IOT_ACT_DISABLE_MCS14 = 0x00000004, 240 HT_IOT_ACT_DISABLE_MCS15 = 0x00000008, 241 HT_IOT_ACT_DISABLE_ALL_2SS = 0x00000010, 242 HT_IOT_ACT_DISABLE_EDCA_TURBO = 0x00000020, 243 HT_IOT_ACT_MGNT_USE_CCK_6M = 0x00000040, 244 HT_IOT_ACT_CDD_FSYNC = 0x00000080, 245 HT_IOT_ACT_PURE_N_MODE = 0x00000100, 246 HT_IOT_ACT_FORCED_CTS2SELF = 0x00000200, 247 HT_IOT_ACT_FORCED_RTS = 0x00000400, 248 HT_IOT_ACT_AMSDU_ENABLE = 0x00000800, 249 HT_IOT_ACT_REJECT_ADDBA_REQ = 0x00001000, 250 HT_IOT_ACT_ALLOW_PEER_AGG_ONE_PKT = 0x00002000, 251 HT_IOT_ACT_EDCA_BIAS_ON_RX = 0x00004000, 252 253 HT_IOT_ACT_HYBRID_AGGREGATION = 0x00010000, 254 HT_IOT_ACT_DISABLE_SHORT_GI = 0x00020000, 255 HT_IOT_ACT_DISABLE_HIGH_POWER = 0x00040000, 256 HT_IOT_ACT_DISABLE_TX_40_MHZ = 0x00080000, 257 HT_IOT_ACT_TX_NO_AGGREGATION = 0x00100000, 258 HT_IOT_ACT_DISABLE_TX_2SS = 0x00200000, 259 260 HT_IOT_ACT_MID_HIGHPOWER = 0x00400000, 261 HT_IOT_ACT_NULL_DATA_POWER_SAVING = 0x00800000, 262 263 HT_IOT_ACT_DISABLE_CCK_RATE = 0x01000000, 264 HT_IOT_ACT_FORCED_ENABLE_BE_TXOP = 0x02000000, 265 HT_IOT_ACT_WA_IOT_Broadcom = 0x04000000, 266 267 HT_IOT_ACT_DISABLE_RX_40MHZ_SHORT_GI = 0x08000000, 268 269 }; 270 271 enum ht_iot_rafunc { 272 HT_IOT_RAFUNC_DISABLE_ALL = 0x00, 273 HT_IOT_RAFUNC_PEER_1R = 0x01, 274 HT_IOT_RAFUNC_TX_AMSDU = 0x02, 275 }; 276 277 enum rt_ht_capability { 278 RT_HT_CAP_USE_TURBO_AGGR = 0x01, 279 RT_HT_CAP_USE_LONG_PREAMBLE = 0x02, 280 RT_HT_CAP_USE_AMPDU = 0x04, 281 RT_HT_CAP_USE_WOW = 0x8, 282 RT_HT_CAP_USE_SOFTAP = 0x10, 283 RT_HT_CAP_USE_92SE = 0x20, 284 }; 285 286 #endif 287