1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved. 4 * 5 * Contact Information: wlanfae <wlanfae@realtek.com> 6 */ 7 #include "rtl_core.h" 8 #include "r8192E_phyreg.h" 9 #include "r8192E_phy.h" 10 #include "r8190P_rtl8256.h" 11 12 void rtl92e_set_bandwidth(struct net_device *dev, 13 enum ht_channel_width bandwidth) 14 { 15 u8 eRFPath; 16 struct r8192_priv *priv = rtllib_priv(dev); 17 18 if (priv->card_8192_version != VERSION_8190_BD && 19 priv->card_8192_version != VERSION_8190_BE) { 20 netdev_warn(dev, "%s(): Unknown HW version.\n", __func__); 21 return; 22 } 23 24 for (eRFPath = 0; eRFPath < priv->NumTotalRFPath; eRFPath++) { 25 if (!rtl92e_is_legal_rf_path(dev, eRFPath)) 26 continue; 27 28 switch (bandwidth) { 29 case HT_CHANNEL_WIDTH_20: 30 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 31 0x0b, bMask12Bits, 0x100); 32 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 33 0x2c, bMask12Bits, 0x3d7); 34 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 35 0x0e, bMask12Bits, 0x021); 36 break; 37 case HT_CHANNEL_WIDTH_20_40: 38 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 39 0x0b, bMask12Bits, 0x300); 40 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 41 0x2c, bMask12Bits, 0x3ff); 42 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 43 0x0e, bMask12Bits, 0x0e1); 44 break; 45 default: 46 netdev_err(dev, "%s(): Unknown bandwidth: %#X\n", 47 __func__, bandwidth); 48 break; 49 } 50 } 51 } 52 53 bool rtl92e_config_rf(struct net_device *dev) 54 { 55 u32 u4RegValue = 0; 56 u8 eRFPath; 57 bool rtStatus = true; 58 struct bb_reg_definition *pPhyReg; 59 struct r8192_priv *priv = rtllib_priv(dev); 60 u32 RegOffSetToBeCheck = 0x3; 61 u32 RegValueToBeCheck = 0x7f1; 62 u32 RF3_Final_Value = 0; 63 u8 ConstRetryTimes = 5, RetryTimes = 5; 64 u8 ret = 0; 65 66 priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH; 67 68 for (eRFPath = (enum rf90_radio_path)RF90_PATH_A; 69 eRFPath < priv->NumTotalRFPath; eRFPath++) { 70 if (!rtl92e_is_legal_rf_path(dev, eRFPath)) 71 continue; 72 73 pPhyReg = &priv->PHYRegDef[eRFPath]; 74 75 switch (eRFPath) { 76 case RF90_PATH_A: 77 case RF90_PATH_C: 78 u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs, 79 bRFSI_RFENV); 80 break; 81 case RF90_PATH_B: 82 case RF90_PATH_D: 83 u4RegValue = rtl92e_get_bb_reg(dev, pPhyReg->rfintfs, 84 bRFSI_RFENV<<16); 85 break; 86 } 87 88 rtl92e_set_bb_reg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); 89 90 rtl92e_set_bb_reg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); 91 92 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, 93 b3WireAddressLength, 0x0); 94 rtl92e_set_bb_reg(dev, pPhyReg->rfHSSIPara2, 95 b3WireDataLength, 0x0); 96 97 rtl92e_set_rf_reg(dev, (enum rf90_radio_path)eRFPath, 0x0, 98 bMask12Bits, 0xbf); 99 100 rtStatus = rtl92e_check_bb_and_rf(dev, HW90_BLOCK_RF, 101 (enum rf90_radio_path)eRFPath); 102 if (!rtStatus) { 103 netdev_err(dev, "%s(): Failed to check RF Path %d.\n", 104 __func__, eRFPath); 105 goto fail; 106 } 107 108 RetryTimes = ConstRetryTimes; 109 RF3_Final_Value = 0; 110 while (RF3_Final_Value != RegValueToBeCheck && 111 RetryTimes != 0) { 112 ret = rtl92e_config_rf_path(dev, 113 (enum rf90_radio_path)eRFPath); 114 RF3_Final_Value = rtl92e_get_rf_reg(dev, 115 (enum rf90_radio_path)eRFPath, 116 RegOffSetToBeCheck, 117 bMask12Bits); 118 RetryTimes--; 119 } 120 121 switch (eRFPath) { 122 case RF90_PATH_A: 123 case RF90_PATH_C: 124 rtl92e_set_bb_reg(dev, pPhyReg->rfintfs, bRFSI_RFENV, 125 u4RegValue); 126 break; 127 case RF90_PATH_B: 128 case RF90_PATH_D: 129 rtl92e_set_bb_reg(dev, pPhyReg->rfintfs, 130 bRFSI_RFENV<<16, u4RegValue); 131 break; 132 } 133 134 if (ret) { 135 netdev_err(dev, 136 "%s(): Failed to initialize RF Path %d.\n", 137 __func__, eRFPath); 138 goto fail; 139 } 140 } 141 return true; 142 143 fail: 144 return false; 145 } 146 147 void rtl92e_set_cck_tx_power(struct net_device *dev, u8 powerlevel) 148 { 149 u32 TxAGC = 0; 150 struct r8192_priv *priv = rtllib_priv(dev); 151 152 TxAGC = powerlevel; 153 if (priv->bDynamicTxLowPower) { 154 if (priv->CustomerID == RT_CID_819x_Netcore) 155 TxAGC = 0x22; 156 else 157 TxAGC += priv->CckPwEnl; 158 } 159 if (TxAGC > 0x24) 160 TxAGC = 0x24; 161 rtl92e_set_bb_reg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC); 162 } 163 164 void rtl92e_set_ofdm_tx_power(struct net_device *dev, u8 powerlevel) 165 { 166 struct r8192_priv *priv = rtllib_priv(dev); 167 u32 writeVal, powerBase0, powerBase1, writeVal_tmp; 168 u8 index = 0; 169 u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c}; 170 u8 byte0, byte1, byte2, byte3; 171 172 powerBase0 = powerlevel + priv->LegacyHTTxPowerDiff; 173 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) | 174 (powerBase0 << 8) | powerBase0; 175 powerBase1 = powerlevel; 176 powerBase1 = (powerBase1 << 24) | (powerBase1 << 16) | 177 (powerBase1 << 8) | powerBase1; 178 179 for (index = 0; index < 6; index++) { 180 writeVal = (u32)(priv->MCSTxPowerLevelOriginalOffset[index] + 181 ((index < 2) ? powerBase0 : powerBase1)); 182 byte0 = writeVal & 0x7f; 183 byte1 = (writeVal & 0x7f00) >> 8; 184 byte2 = (writeVal & 0x7f0000) >> 16; 185 byte3 = (writeVal & 0x7f000000) >> 24; 186 if (byte0 > 0x24) 187 byte0 = 0x24; 188 if (byte1 > 0x24) 189 byte1 = 0x24; 190 if (byte2 > 0x24) 191 byte2 = 0x24; 192 if (byte3 > 0x24) 193 byte3 = 0x24; 194 195 if (index == 3) { 196 writeVal_tmp = (byte3 << 24) | (byte2 << 16) | 197 (byte1 << 8) | byte0; 198 priv->Pwr_Track = writeVal_tmp; 199 } 200 201 if (priv->bDynamicTxHighPower) 202 writeVal = 0x03030303; 203 else 204 writeVal = (byte3 << 24) | (byte2 << 16) | 205 (byte1 << 8) | byte0; 206 rtl92e_set_bb_reg(dev, RegOffset[index], 0x7f7f7f7f, writeVal); 207 } 208 } 209