1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * register description for HopeRf rf69 radio module 4 * 5 * Copyright (C) 2016 Wolf-Entwicklungen 6 * Marcus Wolf <linux@wolf-entwicklungen.de> 7 */ 8 9 /*******************************************/ 10 /* RF69 register addresses */ 11 /*******************************************/ 12 #define REG_FIFO 0x00 13 #define REG_OPMODE 0x01 14 #define REG_DATAMODUL 0x02 15 #define REG_BITRATE_MSB 0x03 16 #define REG_BITRATE_LSB 0x04 17 #define REG_FDEV_MSB 0x05 18 #define REG_FDEV_LSB 0x06 19 #define REG_FRF_MSB 0x07 20 #define REG_FRF_MID 0x08 21 #define REG_FRF_LSB 0x09 22 #define REG_OSC1 0x0A 23 #define REG_AFCCTRL 0x0B 24 #define REG_LOWBAT 0x0C 25 #define REG_LISTEN1 0x0D 26 #define REG_LISTEN2 0x0E 27 #define REG_LISTEN3 0x0F 28 #define REG_VERSION 0x10 29 #define REG_PALEVEL 0x11 30 #define REG_PARAMP 0x12 31 #define REG_OCP 0x13 32 #define REG_AGCREF 0x14 /* not available on RF69 */ 33 #define REG_AGCTHRESH1 0x15 /* not available on RF69 */ 34 #define REG_AGCTHRESH2 0x16 /* not available on RF69 */ 35 #define REG_AGCTHRESH3 0x17 /* not available on RF69 */ 36 #define REG_LNA 0x18 37 #define REG_RXBW 0x19 38 #define REG_AFCBW 0x1A 39 #define REG_OOKPEAK 0x1B 40 #define REG_OOKAVG 0x1C 41 #define REG_OOKFIX 0x1D 42 #define REG_AFCFEI 0x1E 43 #define REG_AFCMSB 0x1F 44 #define REG_AFCLSB 0x20 45 #define REG_FEIMSB 0x21 46 #define REG_FEILSB 0x22 47 #define REG_RSSICONFIG 0x23 48 #define REG_RSSIVALUE 0x24 49 #define REG_DIOMAPPING1 0x25 50 #define REG_DIOMAPPING2 0x26 51 #define REG_IRQFLAGS1 0x27 52 #define REG_IRQFLAGS2 0x28 53 #define REG_RSSITHRESH 0x29 54 #define REG_RXTIMEOUT1 0x2A 55 #define REG_RXTIMEOUT2 0x2B 56 #define REG_PREAMBLE_MSB 0x2C 57 #define REG_PREAMBLE_LSB 0x2D 58 #define REG_SYNC_CONFIG 0x2E 59 #define REG_SYNCVALUE1 0x2F 60 #define REG_SYNCVALUE2 0x30 61 #define REG_SYNCVALUE3 0x31 62 #define REG_SYNCVALUE4 0x32 63 #define REG_SYNCVALUE5 0x33 64 #define REG_SYNCVALUE6 0x34 65 #define REG_SYNCVALUE7 0x35 66 #define REG_SYNCVALUE8 0x36 67 #define REG_PACKETCONFIG1 0x37 68 #define REG_PAYLOAD_LENGTH 0x38 69 #define REG_NODEADRS 0x39 70 #define REG_BROADCASTADRS 0x3A 71 #define REG_AUTOMODES 0x3B 72 #define REG_FIFO_THRESH 0x3C 73 #define REG_PACKETCONFIG2 0x3D 74 #define REG_AESKEY1 0x3E 75 #define REG_AESKEY2 0x3F 76 #define REG_AESKEY3 0x40 77 #define REG_AESKEY4 0x41 78 #define REG_AESKEY5 0x42 79 #define REG_AESKEY6 0x43 80 #define REG_AESKEY7 0x44 81 #define REG_AESKEY8 0x45 82 #define REG_AESKEY9 0x46 83 #define REG_AESKEY10 0x47 84 #define REG_AESKEY11 0x48 85 #define REG_AESKEY12 0x49 86 #define REG_AESKEY13 0x4A 87 #define REG_AESKEY14 0x4B 88 #define REG_AESKEY15 0x4C 89 #define REG_AESKEY16 0x4D 90 #define REG_TEMP1 0x4E 91 #define REG_TEMP2 0x4F 92 #define REG_TESTPA1 0x5A /* only present on RFM69HW */ 93 #define REG_TESTPA2 0x5C /* only present on RFM69HW */ 94 #define REG_TESTDAGC 0x6F 95 96 /******************************************************/ 97 /* RF69/SX1231 bit definition */ 98 /******************************************************/ 99 /* write bit */ 100 #define WRITE_BIT 0x80 101 102 /* RegOpMode */ 103 #define MASK_OPMODE_SEQUENCER_OFF 0x80 104 #define MASK_OPMODE_LISTEN_ON 0x40 105 #define MASK_OPMODE_LISTEN_ABORT 0x20 106 #define MASK_OPMODE_MODE 0x1C 107 108 #define OPMODE_MODE_SLEEP 0x00 109 #define OPMODE_MODE_STANDBY 0x04 /* default */ 110 #define OPMODE_MODE_SYNTHESIZER 0x08 111 #define OPMODE_MODE_TRANSMIT 0x0C 112 #define OPMODE_MODE_RECEIVE 0x10 113 114 /* RegDataModul */ 115 #define MASK_DATAMODUL_MODE 0x06 116 #define MASK_DATAMODUL_MODULATION_TYPE 0x18 117 #define MASK_DATAMODUL_MODULATION_SHAPE 0x03 118 119 #define DATAMODUL_MODE_PACKET 0x00 /* default */ 120 #define DATAMODUL_MODE_CONTINUOUS 0x40 121 #define DATAMODUL_MODE_CONTINUOUS_NOSYNC 0x60 122 123 #define DATAMODUL_MODULATION_TYPE_FSK 0x00 /* default */ 124 #define DATAMODUL_MODULATION_TYPE_OOK 0x08 125 126 #define DATAMODUL_MODULATION_SHAPE_NONE 0x00 /* default */ 127 #define DATAMODUL_MODULATION_SHAPE_1_0 0x01 128 #define DATAMODUL_MODULATION_SHAPE_0_5 0x02 129 #define DATAMODUL_MODULATION_SHAPE_0_3 0x03 130 #define DATAMODUL_MODULATION_SHAPE_BR 0x01 131 #define DATAMODUL_MODULATION_SHAPE_2BR 0x02 132 133 /* RegFDevMsb (0x05)*/ 134 #define FDEVMASB_MASK 0x3f 135 136 /* 137 * // RegOsc1 138 * #define OSC1_RCCAL_START 0x80 139 * #define OSC1_RCCAL_DONE 0x40 140 * 141 * // RegLowBat 142 * #define LOWBAT_MONITOR 0x10 143 * #define LOWBAT_ON 0x08 144 * #define LOWBAT_OFF 0x00 // Default 145 * 146 * #define LOWBAT_TRIM_1695 0x00 147 * #define LOWBAT_TRIM_1764 0x01 148 * #define LOWBAT_TRIM_1835 0x02 // Default 149 * #define LOWBAT_TRIM_1905 0x03 150 * #define LOWBAT_TRIM_1976 0x04 151 * #define LOWBAT_TRIM_2045 0x05 152 * #define LOWBAT_TRIM_2116 0x06 153 * #define LOWBAT_TRIM_2185 0x07 154 * 155 * 156 * // RegListen1 157 * #define LISTEN1_RESOL_64 0x50 158 * #define LISTEN1_RESOL_4100 0xA0 // Default 159 * #define LISTEN1_RESOL_262000 0xF0 160 * 161 * #define LISTEN1_CRITERIA_RSSI 0x00 // Default 162 * #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08 163 * 164 * #define LISTEN1_END_00 0x00 165 * #define LISTEN1_END_01 0x02 // Default 166 * #define LISTEN1_END_10 0x04 167 * 168 * 169 * // RegListen2 170 * #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default 171 * 172 * // RegListen3 173 * #define LISTEN3_COEFRX_VALUE 0x20 // Default 174 */ 175 176 // RegPaLevel 177 #define MASK_PALEVEL_PA0 0x80 178 #define MASK_PALEVEL_PA1 0x40 179 #define MASK_PALEVEL_PA2 0x20 180 #define MASK_PALEVEL_OUTPUT_POWER 0x1F 181 182 // RegPaRamp 183 #define PARAMP_3400 0x00 184 #define PARAMP_2000 0x01 185 #define PARAMP_1000 0x02 186 #define PARAMP_500 0x03 187 #define PARAMP_250 0x04 188 #define PARAMP_125 0x05 189 #define PARAMP_100 0x06 190 #define PARAMP_62 0x07 191 #define PARAMP_50 0x08 192 #define PARAMP_40 0x09 /* default */ 193 #define PARAMP_31 0x0A 194 #define PARAMP_25 0x0B 195 #define PARAMP_20 0x0C 196 #define PARAMP_15 0x0D 197 #define PARAMP_12 0x0E 198 #define PARAMP_10 0x0F 199 200 #define MASK_PARAMP 0x0F 201 202 /* 203 * // RegOcp 204 * #define OCP_OFF 0x0F 205 * #define OCP_ON 0x1A // Default 206 * 207 * #define OCP_TRIM_45 0x00 208 * #define OCP_TRIM_50 0x01 209 * #define OCP_TRIM_55 0x02 210 * #define OCP_TRIM_60 0x03 211 * #define OCP_TRIM_65 0x04 212 * #define OCP_TRIM_70 0x05 213 * #define OCP_TRIM_75 0x06 214 * #define OCP_TRIM_80 0x07 215 * #define OCP_TRIM_85 0x08 216 * #define OCP_TRIM_90 0x09 217 * #define OCP_TRIM_95 0x0A 218 * #define OCP_TRIM_100 0x0B // Default 219 * #define OCP_TRIM_105 0x0C 220 * #define OCP_TRIM_110 0x0D 221 * #define OCP_TRIM_115 0x0E 222 * #define OCP_TRIM_120 0x0F 223 */ 224 225 /* RegLna (0x18) */ 226 #define MASK_LNA_ZIN 0x80 227 #define MASK_LNA_CURRENT_GAIN 0x38 228 #define MASK_LNA_GAIN 0x07 229 230 #define LNA_GAIN_AUTO 0x00 /* default */ 231 #define LNA_GAIN_MAX 0x01 232 #define LNA_GAIN_MAX_MINUS_6 0x02 233 #define LNA_GAIN_MAX_MINUS_12 0x03 234 #define LNA_GAIN_MAX_MINUS_24 0x04 235 #define LNA_GAIN_MAX_MINUS_36 0x05 236 #define LNA_GAIN_MAX_MINUS_48 0x06 237 238 /* RegRxBw (0x19) and RegAfcBw (0x1A) */ 239 #define MASK_BW_DCC_FREQ 0xE0 240 #define MASK_BW_MANTISSE 0x18 241 #define MASK_BW_EXPONENT 0x07 242 243 #define BW_DCC_16_PERCENT 0x00 244 #define BW_DCC_8_PERCENT 0x20 245 #define BW_DCC_4_PERCENT 0x40 /* default */ 246 #define BW_DCC_2_PERCENT 0x60 247 #define BW_DCC_1_PERCENT 0x80 248 #define BW_DCC_0_5_PERCENT 0xA0 249 #define BW_DCC_0_25_PERCENT 0xC0 250 #define BW_DCC_0_125_PERCENT 0xE0 251 252 #define BW_MANT_16 0x00 253 #define BW_MANT_20 0x08 254 #define BW_MANT_24 0x10 /* default */ 255 256 /* RegOokPeak (0x1B) */ 257 #define MASK_OOKPEAK_THRESTYPE 0xc0 258 #define MASK_OOKPEAK_THRESSTEP 0x38 259 #define MASK_OOKPEAK_THRESDEC 0x07 260 261 #define OOKPEAK_THRESHTYPE_FIXED 0x00 262 #define OOKPEAK_THRESHTYPE_PEAK 0x40 /* default */ 263 #define OOKPEAK_THRESHTYPE_AVERAGE 0x80 264 265 #define OOKPEAK_THRESHSTEP_0_5_DB 0x00 /* default */ 266 #define OOKPEAK_THRESHSTEP_1_0_DB 0x08 267 #define OOKPEAK_THRESHSTEP_1_5_DB 0x10 268 #define OOKPEAK_THRESHSTEP_2_0_DB 0x18 269 #define OOKPEAK_THRESHSTEP_3_0_DB 0x20 270 #define OOKPEAK_THRESHSTEP_4_0_DB 0x28 271 #define OOKPEAK_THRESHSTEP_5_0_DB 0x30 272 #define OOKPEAK_THRESHSTEP_6_0_DB 0x38 273 274 #define OOKPEAK_THRESHDEC_ONCE 0x00 /* default */ 275 #define OOKPEAK_THRESHDEC_EVERY_2ND 0x01 276 #define OOKPEAK_THRESHDEC_EVERY_4TH 0x02 277 #define OOKPEAK_THRESHDEC_EVERY_8TH 0x03 278 #define OOKPEAK_THRESHDEC_TWICE 0x04 279 #define OOKPEAK_THRESHDEC_4_TIMES 0x05 280 #define OOKPEAK_THRESHDEC_8_TIMES 0x06 281 #define OOKPEAK_THRESHDEC_16_TIMES 0x07 282 283 /* 284 * // RegOokAvg 285 * #define OOKAVG_AVERAGETHRESHFILT_00 0x00 286 * #define OOKAVG_AVERAGETHRESHFILT_01 0x40 287 * #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default 288 * #define OOKAVG_AVERAGETHRESHFILT_11 0xC0 289 * 290 * 291 * // RegAfcFei 292 * #define AFCFEI_FEI_DONE 0x40 293 * #define AFCFEI_FEI_START 0x20 294 * #define AFCFEI_AFC_DONE 0x10 295 * #define AFCFEI_AFCAUTOCLEAR_ON 0x08 296 * #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default 297 * 298 * #define AFCFEI_AFCAUTO_ON 0x04 299 * #define AFCFEI_AFCAUTO_OFF 0x00 // Default 300 * 301 * #define AFCFEI_AFC_CLEAR 0x02 302 * #define AFCFEI_AFC_START 0x01 303 * 304 * // RegRssiConfig 305 * #define RSSI_FASTRX_ON 0x08 306 * #define RSSI_FASTRX_OFF 0x00 // Default 307 * #define RSSI_DONE 0x02 308 * #define RSSI_START 0x01 309 */ 310 311 /* RegDioMapping1 */ 312 #define MASK_DIO0 0xC0 313 #define MASK_DIO1 0x30 314 #define MASK_DIO2 0x0C 315 #define MASK_DIO3 0x03 316 #define SHIFT_DIO0 6 317 #define SHIFT_DIO1 4 318 #define SHIFT_DIO2 2 319 #define SHIFT_DIO3 0 320 321 /* RegDioMapping2 */ 322 #define MASK_DIO4 0xC0 323 #define MASK_DIO5 0x30 324 #define SHIFT_DIO4 6 325 #define SHIFT_DIO5 4 326 327 /* DIO numbers */ 328 #define DIO0 0 329 #define DIO1 1 330 #define DIO2 2 331 #define DIO3 3 332 #define DIO4 4 333 #define DIO5 5 334 335 /* DIO Mapping values (packet mode) */ 336 #define DIO_MODE_READY_DIO4 0x00 337 #define DIO_MODE_READY_DIO5 0x03 338 #define DIO_CLK_OUT 0x00 339 #define DIO_DATA 0x01 340 #define DIO_TIMEOUT_DIO1 0x03 341 #define DIO_TIMEOUT_DIO4 0x00 342 #define DIO_RSSI_DIO0 0x03 343 #define DIO_RSSI_DIO3_4 0x01 344 #define DIO_RX_READY 0x02 345 #define DIO_PLL_LOCK 0x03 346 #define DIO_TX_READY 0x01 347 #define DIO_FIFO_FULL_DIO1 0x01 348 #define DIO_FIFO_FULL_DIO3 0x00 349 #define DIO_SYNC_ADDRESS 0x02 350 #define DIO_FIFO_NOT_EMPTY_DIO1 0x02 351 #define DIO_FIFO_NOT_EMPTY_FIO2 0x00 352 #define DIO_AUTOMODE 0x04 353 #define DIO_FIFO_LEVEL 0x00 354 #define DIO_CRC_OK 0x00 355 #define DIO_PAYLOAD_READY 0x01 356 #define DIO_PACKET_SENT 0x00 357 #define DIO_DCLK 0x00 358 359 /* RegDioMapping2 CLK_OUT part */ 360 #define MASK_DIOMAPPING2_CLK_OUT 0x07 361 362 #define DIOMAPPING2_CLK_OUT_NO_DIV 0x00 363 #define DIOMAPPING2_CLK_OUT_DIV_2 0x01 364 #define DIOMAPPING2_CLK_OUT_DIV_4 0x02 365 #define DIOMAPPING2_CLK_OUT_DIV_8 0x03 366 #define DIOMAPPING2_CLK_OUT_DIV_16 0x04 367 #define DIOMAPPING2_CLK_OUT_DIV_32 0x05 368 #define DIOMAPPING2_CLK_OUT_RC 0x06 369 #define DIOMAPPING2_CLK_OUT_OFF 0x07 /* default */ 370 371 /* RegIrqFlags1 */ 372 #define MASK_IRQFLAGS1_MODE_READY 0x80 373 #define MASK_IRQFLAGS1_RX_READY 0x40 374 #define MASK_IRQFLAGS1_TX_READY 0x20 375 #define MASK_IRQFLAGS1_PLL_LOCK 0x10 376 #define MASK_IRQFLAGS1_RSSI 0x08 377 #define MASK_IRQFLAGS1_TIMEOUT 0x04 378 #define MASK_IRQFLAGS1_AUTOMODE 0x02 379 #define MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH 0x01 380 381 /* RegIrqFlags2 */ 382 #define MASK_IRQFLAGS2_FIFO_FULL 0x80 383 #define MASK_IRQFLAGS2_FIFO_NOT_EMPTY 0x40 384 #define MASK_IRQFLAGS2_FIFO_LEVEL 0x20 385 #define MASK_IRQFLAGS2_FIFO_OVERRUN 0x10 386 #define MASK_IRQFLAGS2_PACKET_SENT 0x08 387 #define MASK_IRQFLAGS2_PAYLOAD_READY 0x04 388 #define MASK_IRQFLAGS2_CRC_OK 0x02 389 #define MASK_IRQFLAGS2_LOW_BAT 0x01 390 391 /* RegSyncConfig */ 392 #define MASK_SYNC_CONFIG_SYNC_ON 0x80 /* default */ 393 #define MASK_SYNC_CONFIG_FIFO_FILL_CONDITION 0x40 394 #define MASK_SYNC_CONFIG_SYNC_SIZE 0x38 395 #define MASK_SYNC_CONFIG_SYNC_TOLERANCE 0x07 396 397 /* RegPacketConfig1 */ 398 #define MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE 0x80 399 #define MASK_PACKETCONFIG1_DCFREE 0x60 400 #define MASK_PACKETCONFIG1_CRC_ON 0x10 /* default */ 401 #define MASK_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 402 #define MASK_PACKETCONFIG1_ADDRESSFILTERING 0x06 403 404 #define PACKETCONFIG1_DCFREE_OFF 0x00 /* default */ 405 #define PACKETCONFIG1_DCFREE_MANCHESTER 0x20 406 #define PACKETCONFIG1_DCFREE_WHITENING 0x40 407 #define PACKETCONFIG1_ADDRESSFILTERING_OFF 0x00 /* default */ 408 #define PACKETCONFIG1_ADDRESSFILTERING_NODE 0x02 409 #define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04 410 411 /* 412 * // RegAutoModes 413 * #define AUTOMODES_ENTER_OFF 0x00 // Default 414 * #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20 415 * #define AUTOMODES_ENTER_FIFOLEVEL 0x40 416 * #define AUTOMODES_ENTER_CRCOK 0x60 417 * #define AUTOMODES_ENTER_PAYLOADREADY 0x80 418 * #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0 419 * #define AUTOMODES_ENTER_PACKETSENT 0xC0 420 * #define AUTOMODES_ENTER_FIFOEMPTY 0xE0 421 * 422 * #define AUTOMODES_EXIT_OFF 0x00 // Default 423 * #define AUTOMODES_EXIT_FIFOEMPTY 0x04 424 * #define AUTOMODES_EXIT_FIFOLEVEL 0x08 425 * #define AUTOMODES_EXIT_CRCOK 0x0C 426 * #define AUTOMODES_EXIT_PAYLOADREADY 0x10 427 * #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14 428 * #define AUTOMODES_EXIT_PACKETSENT 0x18 429 * #define AUTOMODES_EXIT_RXTIMEOUT 0x1C 430 * 431 * #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default 432 * #define AUTOMODES_INTERMEDIATE_STANDBY 0x01 433 * #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02 434 * #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03 435 * 436 */ 437 /* RegFifoThresh (0x3c) */ 438 #define MASK_FIFO_THRESH_TXSTART 0x80 439 #define MASK_FIFO_THRESH_VALUE 0x7F 440 441 /* 442 * 443 * // RegPacketConfig2 444 * #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default 445 * #define PACKET2_RXRESTARTDELAY_2BITS 0x10 446 * #define PACKET2_RXRESTARTDELAY_4BITS 0x20 447 * #define PACKET2_RXRESTARTDELAY_8BITS 0x30 448 * #define PACKET2_RXRESTARTDELAY_16BITS 0x40 449 * #define PACKET2_RXRESTARTDELAY_32BITS 0x50 450 * #define PACKET2_RXRESTARTDELAY_64BITS 0x60 451 * #define PACKET2_RXRESTARTDELAY_128BITS 0x70 452 * #define PACKET2_RXRESTARTDELAY_256BITS 0x80 453 * #define PACKET2_RXRESTARTDELAY_512BITS 0x90 454 * #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0 455 * #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0 456 * #define PACKET2_RXRESTARTDELAY_NONE 0xC0 457 * #define PACKET2_RXRESTART 0x04 458 * 459 * #define PACKET2_AUTORXRESTART_ON 0x02 // Default 460 * #define PACKET2_AUTORXRESTART_OFF 0x00 461 * 462 * #define PACKET2_AES_ON 0x01 463 * #define PACKET2_AES_OFF 0x00 // Default 464 * 465 * 466 * // RegTemp1 467 * #define TEMP1_MEAS_START 0x08 468 * #define TEMP1_MEAS_RUNNING 0x04 469 * #define TEMP1_ADCLOWPOWER_ON 0x01 // Default 470 * #define TEMP1_ADCLOWPOWER_OFF 0x00 471 */ 472 473 // RegTestDagc (0x6F) 474 #define DAGC_NORMAL 0x00 /* Reset value */ 475 #define DAGC_IMPROVED_LOWBETA1 0x20 476 #define DAGC_IMPROVED_LOWBETA0 0x30 /* Recommended val */ 477