1 /* 2 * register description for HopeRf rf69 radio module 3 * 4 * Copyright (C) 2016 Wolf-Entwicklungen 5 * Marcus Wolf <linux@wolf-entwicklungen.de> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 /*******************************************/ 19 /* RF69 register addresses */ 20 /*******************************************/ 21 #define REG_FIFO 0x00 22 #define REG_OPMODE 0x01 23 #define REG_DATAMODUL 0x02 24 #define REG_BITRATE_MSB 0x03 25 #define REG_BITRATE_LSB 0x04 26 #define REG_FDEV_MSB 0x05 27 #define REG_FDEV_LSB 0x06 28 #define REG_FRF_MSB 0x07 29 #define REG_FRF_MID 0x08 30 #define REG_FRF_LSB 0x09 31 #define REG_OSC1 0x0A 32 #define REG_AFCCTRL 0x0B 33 #define REG_LOWBAT 0x0C 34 #define REG_LISTEN1 0x0D 35 #define REG_LISTEN2 0x0E 36 #define REG_LISTEN3 0x0F 37 #define REG_VERSION 0x10 38 #define REG_PALEVEL 0x11 39 #define REG_PARAMP 0x12 40 #define REG_OCP 0x13 41 #define REG_AGCREF 0x14 /* not available on RF69 */ 42 #define REG_AGCTHRESH1 0x15 /* not available on RF69 */ 43 #define REG_AGCTHRESH2 0x16 /* not available on RF69 */ 44 #define REG_AGCTHRESH3 0x17 /* not available on RF69 */ 45 #define REG_LNA 0x18 46 #define REG_RXBW 0x19 47 #define REG_AFCBW 0x1A 48 #define REG_OOKPEAK 0x1B 49 #define REG_OOKAVG 0x1C 50 #define REG_OOKFIX 0x1D 51 #define REG_AFCFEI 0x1E 52 #define REG_AFCMSB 0x1F 53 #define REG_AFCLSB 0x20 54 #define REG_FEIMSB 0x21 55 #define REG_FEILSB 0x22 56 #define REG_RSSICONFIG 0x23 57 #define REG_RSSIVALUE 0x24 58 #define REG_DIOMAPPING1 0x25 59 #define REG_DIOMAPPING2 0x26 60 #define REG_IRQFLAGS1 0x27 61 #define REG_IRQFLAGS2 0x28 62 #define REG_RSSITHRESH 0x29 63 #define REG_RXTIMEOUT1 0x2A 64 #define REG_RXTIMEOUT2 0x2B 65 #define REG_PREAMBLE_MSB 0x2C 66 #define REG_PREAMBLE_LSB 0x2D 67 #define REG_SYNC_CONFIG 0x2E 68 #define REG_SYNCVALUE1 0x2F 69 #define REG_SYNCVALUE2 0x30 70 #define REG_SYNCVALUE3 0x31 71 #define REG_SYNCVALUE4 0x32 72 #define REG_SYNCVALUE5 0x33 73 #define REG_SYNCVALUE6 0x34 74 #define REG_SYNCVALUE7 0x35 75 #define REG_SYNCVALUE8 0x36 76 #define REG_PACKETCONFIG1 0x37 77 #define REG_PAYLOAD_LENGTH 0x38 78 #define REG_NODEADRS 0x39 79 #define REG_BROADCASTADRS 0x3A 80 #define REG_AUTOMODES 0x3B 81 #define REG_FIFO_THRESH 0x3C 82 #define REG_PACKETCONFIG2 0x3D 83 #define REG_AESKEY1 0x3E 84 #define REG_AESKEY2 0x3F 85 #define REG_AESKEY3 0x40 86 #define REG_AESKEY4 0x41 87 #define REG_AESKEY5 0x42 88 #define REG_AESKEY6 0x43 89 #define REG_AESKEY7 0x44 90 #define REG_AESKEY8 0x45 91 #define REG_AESKEY9 0x46 92 #define REG_AESKEY10 0x47 93 #define REG_AESKEY11 0x48 94 #define REG_AESKEY12 0x49 95 #define REG_AESKEY13 0x4A 96 #define REG_AESKEY14 0x4B 97 #define REG_AESKEY15 0x4C 98 #define REG_AESKEY16 0x4D 99 #define REG_TEMP1 0x4E 100 #define REG_TEMP2 0x4F 101 #define REG_TESTPA1 0x5A /* only present on RFM69HW */ 102 #define REG_TESTPA2 0x5C /* only present on RFM69HW */ 103 #define REG_TESTDAGC 0x6F 104 105 /******************************************************/ 106 /* RF69/SX1231 bit definition */ 107 /******************************************************/ 108 /* write bit */ 109 #define WRITE_BIT 0x80 110 111 /* RegOpMode */ 112 #define MASK_OPMODE_SEQUENCER_OFF 0x80 113 #define MASK_OPMODE_LISTEN_ON 0x40 114 #define MASK_OPMODE_LISTEN_ABORT 0x20 115 #define MASK_OPMODE_MODE 0x1C 116 117 #define OPMODE_MODE_SLEEP 0x00 118 #define OPMODE_MODE_STANDBY 0x04 /* default */ 119 #define OPMODE_MODE_SYNTHESIZER 0x08 120 #define OPMODE_MODE_TRANSMIT 0x0C 121 #define OPMODE_MODE_RECEIVE 0x10 122 123 /* RegDataModul */ 124 #define MASK_DATAMODUL_MODE 0x06 125 #define MASK_DATAMODUL_MODULATION_TYPE 0x18 126 #define MASK_DATAMODUL_MODULATION_SHAPE 0x03 127 128 #define DATAMODUL_MODE_PACKET 0x00 /* default */ 129 #define DATAMODUL_MODE_CONTINUOUS 0x40 130 #define DATAMODUL_MODE_CONTINUOUS_NOSYNC 0x60 131 132 #define DATAMODUL_MODULATION_TYPE_FSK 0x00 /* default */ 133 #define DATAMODUL_MODULATION_TYPE_OOK 0x08 134 135 #define DATAMODUL_MODULATION_SHAPE_NONE 0x00 /* default */ 136 #define DATAMODUL_MODULATION_SHAPE_1_0 0x01 137 #define DATAMODUL_MODULATION_SHAPE_0_5 0x02 138 #define DATAMODUL_MODULATION_SHAPE_0_3 0x03 139 #define DATAMODUL_MODULATION_SHAPE_BR 0x01 140 #define DATAMODUL_MODULATION_SHAPE_2BR 0x02 141 142 /* RegFDevMsb (0x05)*/ 143 #define FDEVMASB_MASK 0x3f 144 145 /* 146 * // RegOsc1 147 * #define OSC1_RCCAL_START 0x80 148 * #define OSC1_RCCAL_DONE 0x40 149 * 150 * // RegLowBat 151 * #define LOWBAT_MONITOR 0x10 152 * #define LOWBAT_ON 0x08 153 * #define LOWBAT_OFF 0x00 // Default 154 * 155 * #define LOWBAT_TRIM_1695 0x00 156 * #define LOWBAT_TRIM_1764 0x01 157 * #define LOWBAT_TRIM_1835 0x02 // Default 158 * #define LOWBAT_TRIM_1905 0x03 159 * #define LOWBAT_TRIM_1976 0x04 160 * #define LOWBAT_TRIM_2045 0x05 161 * #define LOWBAT_TRIM_2116 0x06 162 * #define LOWBAT_TRIM_2185 0x07 163 * 164 * 165 * // RegListen1 166 * #define LISTEN1_RESOL_64 0x50 167 * #define LISTEN1_RESOL_4100 0xA0 // Default 168 * #define LISTEN1_RESOL_262000 0xF0 169 * 170 * #define LISTEN1_CRITERIA_RSSI 0x00 // Default 171 * #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08 172 * 173 * #define LISTEN1_END_00 0x00 174 * #define LISTEN1_END_01 0x02 // Default 175 * #define LISTEN1_END_10 0x04 176 * 177 * 178 * // RegListen2 179 * #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default 180 * 181 * // RegListen3 182 * #define LISTEN3_COEFRX_VALUE 0x20 // Default 183 */ 184 185 // RegPaLevel 186 #define MASK_PALEVEL_PA0 0x80 187 #define MASK_PALEVEL_PA1 0x40 188 #define MASK_PALEVEL_PA2 0x20 189 #define MASK_PALEVEL_OUTPUT_POWER 0x1F 190 191 192 193 // RegPaRamp 194 #define PARAMP_3400 0x00 195 #define PARAMP_2000 0x01 196 #define PARAMP_1000 0x02 197 #define PARAMP_500 0x03 198 #define PARAMP_250 0x04 199 #define PARAMP_125 0x05 200 #define PARAMP_100 0x06 201 #define PARAMP_62 0x07 202 #define PARAMP_50 0x08 203 #define PARAMP_40 0x09 /* default */ 204 #define PARAMP_31 0x0A 205 #define PARAMP_25 0x0B 206 #define PARAMP_20 0x0C 207 #define PARAMP_15 0x0D 208 #define PARAMP_12 0x0E 209 #define PARAMP_10 0x0F 210 211 #define MASK_PARAMP 0x0F 212 213 /* 214 * // RegOcp 215 * #define OCP_OFF 0x0F 216 * #define OCP_ON 0x1A // Default 217 * 218 * #define OCP_TRIM_45 0x00 219 * #define OCP_TRIM_50 0x01 220 * #define OCP_TRIM_55 0x02 221 * #define OCP_TRIM_60 0x03 222 * #define OCP_TRIM_65 0x04 223 * #define OCP_TRIM_70 0x05 224 * #define OCP_TRIM_75 0x06 225 * #define OCP_TRIM_80 0x07 226 * #define OCP_TRIM_85 0x08 227 * #define OCP_TRIM_90 0x09 228 * #define OCP_TRIM_95 0x0A 229 * #define OCP_TRIM_100 0x0B // Default 230 * #define OCP_TRIM_105 0x0C 231 * #define OCP_TRIM_110 0x0D 232 * #define OCP_TRIM_115 0x0E 233 * #define OCP_TRIM_120 0x0F 234 */ 235 236 /* RegLna (0x18) */ 237 #define MASK_LNA_ZIN 0x80 238 #define MASK_LNA_CURRENT_GAIN 0x38 239 #define MASK_LNA_GAIN 0x07 240 241 #define LNA_GAIN_AUTO 0x00 /* default */ 242 #define LNA_GAIN_MAX 0x01 243 #define LNA_GAIN_MAX_MINUS_6 0x02 244 #define LNA_GAIN_MAX_MINUS_12 0x03 245 #define LNA_GAIN_MAX_MINUS_24 0x04 246 #define LNA_GAIN_MAX_MINUS_36 0x05 247 #define LNA_GAIN_MAX_MINUS_48 0x06 248 249 250 /* RegRxBw (0x19) and RegAfcBw (0x1A) */ 251 #define MASK_BW_DCC_FREQ 0xE0 252 #define MASK_BW_MANTISSE 0x18 253 #define MASK_BW_EXPONENT 0x07 254 255 #define BW_DCC_16_PERCENT 0x00 256 #define BW_DCC_8_PERCENT 0x20 257 #define BW_DCC_4_PERCENT 0x40 /* default */ 258 #define BW_DCC_2_PERCENT 0x60 259 #define BW_DCC_1_PERCENT 0x80 260 #define BW_DCC_0_5_PERCENT 0xA0 261 #define BW_DCC_0_25_PERCENT 0xC0 262 #define BW_DCC_0_125_PERCENT 0xE0 263 264 #define BW_MANT_16 0x00 265 #define BW_MANT_20 0x08 266 #define BW_MANT_24 0x10 /* default */ 267 268 269 /* RegOokPeak (0x1B) */ 270 #define MASK_OOKPEAK_THRESTYPE 0xc0 271 #define MASK_OOKPEAK_THRESSTEP 0x38 272 #define MASK_OOKPEAK_THRESDEC 0x07 273 274 #define OOKPEAK_THRESHTYPE_FIXED 0x00 275 #define OOKPEAK_THRESHTYPE_PEAK 0x40 /* default */ 276 #define OOKPEAK_THRESHTYPE_AVERAGE 0x80 277 278 #define OOKPEAK_THRESHSTEP_0_5_DB 0x00 /* default */ 279 #define OOKPEAK_THRESHSTEP_1_0_DB 0x08 280 #define OOKPEAK_THRESHSTEP_1_5_DB 0x10 281 #define OOKPEAK_THRESHSTEP_2_0_DB 0x18 282 #define OOKPEAK_THRESHSTEP_3_0_DB 0x20 283 #define OOKPEAK_THRESHSTEP_4_0_DB 0x28 284 #define OOKPEAK_THRESHSTEP_5_0_DB 0x30 285 #define OOKPEAK_THRESHSTEP_6_0_DB 0x38 286 287 #define OOKPEAK_THRESHDEC_ONCE 0x00 /* default */ 288 #define OOKPEAK_THRESHDEC_EVERY_2ND 0x01 289 #define OOKPEAK_THRESHDEC_EVERY_4TH 0x02 290 #define OOKPEAK_THRESHDEC_EVERY_8TH 0x03 291 #define OOKPEAK_THRESHDEC_TWICE 0x04 292 #define OOKPEAK_THRESHDEC_4_TIMES 0x05 293 #define OOKPEAK_THRESHDEC_8_TIMES 0x06 294 #define OOKPEAK_THRESHDEC_16_TIMES 0x07 295 296 /* 297 * // RegOokAvg 298 * #define OOKAVG_AVERAGETHRESHFILT_00 0x00 299 * #define OOKAVG_AVERAGETHRESHFILT_01 0x40 300 * #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default 301 * #define OOKAVG_AVERAGETHRESHFILT_11 0xC0 302 * 303 * 304 * // RegAfcFei 305 * #define AFCFEI_FEI_DONE 0x40 306 * #define AFCFEI_FEI_START 0x20 307 * #define AFCFEI_AFC_DONE 0x10 308 * #define AFCFEI_AFCAUTOCLEAR_ON 0x08 309 * #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default 310 * 311 * #define AFCFEI_AFCAUTO_ON 0x04 312 * #define AFCFEI_AFCAUTO_OFF 0x00 // Default 313 * 314 * #define AFCFEI_AFC_CLEAR 0x02 315 * #define AFCFEI_AFC_START 0x01 316 * 317 * // RegRssiConfig 318 * #define RSSI_FASTRX_ON 0x08 319 * #define RSSI_FASTRX_OFF 0x00 // Default 320 * #define RSSI_DONE 0x02 321 * #define RSSI_START 0x01 322 */ 323 324 /* RegDioMapping1 */ 325 #define MASK_DIO0 0xC0 326 #define MASK_DIO1 0x30 327 #define MASK_DIO2 0x0C 328 #define MASK_DIO3 0x03 329 #define SHIFT_DIO0 6 330 #define SHIFT_DIO1 4 331 #define SHIFT_DIO2 2 332 #define SHIFT_DIO3 0 333 334 /* RegDioMapping2 */ 335 #define MASK_DIO4 0xC0 336 #define MASK_DIO5 0x30 337 #define SHIFT_DIO4 6 338 #define SHIFT_DIO5 4 339 340 /* DIO numbers */ 341 #define DIO0 0 342 #define DIO1 1 343 #define DIO2 2 344 #define DIO3 3 345 #define DIO4 4 346 #define DIO5 5 347 348 /* DIO Mapping values (packet mode) */ 349 #define DIO_ModeReady_DIO4 0x00 350 #define DIO_ModeReady_DIO5 0x03 351 #define DIO_ClkOut 0x00 352 #define DIO_Data 0x01 353 #define DIO_TimeOut_DIO1 0x03 354 #define DIO_TimeOut_DIO4 0x00 355 #define DIO_Rssi_DIO0 0x03 356 #define DIO_Rssi_DIO3_4 0x01 357 #define DIO_RxReady 0x02 358 #define DIO_PLLLock 0x03 359 #define DIO_TxReady 0x01 360 #define DIO_FifoFull_DIO1 0x01 361 #define DIO_FifoFull_DIO3 0x00 362 #define DIO_SyncAddress 0x02 363 #define DIO_FifoNotEmpty_DIO1 0x02 364 #define DIO_FifoNotEmpty_FIO2 0x00 365 #define DIO_Automode 0x04 366 #define DIO_FifoLevel 0x00 367 #define DIO_CrcOk 0x00 368 #define DIO_PayloadReady 0x01 369 #define DIO_PacketSent 0x00 370 #define DIO_Dclk 0x00 371 372 /* RegDioMapping2 CLK_OUT part */ 373 #define MASK_DIOMAPPING2_CLK_OUT 0x07 374 375 #define DIOMAPPING2_CLK_OUT_NO_DIV 0x00 376 #define DIOMAPPING2_CLK_OUT_DIV_2 0x01 377 #define DIOMAPPING2_CLK_OUT_DIV_4 0x02 378 #define DIOMAPPING2_CLK_OUT_DIV_8 0x03 379 #define DIOMAPPING2_CLK_OUT_DIV_16 0x04 380 #define DIOMAPPING2_CLK_OUT_DIV_32 0x05 381 #define DIOMAPPING2_CLK_OUT_RC 0x06 382 #define DIOMAPPING2_CLK_OUT_OFF 0x07 /* default */ 383 384 /* RegIrqFlags1 */ 385 #define MASK_IRQFLAGS1_MODE_READY 0x80 386 #define MASK_IRQFLAGS1_RX_READY 0x40 387 #define MASK_IRQFLAGS1_TX_READY 0x20 388 #define MASK_IRQFLAGS1_PLL_LOCK 0x10 389 #define MASK_IRQFLAGS1_RSSI 0x08 390 #define MASK_IRQFLAGS1_TIMEOUT 0x04 391 #define MASK_IRQFLAGS1_AUTOMODE 0x02 392 #define MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH 0x01 393 394 /* RegIrqFlags2 */ 395 #define MASK_IRQFLAGS2_FIFO_FULL 0x80 396 #define MASK_IRQFLAGS2_FIFO_NOT_EMPTY 0x40 397 #define MASK_IRQFLAGS2_FIFO_LEVEL 0x20 398 #define MASK_IRQFLAGS2_FIFO_OVERRUN 0x10 399 #define MASK_IRQFLAGS2_PACKET_SENT 0x08 400 #define MASK_IRQFLAGS2_PAYLOAD_READY 0x04 401 #define MASK_IRQFLAGS2_CRC_OK 0x02 402 #define MASK_IRQFLAGS2_LOW_BAT 0x01 403 404 /* RegSyncConfig */ 405 #define MASK_SYNC_CONFIG_SYNC_ON 0x80 /* default */ 406 #define MASK_SYNC_CONFIG_FIFO_FILL_CONDITION 0x40 407 #define MASK_SYNC_CONFIG_SYNC_SIZE 0x38 408 #define MASK_SYNC_CONFIG_SYNC_TOLERANCE 0x07 409 410 /* RegPacketConfig1 */ 411 #define MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE 0x80 412 #define MASK_PACKETCONFIG1_DCFREE 0x60 413 #define MASK_PACKETCONFIG1_CRC_ON 0x10 /* default */ 414 #define MASK_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 415 #define MASK_PACKETCONFIG1_ADDRESSFILTERING 0x06 416 417 #define PACKETCONFIG1_DCFREE_OFF 0x00 /* default */ 418 #define PACKETCONFIG1_DCFREE_MANCHESTER 0x20 419 #define PACKETCONFIG1_DCFREE_WHITENING 0x40 420 #define PACKETCONFIG1_ADDRESSFILTERING_OFF 0x00 /* default */ 421 #define PACKETCONFIG1_ADDRESSFILTERING_NODE 0x02 422 #define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04 423 424 /* 425 * // RegAutoModes 426 * #define AUTOMODES_ENTER_OFF 0x00 // Default 427 * #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20 428 * #define AUTOMODES_ENTER_FIFOLEVEL 0x40 429 * #define AUTOMODES_ENTER_CRCOK 0x60 430 * #define AUTOMODES_ENTER_PAYLOADREADY 0x80 431 * #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0 432 * #define AUTOMODES_ENTER_PACKETSENT 0xC0 433 * #define AUTOMODES_ENTER_FIFOEMPTY 0xE0 434 * 435 * #define AUTOMODES_EXIT_OFF 0x00 // Default 436 * #define AUTOMODES_EXIT_FIFOEMPTY 0x04 437 * #define AUTOMODES_EXIT_FIFOLEVEL 0x08 438 * #define AUTOMODES_EXIT_CRCOK 0x0C 439 * #define AUTOMODES_EXIT_PAYLOADREADY 0x10 440 * #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14 441 * #define AUTOMODES_EXIT_PACKETSENT 0x18 442 * #define AUTOMODES_EXIT_RXTIMEOUT 0x1C 443 * 444 * #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default 445 * #define AUTOMODES_INTERMEDIATE_STANDBY 0x01 446 * #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02 447 * #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03 448 * 449 */ 450 /* RegFifoThresh (0x3c) */ 451 #define MASK_FIFO_THRESH_TXSTART 0x80 452 #define MASK_FIFO_THRESH_VALUE 0x7F 453 454 /* 455 * 456 * // RegPacketConfig2 457 * #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default 458 * #define PACKET2_RXRESTARTDELAY_2BITS 0x10 459 * #define PACKET2_RXRESTARTDELAY_4BITS 0x20 460 * #define PACKET2_RXRESTARTDELAY_8BITS 0x30 461 * #define PACKET2_RXRESTARTDELAY_16BITS 0x40 462 * #define PACKET2_RXRESTARTDELAY_32BITS 0x50 463 * #define PACKET2_RXRESTARTDELAY_64BITS 0x60 464 * #define PACKET2_RXRESTARTDELAY_128BITS 0x70 465 * #define PACKET2_RXRESTARTDELAY_256BITS 0x80 466 * #define PACKET2_RXRESTARTDELAY_512BITS 0x90 467 * #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0 468 * #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0 469 * #define PACKET2_RXRESTARTDELAY_NONE 0xC0 470 * #define PACKET2_RXRESTART 0x04 471 * 472 * #define PACKET2_AUTORXRESTART_ON 0x02 // Default 473 * #define PACKET2_AUTORXRESTART_OFF 0x00 474 * 475 * #define PACKET2_AES_ON 0x01 476 * #define PACKET2_AES_OFF 0x00 // Default 477 * 478 * 479 * // RegTemp1 480 * #define TEMP1_MEAS_START 0x08 481 * #define TEMP1_MEAS_RUNNING 0x04 482 * #define TEMP1_ADCLOWPOWER_ON 0x01 // Default 483 * #define TEMP1_ADCLOWPOWER_OFF 0x00 484 */ 485 486 // RegTestDagc (0x6F) 487 #define DAGC_NORMAL 0x00 /* Reset value */ 488 #define DAGC_IMPROVED_LOWBETA1 0x20 489 #define DAGC_IMPROVED_LOWBETA0 0x30 /* Recommended val */ 490