1874bcba6SMarcus Wolf /* 2874bcba6SMarcus Wolf * register description for HopeRf rf69 radio module 3874bcba6SMarcus Wolf * 4874bcba6SMarcus Wolf * Copyright (C) 2016 Wolf-Entwicklungen 5874bcba6SMarcus Wolf * Marcus Wolf <linux@wolf-entwicklungen.de> 6874bcba6SMarcus Wolf * 7874bcba6SMarcus Wolf * This program is free software; you can redistribute it and/or modify 8874bcba6SMarcus Wolf * it under the terms of the GNU General Public License as published by 9874bcba6SMarcus Wolf * the Free Software Foundation; either version 2 of the License, or 10874bcba6SMarcus Wolf * (at your option) any later version. 11874bcba6SMarcus Wolf * 12874bcba6SMarcus Wolf * This program is distributed in the hope that it will be useful, 13874bcba6SMarcus Wolf * but WITHOUT ANY WARRANTY; without even the implied warranty of 14874bcba6SMarcus Wolf * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15874bcba6SMarcus Wolf * GNU General Public License for more details. 16874bcba6SMarcus Wolf */ 17874bcba6SMarcus Wolf 18874bcba6SMarcus Wolf /*******************************************/ 19874bcba6SMarcus Wolf /* RF69 register addresses */ 20874bcba6SMarcus Wolf /*******************************************/ 21874bcba6SMarcus Wolf #define REG_FIFO 0x00 22874bcba6SMarcus Wolf #define REG_OPMODE 0x01 23874bcba6SMarcus Wolf #define REG_DATAMODUL 0x02 24874bcba6SMarcus Wolf #define REG_BITRATE_MSB 0x03 25874bcba6SMarcus Wolf #define REG_BITRATE_LSB 0x04 26874bcba6SMarcus Wolf #define REG_FDEV_MSB 0x05 27874bcba6SMarcus Wolf #define REG_FDEV_LSB 0x06 28874bcba6SMarcus Wolf #define REG_FRF_MSB 0x07 29874bcba6SMarcus Wolf #define REG_FRF_MID 0x08 30874bcba6SMarcus Wolf #define REG_FRF_LSB 0x09 31874bcba6SMarcus Wolf #define REG_OSC1 0x0A 32874bcba6SMarcus Wolf #define REG_AFCCTRL 0x0B 33874bcba6SMarcus Wolf #define REG_LOWBAT 0x0C 34874bcba6SMarcus Wolf #define REG_LISTEN1 0x0D 35874bcba6SMarcus Wolf #define REG_LISTEN2 0x0E 36874bcba6SMarcus Wolf #define REG_LISTEN3 0x0F 37874bcba6SMarcus Wolf #define REG_VERSION 0x10 38874bcba6SMarcus Wolf #define REG_PALEVEL 0x11 39874bcba6SMarcus Wolf #define REG_PARAMP 0x12 40874bcba6SMarcus Wolf #define REG_OCP 0x13 41874bcba6SMarcus Wolf #define REG_AGCREF 0x14 /* not available on RF69 */ 42874bcba6SMarcus Wolf #define REG_AGCTHRESH1 0x15 /* not available on RF69 */ 43874bcba6SMarcus Wolf #define REG_AGCTHRESH2 0x16 /* not available on RF69 */ 44874bcba6SMarcus Wolf #define REG_AGCTHRESH3 0x17 /* not available on RF69 */ 45874bcba6SMarcus Wolf #define REG_LNA 0x18 46874bcba6SMarcus Wolf #define REG_RXBW 0x19 47874bcba6SMarcus Wolf #define REG_AFCBW 0x1A 48874bcba6SMarcus Wolf #define REG_OOKPEAK 0x1B 49874bcba6SMarcus Wolf #define REG_OOKAVG 0x1C 50874bcba6SMarcus Wolf #define REG_OOKFIX 0x1D 51874bcba6SMarcus Wolf #define REG_AFCFEI 0x1E 52874bcba6SMarcus Wolf #define REG_AFCMSB 0x1F 53874bcba6SMarcus Wolf #define REG_AFCLSB 0x20 54874bcba6SMarcus Wolf #define REG_FEIMSB 0x21 55874bcba6SMarcus Wolf #define REG_FEILSB 0x22 56874bcba6SMarcus Wolf #define REG_RSSICONFIG 0x23 57874bcba6SMarcus Wolf #define REG_RSSIVALUE 0x24 58874bcba6SMarcus Wolf #define REG_DIOMAPPING1 0x25 59874bcba6SMarcus Wolf #define REG_DIOMAPPING2 0x26 60874bcba6SMarcus Wolf #define REG_IRQFLAGS1 0x27 61874bcba6SMarcus Wolf #define REG_IRQFLAGS2 0x28 62874bcba6SMarcus Wolf #define REG_RSSITHRESH 0x29 63874bcba6SMarcus Wolf #define REG_RXTIMEOUT1 0x2A 64874bcba6SMarcus Wolf #define REG_RXTIMEOUT2 0x2B 65874bcba6SMarcus Wolf #define REG_PREAMBLE_MSB 0x2C 66874bcba6SMarcus Wolf #define REG_PREAMBLE_LSB 0x2D 67874bcba6SMarcus Wolf #define REG_SYNC_CONFIG 0x2E 68874bcba6SMarcus Wolf #define REG_SYNCVALUE1 0x2F 69874bcba6SMarcus Wolf #define REG_SYNCVALUE2 0x30 70874bcba6SMarcus Wolf #define REG_SYNCVALUE3 0x31 71874bcba6SMarcus Wolf #define REG_SYNCVALUE4 0x32 72874bcba6SMarcus Wolf #define REG_SYNCVALUE5 0x33 73874bcba6SMarcus Wolf #define REG_SYNCVALUE6 0x34 74874bcba6SMarcus Wolf #define REG_SYNCVALUE7 0x35 75874bcba6SMarcus Wolf #define REG_SYNCVALUE8 0x36 76874bcba6SMarcus Wolf #define REG_PACKETCONFIG1 0x37 77874bcba6SMarcus Wolf #define REG_PAYLOAD_LENGTH 0x38 78874bcba6SMarcus Wolf #define REG_NODEADRS 0x39 79874bcba6SMarcus Wolf #define REG_BROADCASTADRS 0x3A 80874bcba6SMarcus Wolf #define REG_AUTOMODES 0x3B 81874bcba6SMarcus Wolf #define REG_FIFO_THRESH 0x3C 82874bcba6SMarcus Wolf #define REG_PACKETCONFIG2 0x3D 83874bcba6SMarcus Wolf #define REG_AESKEY1 0x3E 84874bcba6SMarcus Wolf #define REG_AESKEY2 0x3F 85874bcba6SMarcus Wolf #define REG_AESKEY3 0x40 86874bcba6SMarcus Wolf #define REG_AESKEY4 0x41 87874bcba6SMarcus Wolf #define REG_AESKEY5 0x42 88874bcba6SMarcus Wolf #define REG_AESKEY6 0x43 89874bcba6SMarcus Wolf #define REG_AESKEY7 0x44 90874bcba6SMarcus Wolf #define REG_AESKEY8 0x45 91874bcba6SMarcus Wolf #define REG_AESKEY9 0x46 92874bcba6SMarcus Wolf #define REG_AESKEY10 0x47 93874bcba6SMarcus Wolf #define REG_AESKEY11 0x48 94874bcba6SMarcus Wolf #define REG_AESKEY12 0x49 95874bcba6SMarcus Wolf #define REG_AESKEY13 0x4A 96874bcba6SMarcus Wolf #define REG_AESKEY14 0x4B 97874bcba6SMarcus Wolf #define REG_AESKEY15 0x4C 98874bcba6SMarcus Wolf #define REG_AESKEY16 0x4D 99874bcba6SMarcus Wolf #define REG_TEMP1 0x4E 100874bcba6SMarcus Wolf #define REG_TEMP2 0x4F 101874bcba6SMarcus Wolf #define REG_TESTPA1 0x5A /* only present on RFM69HW */ 102874bcba6SMarcus Wolf #define REG_TESTPA2 0x5C /* only present on RFM69HW */ 103874bcba6SMarcus Wolf #define REG_TESTDAGC 0x6F 104874bcba6SMarcus Wolf 105874bcba6SMarcus Wolf /******************************************************/ 106874bcba6SMarcus Wolf /* RF69/SX1231 bit definition */ 107874bcba6SMarcus Wolf /******************************************************/ 108874bcba6SMarcus Wolf /* write bit */ 109874bcba6SMarcus Wolf #define WRITE_BIT 0x80 110874bcba6SMarcus Wolf 111874bcba6SMarcus Wolf /* RegOpMode */ 112874bcba6SMarcus Wolf #define MASK_OPMODE_SEQUENCER_OFF 0x80 113874bcba6SMarcus Wolf #define MASK_OPMODE_LISTEN_ON 0x40 114874bcba6SMarcus Wolf #define MASK_OPMODE_LISTEN_ABORT 0x20 115874bcba6SMarcus Wolf #define MASK_OPMODE_MODE 0x1C 116874bcba6SMarcus Wolf 117874bcba6SMarcus Wolf #define OPMODE_MODE_SLEEP 0x00 118874bcba6SMarcus Wolf #define OPMODE_MODE_STANDBY 0x04 /* default */ 119874bcba6SMarcus Wolf #define OPMODE_MODE_SYNTHESIZER 0x08 120874bcba6SMarcus Wolf #define OPMODE_MODE_TRANSMIT 0x0C 121874bcba6SMarcus Wolf #define OPMODE_MODE_RECEIVE 0x10 122874bcba6SMarcus Wolf 123874bcba6SMarcus Wolf /* RegDataModul */ 124874bcba6SMarcus Wolf #define MASK_DATAMODUL_MODE 0x06 125874bcba6SMarcus Wolf #define MASK_DATAMODUL_MODULATION_TYPE 0x18 126874bcba6SMarcus Wolf #define MASK_DATAMODUL_MODULATION_SHAPE 0x03 127874bcba6SMarcus Wolf 128874bcba6SMarcus Wolf #define DATAMODUL_MODE_PACKET 0x00 /* default */ 129874bcba6SMarcus Wolf #define DATAMODUL_MODE_CONTINUOUS 0x40 130874bcba6SMarcus Wolf #define DATAMODUL_MODE_CONTINUOUS_NOSYNC 0x60 131874bcba6SMarcus Wolf 132874bcba6SMarcus Wolf #define DATAMODUL_MODULATION_TYPE_FSK 0x00 /* default */ 133874bcba6SMarcus Wolf #define DATAMODUL_MODULATION_TYPE_OOK 0x08 134874bcba6SMarcus Wolf 135874bcba6SMarcus Wolf #define DATAMODUL_MODULATION_SHAPE_NONE 0x00 /* default */ 136874bcba6SMarcus Wolf #define DATAMODUL_MODULATION_SHAPE_1_0 0x01 137874bcba6SMarcus Wolf #define DATAMODUL_MODULATION_SHAPE_0_5 0x02 138874bcba6SMarcus Wolf #define DATAMODUL_MODULATION_SHAPE_0_3 0x03 139874bcba6SMarcus Wolf #define DATAMODUL_MODULATION_SHAPE_BR 0x01 140874bcba6SMarcus Wolf #define DATAMODUL_MODULATION_SHAPE_2BR 0x02 141874bcba6SMarcus Wolf 142874bcba6SMarcus Wolf /* RegFDevMsb (0x05)*/ 143874bcba6SMarcus Wolf #define FDEVMASB_MASK 0x3f 144874bcba6SMarcus Wolf 145874bcba6SMarcus Wolf /* 146056eeda2SDerek Robson * // RegOsc1 147056eeda2SDerek Robson * #define OSC1_RCCAL_START 0x80 148056eeda2SDerek Robson * #define OSC1_RCCAL_DONE 0x40 149056eeda2SDerek Robson * 150056eeda2SDerek Robson * // RegLowBat 151056eeda2SDerek Robson * #define LOWBAT_MONITOR 0x10 152056eeda2SDerek Robson * #define LOWBAT_ON 0x08 153056eeda2SDerek Robson * #define LOWBAT_OFF 0x00 // Default 154056eeda2SDerek Robson * 155056eeda2SDerek Robson * #define LOWBAT_TRIM_1695 0x00 156056eeda2SDerek Robson * #define LOWBAT_TRIM_1764 0x01 157056eeda2SDerek Robson * #define LOWBAT_TRIM_1835 0x02 // Default 158056eeda2SDerek Robson * #define LOWBAT_TRIM_1905 0x03 159056eeda2SDerek Robson * #define LOWBAT_TRIM_1976 0x04 160056eeda2SDerek Robson * #define LOWBAT_TRIM_2045 0x05 161056eeda2SDerek Robson * #define LOWBAT_TRIM_2116 0x06 162056eeda2SDerek Robson * #define LOWBAT_TRIM_2185 0x07 163056eeda2SDerek Robson * 164056eeda2SDerek Robson * 165056eeda2SDerek Robson * // RegListen1 166056eeda2SDerek Robson * #define LISTEN1_RESOL_64 0x50 167056eeda2SDerek Robson * #define LISTEN1_RESOL_4100 0xA0 // Default 168056eeda2SDerek Robson * #define LISTEN1_RESOL_262000 0xF0 169056eeda2SDerek Robson * 170056eeda2SDerek Robson * #define LISTEN1_CRITERIA_RSSI 0x00 // Default 171056eeda2SDerek Robson * #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08 172056eeda2SDerek Robson * 173056eeda2SDerek Robson * #define LISTEN1_END_00 0x00 174056eeda2SDerek Robson * #define LISTEN1_END_01 0x02 // Default 175056eeda2SDerek Robson * #define LISTEN1_END_10 0x04 176056eeda2SDerek Robson * 177056eeda2SDerek Robson * 178056eeda2SDerek Robson * // RegListen2 179056eeda2SDerek Robson * #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default 180056eeda2SDerek Robson * 181056eeda2SDerek Robson * // RegListen3 182056eeda2SDerek Robson * #define LISTEN3_COEFRX_VALUE 0x20 // Default 183874bcba6SMarcus Wolf */ 184874bcba6SMarcus Wolf 185874bcba6SMarcus Wolf // RegPaLevel 186874bcba6SMarcus Wolf #define MASK_PALEVEL_PA0 0x80 187874bcba6SMarcus Wolf #define MASK_PALEVEL_PA1 0x40 188874bcba6SMarcus Wolf #define MASK_PALEVEL_PA2 0x20 189874bcba6SMarcus Wolf #define MASK_PALEVEL_OUTPUT_POWER 0x1F 190874bcba6SMarcus Wolf 191874bcba6SMarcus Wolf 192874bcba6SMarcus Wolf 193874bcba6SMarcus Wolf // RegPaRamp 194874bcba6SMarcus Wolf #define PARAMP_3400 0x00 195874bcba6SMarcus Wolf #define PARAMP_2000 0x01 196874bcba6SMarcus Wolf #define PARAMP_1000 0x02 197874bcba6SMarcus Wolf #define PARAMP_500 0x03 198874bcba6SMarcus Wolf #define PARAMP_250 0x04 199874bcba6SMarcus Wolf #define PARAMP_125 0x05 200874bcba6SMarcus Wolf #define PARAMP_100 0x06 201874bcba6SMarcus Wolf #define PARAMP_62 0x07 202874bcba6SMarcus Wolf #define PARAMP_50 0x08 203874bcba6SMarcus Wolf #define PARAMP_40 0x09 /* default */ 204874bcba6SMarcus Wolf #define PARAMP_31 0x0A 205874bcba6SMarcus Wolf #define PARAMP_25 0x0B 206874bcba6SMarcus Wolf #define PARAMP_20 0x0C 207874bcba6SMarcus Wolf #define PARAMP_15 0x0D 208874bcba6SMarcus Wolf #define PARAMP_12 0x0E 209874bcba6SMarcus Wolf #define PARAMP_10 0x0F 210874bcba6SMarcus Wolf 211874bcba6SMarcus Wolf #define MASK_PARAMP 0x0F 212874bcba6SMarcus Wolf 213874bcba6SMarcus Wolf /* 214056eeda2SDerek Robson * // RegOcp 215056eeda2SDerek Robson * #define OCP_OFF 0x0F 216056eeda2SDerek Robson * #define OCP_ON 0x1A // Default 217056eeda2SDerek Robson * 218056eeda2SDerek Robson * #define OCP_TRIM_45 0x00 219056eeda2SDerek Robson * #define OCP_TRIM_50 0x01 220056eeda2SDerek Robson * #define OCP_TRIM_55 0x02 221056eeda2SDerek Robson * #define OCP_TRIM_60 0x03 222056eeda2SDerek Robson * #define OCP_TRIM_65 0x04 223056eeda2SDerek Robson * #define OCP_TRIM_70 0x05 224056eeda2SDerek Robson * #define OCP_TRIM_75 0x06 225056eeda2SDerek Robson * #define OCP_TRIM_80 0x07 226056eeda2SDerek Robson * #define OCP_TRIM_85 0x08 227056eeda2SDerek Robson * #define OCP_TRIM_90 0x09 228056eeda2SDerek Robson * #define OCP_TRIM_95 0x0A 229056eeda2SDerek Robson * #define OCP_TRIM_100 0x0B // Default 230056eeda2SDerek Robson * #define OCP_TRIM_105 0x0C 231056eeda2SDerek Robson * #define OCP_TRIM_110 0x0D 232056eeda2SDerek Robson * #define OCP_TRIM_115 0x0E 233056eeda2SDerek Robson * #define OCP_TRIM_120 0x0F 234874bcba6SMarcus Wolf */ 235874bcba6SMarcus Wolf 236874bcba6SMarcus Wolf /* RegLna (0x18) */ 237874bcba6SMarcus Wolf #define MASK_LNA_ZIN 0x80 238874bcba6SMarcus Wolf #define MASK_LNA_CURRENT_GAIN 0x38 239874bcba6SMarcus Wolf #define MASK_LNA_GAIN 0x07 240874bcba6SMarcus Wolf 241874bcba6SMarcus Wolf #define LNA_GAIN_AUTO 0x00 /* default */ 242874bcba6SMarcus Wolf #define LNA_GAIN_MAX 0x01 243874bcba6SMarcus Wolf #define LNA_GAIN_MAX_MINUS_6 0x02 244874bcba6SMarcus Wolf #define LNA_GAIN_MAX_MINUS_12 0x03 245874bcba6SMarcus Wolf #define LNA_GAIN_MAX_MINUS_24 0x04 246874bcba6SMarcus Wolf #define LNA_GAIN_MAX_MINUS_36 0x05 247874bcba6SMarcus Wolf #define LNA_GAIN_MAX_MINUS_48 0x06 248874bcba6SMarcus Wolf 249874bcba6SMarcus Wolf 250874bcba6SMarcus Wolf /* RegRxBw (0x19) and RegAfcBw (0x1A) */ 251874bcba6SMarcus Wolf #define MASK_BW_DCC_FREQ 0xE0 252874bcba6SMarcus Wolf #define MASK_BW_MANTISSE 0x18 253874bcba6SMarcus Wolf #define MASK_BW_EXPONENT 0x07 254874bcba6SMarcus Wolf 255874bcba6SMarcus Wolf #define BW_DCC_16_PERCENT 0x00 256874bcba6SMarcus Wolf #define BW_DCC_8_PERCENT 0x20 257874bcba6SMarcus Wolf #define BW_DCC_4_PERCENT 0x40 /* default */ 258874bcba6SMarcus Wolf #define BW_DCC_2_PERCENT 0x60 259874bcba6SMarcus Wolf #define BW_DCC_1_PERCENT 0x80 260874bcba6SMarcus Wolf #define BW_DCC_0_5_PERCENT 0xA0 261874bcba6SMarcus Wolf #define BW_DCC_0_25_PERCENT 0xC0 262874bcba6SMarcus Wolf #define BW_DCC_0_125_PERCENT 0xE0 263874bcba6SMarcus Wolf 264874bcba6SMarcus Wolf #define BW_MANT_16 0x00 265874bcba6SMarcus Wolf #define BW_MANT_20 0x08 266874bcba6SMarcus Wolf #define BW_MANT_24 0x10 /* default */ 267874bcba6SMarcus Wolf 268874bcba6SMarcus Wolf 269874bcba6SMarcus Wolf /* RegOokPeak (0x1B) */ 270874bcba6SMarcus Wolf #define MASK_OOKPEAK_THRESTYPE 0xc0 271874bcba6SMarcus Wolf #define MASK_OOKPEAK_THRESSTEP 0x38 272874bcba6SMarcus Wolf #define MASK_OOKPEAK_THRESDEC 0x07 273874bcba6SMarcus Wolf 274874bcba6SMarcus Wolf #define OOKPEAK_THRESHTYPE_FIXED 0x00 275874bcba6SMarcus Wolf #define OOKPEAK_THRESHTYPE_PEAK 0x40 /* default */ 276874bcba6SMarcus Wolf #define OOKPEAK_THRESHTYPE_AVERAGE 0x80 277874bcba6SMarcus Wolf 278874bcba6SMarcus Wolf #define OOKPEAK_THRESHSTEP_0_5_DB 0x00 /* default */ 279874bcba6SMarcus Wolf #define OOKPEAK_THRESHSTEP_1_0_DB 0x08 280874bcba6SMarcus Wolf #define OOKPEAK_THRESHSTEP_1_5_DB 0x10 281874bcba6SMarcus Wolf #define OOKPEAK_THRESHSTEP_2_0_DB 0x18 282874bcba6SMarcus Wolf #define OOKPEAK_THRESHSTEP_3_0_DB 0x20 283874bcba6SMarcus Wolf #define OOKPEAK_THRESHSTEP_4_0_DB 0x28 284874bcba6SMarcus Wolf #define OOKPEAK_THRESHSTEP_5_0_DB 0x30 285874bcba6SMarcus Wolf #define OOKPEAK_THRESHSTEP_6_0_DB 0x38 286874bcba6SMarcus Wolf 287874bcba6SMarcus Wolf #define OOKPEAK_THRESHDEC_ONCE 0x00 /* default */ 288874bcba6SMarcus Wolf #define OOKPEAK_THRESHDEC_EVERY_2ND 0x01 289874bcba6SMarcus Wolf #define OOKPEAK_THRESHDEC_EVERY_4TH 0x02 290874bcba6SMarcus Wolf #define OOKPEAK_THRESHDEC_EVERY_8TH 0x03 291874bcba6SMarcus Wolf #define OOKPEAK_THRESHDEC_TWICE 0x04 292874bcba6SMarcus Wolf #define OOKPEAK_THRESHDEC_4_TIMES 0x05 293874bcba6SMarcus Wolf #define OOKPEAK_THRESHDEC_8_TIMES 0x06 294874bcba6SMarcus Wolf #define OOKPEAK_THRESHDEC_16_TIMES 0x07 295874bcba6SMarcus Wolf 296874bcba6SMarcus Wolf /* 297056eeda2SDerek Robson * // RegOokAvg 298056eeda2SDerek Robson * #define OOKAVG_AVERAGETHRESHFILT_00 0x00 299056eeda2SDerek Robson * #define OOKAVG_AVERAGETHRESHFILT_01 0x40 300056eeda2SDerek Robson * #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default 301056eeda2SDerek Robson * #define OOKAVG_AVERAGETHRESHFILT_11 0xC0 302056eeda2SDerek Robson * 303056eeda2SDerek Robson * 304056eeda2SDerek Robson * // RegAfcFei 305056eeda2SDerek Robson * #define AFCFEI_FEI_DONE 0x40 306056eeda2SDerek Robson * #define AFCFEI_FEI_START 0x20 307056eeda2SDerek Robson * #define AFCFEI_AFC_DONE 0x10 308056eeda2SDerek Robson * #define AFCFEI_AFCAUTOCLEAR_ON 0x08 309056eeda2SDerek Robson * #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default 310056eeda2SDerek Robson * 311056eeda2SDerek Robson * #define AFCFEI_AFCAUTO_ON 0x04 312056eeda2SDerek Robson * #define AFCFEI_AFCAUTO_OFF 0x00 // Default 313056eeda2SDerek Robson * 314056eeda2SDerek Robson * #define AFCFEI_AFC_CLEAR 0x02 315056eeda2SDerek Robson * #define AFCFEI_AFC_START 0x01 316056eeda2SDerek Robson * 317056eeda2SDerek Robson * // RegRssiConfig 318056eeda2SDerek Robson * #define RSSI_FASTRX_ON 0x08 319056eeda2SDerek Robson * #define RSSI_FASTRX_OFF 0x00 // Default 320056eeda2SDerek Robson * #define RSSI_DONE 0x02 321056eeda2SDerek Robson * #define RSSI_START 0x01 322874bcba6SMarcus Wolf */ 323874bcba6SMarcus Wolf 324874bcba6SMarcus Wolf /* RegDioMapping1 */ 325874bcba6SMarcus Wolf #define MASK_DIO0 0xC0 326874bcba6SMarcus Wolf #define MASK_DIO1 0x30 327874bcba6SMarcus Wolf #define MASK_DIO2 0x0C 328874bcba6SMarcus Wolf #define MASK_DIO3 0x03 329874bcba6SMarcus Wolf #define SHIFT_DIO0 6 330874bcba6SMarcus Wolf #define SHIFT_DIO1 4 331874bcba6SMarcus Wolf #define SHIFT_DIO2 2 332874bcba6SMarcus Wolf #define SHIFT_DIO3 0 333874bcba6SMarcus Wolf 334874bcba6SMarcus Wolf /* RegDioMapping2 */ 335874bcba6SMarcus Wolf #define MASK_DIO4 0xC0 336874bcba6SMarcus Wolf #define MASK_DIO5 0x30 337874bcba6SMarcus Wolf #define SHIFT_DIO4 6 338874bcba6SMarcus Wolf #define SHIFT_DIO5 4 339874bcba6SMarcus Wolf 340874bcba6SMarcus Wolf /* DIO numbers */ 341874bcba6SMarcus Wolf #define DIO0 0 342874bcba6SMarcus Wolf #define DIO1 1 343874bcba6SMarcus Wolf #define DIO2 2 344874bcba6SMarcus Wolf #define DIO3 3 345874bcba6SMarcus Wolf #define DIO4 4 346874bcba6SMarcus Wolf #define DIO5 5 347874bcba6SMarcus Wolf 348874bcba6SMarcus Wolf /* DIO Mapping values (packet mode) */ 3493d7f3bf2SSimon Sandström #define DIO_MODE_READY_DIO4 0x00 3503d7f3bf2SSimon Sandström #define DIO_MODE_READY_DIO5 0x03 3513d7f3bf2SSimon Sandström #define DIO_CLK_OUT 0x00 3523d7f3bf2SSimon Sandström #define DIO_DATA 0x01 3533d7f3bf2SSimon Sandström #define DIO_TIMEOUT_DIO1 0x03 3543d7f3bf2SSimon Sandström #define DIO_TIMEOUT_DIO4 0x00 3553d7f3bf2SSimon Sandström #define DIO_RSSI_DIO0 0x03 3563d7f3bf2SSimon Sandström #define DIO_RSSI_DIO3_4 0x01 3573d7f3bf2SSimon Sandström #define DIO_RX_READY 0x02 3583d7f3bf2SSimon Sandström #define DIO_PLL_LOCK 0x03 3593d7f3bf2SSimon Sandström #define DIO_TX_READY 0x01 3603d7f3bf2SSimon Sandström #define DIO_FIFO_FULL_DIO1 0x01 3613d7f3bf2SSimon Sandström #define DIO_FIFO_FULL_DIO3 0x00 3623d7f3bf2SSimon Sandström #define DIO_SYNC_ADDRESS 0x02 3633d7f3bf2SSimon Sandström #define DIO_FIFO_NOT_EMPTY_DIO1 0x02 3643d7f3bf2SSimon Sandström #define DIO_FIFO_NOT_EMPTY_FIO2 0x00 3653d7f3bf2SSimon Sandström #define DIO_AUTOMODE 0x04 3663d7f3bf2SSimon Sandström #define DIO_FIFO_LEVEL 0x00 3673d7f3bf2SSimon Sandström #define DIO_CRC_OK 0x00 3683d7f3bf2SSimon Sandström #define DIO_PAYLOAD_READY 0x01 3693d7f3bf2SSimon Sandström #define DIO_PACKET_SENT 0x00 3703d7f3bf2SSimon Sandström #define DIO_DCLK 0x00 371874bcba6SMarcus Wolf 372874bcba6SMarcus Wolf /* RegDioMapping2 CLK_OUT part */ 373874bcba6SMarcus Wolf #define MASK_DIOMAPPING2_CLK_OUT 0x07 374874bcba6SMarcus Wolf 375874bcba6SMarcus Wolf #define DIOMAPPING2_CLK_OUT_NO_DIV 0x00 376874bcba6SMarcus Wolf #define DIOMAPPING2_CLK_OUT_DIV_2 0x01 377874bcba6SMarcus Wolf #define DIOMAPPING2_CLK_OUT_DIV_4 0x02 378874bcba6SMarcus Wolf #define DIOMAPPING2_CLK_OUT_DIV_8 0x03 379874bcba6SMarcus Wolf #define DIOMAPPING2_CLK_OUT_DIV_16 0x04 380874bcba6SMarcus Wolf #define DIOMAPPING2_CLK_OUT_DIV_32 0x05 381874bcba6SMarcus Wolf #define DIOMAPPING2_CLK_OUT_RC 0x06 382874bcba6SMarcus Wolf #define DIOMAPPING2_CLK_OUT_OFF 0x07 /* default */ 383874bcba6SMarcus Wolf 384874bcba6SMarcus Wolf /* RegIrqFlags1 */ 385874bcba6SMarcus Wolf #define MASK_IRQFLAGS1_MODE_READY 0x80 386874bcba6SMarcus Wolf #define MASK_IRQFLAGS1_RX_READY 0x40 387874bcba6SMarcus Wolf #define MASK_IRQFLAGS1_TX_READY 0x20 388874bcba6SMarcus Wolf #define MASK_IRQFLAGS1_PLL_LOCK 0x10 389874bcba6SMarcus Wolf #define MASK_IRQFLAGS1_RSSI 0x08 390874bcba6SMarcus Wolf #define MASK_IRQFLAGS1_TIMEOUT 0x04 391874bcba6SMarcus Wolf #define MASK_IRQFLAGS1_AUTOMODE 0x02 392874bcba6SMarcus Wolf #define MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH 0x01 393874bcba6SMarcus Wolf 394874bcba6SMarcus Wolf /* RegIrqFlags2 */ 395874bcba6SMarcus Wolf #define MASK_IRQFLAGS2_FIFO_FULL 0x80 396874bcba6SMarcus Wolf #define MASK_IRQFLAGS2_FIFO_NOT_EMPTY 0x40 397874bcba6SMarcus Wolf #define MASK_IRQFLAGS2_FIFO_LEVEL 0x20 398874bcba6SMarcus Wolf #define MASK_IRQFLAGS2_FIFO_OVERRUN 0x10 399874bcba6SMarcus Wolf #define MASK_IRQFLAGS2_PACKET_SENT 0x08 400874bcba6SMarcus Wolf #define MASK_IRQFLAGS2_PAYLOAD_READY 0x04 401874bcba6SMarcus Wolf #define MASK_IRQFLAGS2_CRC_OK 0x02 402874bcba6SMarcus Wolf #define MASK_IRQFLAGS2_LOW_BAT 0x01 403874bcba6SMarcus Wolf 404874bcba6SMarcus Wolf /* RegSyncConfig */ 405874bcba6SMarcus Wolf #define MASK_SYNC_CONFIG_SYNC_ON 0x80 /* default */ 406874bcba6SMarcus Wolf #define MASK_SYNC_CONFIG_FIFO_FILL_CONDITION 0x40 407874bcba6SMarcus Wolf #define MASK_SYNC_CONFIG_SYNC_SIZE 0x38 408874bcba6SMarcus Wolf #define MASK_SYNC_CONFIG_SYNC_TOLERANCE 0x07 409874bcba6SMarcus Wolf 410874bcba6SMarcus Wolf /* RegPacketConfig1 */ 411874bcba6SMarcus Wolf #define MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE 0x80 412874bcba6SMarcus Wolf #define MASK_PACKETCONFIG1_DCFREE 0x60 413874bcba6SMarcus Wolf #define MASK_PACKETCONFIG1_CRC_ON 0x10 /* default */ 414874bcba6SMarcus Wolf #define MASK_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 415874bcba6SMarcus Wolf #define MASK_PACKETCONFIG1_ADDRESSFILTERING 0x06 416874bcba6SMarcus Wolf 417874bcba6SMarcus Wolf #define PACKETCONFIG1_DCFREE_OFF 0x00 /* default */ 418874bcba6SMarcus Wolf #define PACKETCONFIG1_DCFREE_MANCHESTER 0x20 419874bcba6SMarcus Wolf #define PACKETCONFIG1_DCFREE_WHITENING 0x40 420874bcba6SMarcus Wolf #define PACKETCONFIG1_ADDRESSFILTERING_OFF 0x00 /* default */ 421874bcba6SMarcus Wolf #define PACKETCONFIG1_ADDRESSFILTERING_NODE 0x02 422874bcba6SMarcus Wolf #define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04 423874bcba6SMarcus Wolf 424874bcba6SMarcus Wolf /* 425056eeda2SDerek Robson * // RegAutoModes 426056eeda2SDerek Robson * #define AUTOMODES_ENTER_OFF 0x00 // Default 427056eeda2SDerek Robson * #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20 428056eeda2SDerek Robson * #define AUTOMODES_ENTER_FIFOLEVEL 0x40 429056eeda2SDerek Robson * #define AUTOMODES_ENTER_CRCOK 0x60 430056eeda2SDerek Robson * #define AUTOMODES_ENTER_PAYLOADREADY 0x80 431056eeda2SDerek Robson * #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0 432056eeda2SDerek Robson * #define AUTOMODES_ENTER_PACKETSENT 0xC0 433056eeda2SDerek Robson * #define AUTOMODES_ENTER_FIFOEMPTY 0xE0 434056eeda2SDerek Robson * 435056eeda2SDerek Robson * #define AUTOMODES_EXIT_OFF 0x00 // Default 436056eeda2SDerek Robson * #define AUTOMODES_EXIT_FIFOEMPTY 0x04 437056eeda2SDerek Robson * #define AUTOMODES_EXIT_FIFOLEVEL 0x08 438056eeda2SDerek Robson * #define AUTOMODES_EXIT_CRCOK 0x0C 439056eeda2SDerek Robson * #define AUTOMODES_EXIT_PAYLOADREADY 0x10 440056eeda2SDerek Robson * #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14 441056eeda2SDerek Robson * #define AUTOMODES_EXIT_PACKETSENT 0x18 442056eeda2SDerek Robson * #define AUTOMODES_EXIT_RXTIMEOUT 0x1C 443056eeda2SDerek Robson * 444056eeda2SDerek Robson * #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default 445056eeda2SDerek Robson * #define AUTOMODES_INTERMEDIATE_STANDBY 0x01 446056eeda2SDerek Robson * #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02 447056eeda2SDerek Robson * #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03 448056eeda2SDerek Robson * 449874bcba6SMarcus Wolf */ 450874bcba6SMarcus Wolf /* RegFifoThresh (0x3c) */ 451874bcba6SMarcus Wolf #define MASK_FIFO_THRESH_TXSTART 0x80 452874bcba6SMarcus Wolf #define MASK_FIFO_THRESH_VALUE 0x7F 453874bcba6SMarcus Wolf 454874bcba6SMarcus Wolf /* 455056eeda2SDerek Robson * 456056eeda2SDerek Robson * // RegPacketConfig2 457056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default 458056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_2BITS 0x10 459056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_4BITS 0x20 460056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_8BITS 0x30 461056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_16BITS 0x40 462056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_32BITS 0x50 463056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_64BITS 0x60 464056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_128BITS 0x70 465056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_256BITS 0x80 466056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_512BITS 0x90 467056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0 468056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0 469056eeda2SDerek Robson * #define PACKET2_RXRESTARTDELAY_NONE 0xC0 470056eeda2SDerek Robson * #define PACKET2_RXRESTART 0x04 471056eeda2SDerek Robson * 472056eeda2SDerek Robson * #define PACKET2_AUTORXRESTART_ON 0x02 // Default 473056eeda2SDerek Robson * #define PACKET2_AUTORXRESTART_OFF 0x00 474056eeda2SDerek Robson * 475056eeda2SDerek Robson * #define PACKET2_AES_ON 0x01 476056eeda2SDerek Robson * #define PACKET2_AES_OFF 0x00 // Default 477056eeda2SDerek Robson * 478056eeda2SDerek Robson * 479056eeda2SDerek Robson * // RegTemp1 480056eeda2SDerek Robson * #define TEMP1_MEAS_START 0x08 481056eeda2SDerek Robson * #define TEMP1_MEAS_RUNNING 0x04 482056eeda2SDerek Robson * #define TEMP1_ADCLOWPOWER_ON 0x01 // Default 483056eeda2SDerek Robson * #define TEMP1_ADCLOWPOWER_OFF 0x00 484874bcba6SMarcus Wolf */ 485874bcba6SMarcus Wolf 486874bcba6SMarcus Wolf // RegTestDagc (0x6F) 487874bcba6SMarcus Wolf #define DAGC_NORMAL 0x00 /* Reset value */ 488874bcba6SMarcus Wolf #define DAGC_IMPROVED_LOWBETA1 0x20 489874bcba6SMarcus Wolf #define DAGC_IMPROVED_LOWBETA0 0x30 /* Recommended val */ 490