1 /* 2 * abstraction of the spi interface of HopeRf rf69 radio module 3 * 4 * Copyright (C) 2016 Wolf-Entwicklungen 5 * Marcus Wolf <linux@wolf-entwicklungen.de> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 /* enable prosa debug info */ 19 #undef DEBUG 20 /* enable print of values on reg access */ 21 #undef DEBUG_VALUES 22 /* enable print of values on fifo access */ 23 #undef DEBUG_FIFO_ACCESS 24 25 #include <linux/types.h> 26 #include <linux/spi/spi.h> 27 28 #include "rf69.h" 29 #include "rf69_registers.h" 30 31 #define F_OSC 32000000 /* in Hz */ 32 #define FIFO_SIZE 66 /* in byte */ 33 34 /*-------------------------------------------------------------------------*/ 35 36 static u8 rf69_read_reg(struct spi_device *spi, u8 addr) 37 { 38 int retval; 39 40 retval = spi_w8r8(spi, addr); 41 42 #ifdef DEBUG_VALUES 43 if (retval < 0) 44 /* should never happen, since we already checked, 45 * that module is connected. Therefore no error 46 * handling, just an optional error message... 47 */ 48 dev_dbg(&spi->dev, "read 0x%x FAILED\n", addr); 49 else 50 dev_dbg(&spi->dev, "read 0x%x from reg 0x%x\n", retval, addr); 51 #endif 52 53 return retval; 54 } 55 56 static int rf69_write_reg(struct spi_device *spi, u8 addr, u8 value) 57 { 58 int retval; 59 char buffer[2]; 60 61 buffer[0] = addr | WRITE_BIT; 62 buffer[1] = value; 63 64 retval = spi_write(spi, &buffer, 2); 65 66 #ifdef DEBUG_VALUES 67 if (retval < 0) 68 /* should never happen, since we already checked, 69 * that module is connected. Therefore no error 70 * handling, just an optional error message... 71 */ 72 dev_dbg(&spi->dev, "write 0x%x to 0x%x FAILED\n", value, addr); 73 else 74 dev_dbg(&spi->dev, "wrote 0x%x to reg 0x%x\n", value, addr); 75 #endif 76 77 return retval; 78 } 79 80 /*-------------------------------------------------------------------------*/ 81 82 static int rf69_set_bit(struct spi_device *spi, u8 reg, u8 mask) 83 { 84 u8 tmp; 85 86 tmp = rf69_read_reg(spi, reg); 87 tmp = tmp | mask; 88 return rf69_write_reg(spi, reg, tmp); 89 } 90 91 static int rf69_clear_bit(struct spi_device *spi, u8 reg, u8 mask) 92 { 93 u8 tmp; 94 95 tmp = rf69_read_reg(spi, reg); 96 tmp = tmp & ~mask; 97 return rf69_write_reg(spi, reg, tmp); 98 } 99 100 static inline int rf69_read_mod_write(struct spi_device *spi, u8 reg, u8 mask, u8 value) 101 { 102 u8 tmp; 103 104 tmp = rf69_read_reg(spi, reg); 105 tmp = (tmp & ~mask) | value; 106 return rf69_write_reg(spi, reg, tmp); 107 } 108 109 /*-------------------------------------------------------------------------*/ 110 111 int rf69_set_mode(struct spi_device *spi, enum mode mode) 112 { 113 switch (mode) { 114 case transmit: 115 return rf69_read_mod_write(spi, REG_OPMODE, MASK_OPMODE_MODE, OPMODE_MODE_TRANSMIT); 116 case receive: 117 return rf69_read_mod_write(spi, REG_OPMODE, MASK_OPMODE_MODE, OPMODE_MODE_RECEIVE); 118 case synthesizer: 119 return rf69_read_mod_write(spi, REG_OPMODE, MASK_OPMODE_MODE, OPMODE_MODE_SYNTHESIZER); 120 case standby: 121 return rf69_read_mod_write(spi, REG_OPMODE, MASK_OPMODE_MODE, OPMODE_MODE_STANDBY); 122 case mode_sleep: 123 return rf69_read_mod_write(spi, REG_OPMODE, MASK_OPMODE_MODE, OPMODE_MODE_SLEEP); 124 default: 125 dev_dbg(&spi->dev, "set: illegal input param"); 126 return -EINVAL; 127 } 128 129 // we are using packet mode, so this check is not really needed 130 // but waiting for mode ready is necessary when going from sleep because the FIFO may not be immediately available from previous mode 131 //while (_mode == RF69_MODE_SLEEP && (READ_REG(REG_IRQFLAGS1) & RF_IRQFLAGS1_MODEREADY) == 0x00); // Wait for ModeReady 132 } 133 134 int rf69_set_data_mode(struct spi_device *spi, u8 data_mode) 135 { 136 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODE, data_mode); 137 } 138 139 int rf69_set_modulation(struct spi_device *spi, enum modulation modulation) 140 { 141 switch (modulation) { 142 case OOK: 143 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODULATION_TYPE, DATAMODUL_MODULATION_TYPE_OOK); 144 case FSK: 145 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODULATION_TYPE, DATAMODUL_MODULATION_TYPE_FSK); 146 default: 147 dev_dbg(&spi->dev, "set: illegal input param"); 148 return -EINVAL; 149 } 150 } 151 152 static enum modulation rf69_get_modulation(struct spi_device *spi) 153 { 154 u8 currentValue; 155 156 currentValue = rf69_read_reg(spi, REG_DATAMODUL); 157 158 switch (currentValue & MASK_DATAMODUL_MODULATION_TYPE) { 159 case DATAMODUL_MODULATION_TYPE_OOK: 160 return OOK; 161 case DATAMODUL_MODULATION_TYPE_FSK: 162 return FSK; 163 default: 164 return UNDEF; 165 } 166 } 167 168 int rf69_set_modulation_shaping(struct spi_device *spi, 169 enum mod_shaping mod_shaping) 170 { 171 switch (rf69_get_modulation(spi)) { 172 case FSK: 173 switch (mod_shaping) { 174 case SHAPING_OFF: 175 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODULATION_SHAPE, DATAMODUL_MODULATION_SHAPE_NONE); 176 case SHAPING_1_0: 177 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODULATION_SHAPE, DATAMODUL_MODULATION_SHAPE_1_0); 178 case SHAPING_0_5: 179 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODULATION_SHAPE, DATAMODUL_MODULATION_SHAPE_0_5); 180 case SHAPING_0_3: 181 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODULATION_SHAPE, DATAMODUL_MODULATION_SHAPE_0_3); 182 default: 183 dev_dbg(&spi->dev, "set: illegal input param"); 184 return -EINVAL; 185 } 186 case OOK: 187 switch (mod_shaping) { 188 case SHAPING_OFF: 189 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODULATION_SHAPE, DATAMODUL_MODULATION_SHAPE_NONE); 190 case SHAPING_BR: 191 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODULATION_SHAPE, DATAMODUL_MODULATION_SHAPE_BR); 192 case SHAPING_2BR: 193 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODULATION_SHAPE, DATAMODUL_MODULATION_SHAPE_2BR); 194 default: 195 dev_dbg(&spi->dev, "set: illegal input param"); 196 return -EINVAL; 197 } 198 default: 199 dev_dbg(&spi->dev, "set: modulation undefined"); 200 return -EINVAL; 201 } 202 } 203 204 int rf69_set_bit_rate(struct spi_device *spi, u16 bitRate) 205 { 206 int retval; 207 u32 bitRate_min; 208 u32 bitRate_reg; 209 u8 msb; 210 u8 lsb; 211 212 // check input value 213 bitRate_min = F_OSC / 8388608; // 8388608 = 2^23; 214 if (bitRate < bitRate_min) { 215 dev_dbg(&spi->dev, "setBitRate: illegal input param"); 216 return -EINVAL; 217 } 218 219 // calculate reg settings 220 bitRate_reg = (F_OSC / bitRate); 221 222 msb = (bitRate_reg & 0xff00) >> 8; 223 lsb = (bitRate_reg & 0xff); 224 225 // transmit to RF 69 226 retval = rf69_write_reg(spi, REG_BITRATE_MSB, msb); 227 if (retval) 228 return retval; 229 retval = rf69_write_reg(spi, REG_BITRATE_LSB, lsb); 230 if (retval) 231 return retval; 232 233 return 0; 234 } 235 236 int rf69_set_deviation(struct spi_device *spi, u32 deviation) 237 { 238 int retval; 239 u64 f_reg; 240 u64 f_step; 241 u8 msb; 242 u8 lsb; 243 u64 factor = 1000000; // to improve precision of calculation 244 245 // TODO: Dependency to bitrate 246 if (deviation < 600 || deviation > 500000) { 247 dev_dbg(&spi->dev, "set_deviation: illegal input param"); 248 return -EINVAL; 249 } 250 251 // calculat f step 252 f_step = F_OSC * factor; 253 do_div(f_step, 524288); // 524288 = 2^19 254 255 // calculate register settings 256 f_reg = deviation * factor; 257 do_div(f_reg, f_step); 258 259 msb = (f_reg & 0xff00) >> 8; 260 lsb = (f_reg & 0xff); 261 262 // check msb 263 if (msb & ~FDEVMASB_MASK) { 264 dev_dbg(&spi->dev, "set_deviation: err in calc of msb"); 265 return -EINVAL; 266 } 267 268 // write to chip 269 retval = rf69_write_reg(spi, REG_FDEV_MSB, msb); 270 if (retval) 271 return retval; 272 retval = rf69_write_reg(spi, REG_FDEV_LSB, lsb); 273 if (retval) 274 return retval; 275 276 return 0; 277 } 278 279 int rf69_set_frequency(struct spi_device *spi, u32 frequency) 280 { 281 int retval; 282 u32 f_max; 283 u64 f_reg; 284 u64 f_step; 285 u8 msb; 286 u8 mid; 287 u8 lsb; 288 u64 factor = 1000000; // to improve precision of calculation 289 290 // calculat f step 291 f_step = F_OSC * factor; 292 do_div(f_step, 524288); // 524288 = 2^19 293 294 // check input value 295 f_max = div_u64(f_step * 8388608, factor); 296 if (frequency > f_max) { 297 dev_dbg(&spi->dev, "setFrequency: illegal input param"); 298 return -EINVAL; 299 } 300 301 // calculate reg settings 302 f_reg = frequency * factor; 303 do_div(f_reg, f_step); 304 305 msb = (f_reg & 0xff0000) >> 16; 306 mid = (f_reg & 0xff00) >> 8; 307 lsb = (f_reg & 0xff); 308 309 // write to chip 310 retval = rf69_write_reg(spi, REG_FRF_MSB, msb); 311 if (retval) 312 return retval; 313 retval = rf69_write_reg(spi, REG_FRF_MID, mid); 314 if (retval) 315 return retval; 316 retval = rf69_write_reg(spi, REG_FRF_LSB, lsb); 317 if (retval) 318 return retval; 319 320 return 0; 321 } 322 323 int rf69_enable_amplifier(struct spi_device *spi, u8 amplifier_mask) 324 { 325 return rf69_set_bit(spi, REG_PALEVEL, amplifier_mask); 326 } 327 328 int rf69_disable_amplifier(struct spi_device *spi, u8 amplifier_mask) 329 { 330 return rf69_clear_bit(spi, REG_PALEVEL, amplifier_mask); 331 } 332 333 int rf69_set_output_power_level(struct spi_device *spi, u8 powerLevel) 334 { 335 // TODO: Dependency to PA0,1,2 setting 336 powerLevel += 18; 337 338 // check input value 339 if (powerLevel > 0x1f) { 340 dev_dbg(&spi->dev, "set: illegal input param"); 341 return -EINVAL; 342 } 343 344 // write value 345 return rf69_read_mod_write(spi, REG_PALEVEL, MASK_PALEVEL_OUTPUT_POWER, powerLevel); 346 } 347 348 int rf69_set_pa_ramp(struct spi_device *spi, enum paRamp paRamp) 349 { 350 switch (paRamp) { 351 case ramp3400: 352 return rf69_write_reg(spi, REG_PARAMP, PARAMP_3400); 353 case ramp2000: 354 return rf69_write_reg(spi, REG_PARAMP, PARAMP_2000); 355 case ramp1000: 356 return rf69_write_reg(spi, REG_PARAMP, PARAMP_1000); 357 case ramp500: 358 return rf69_write_reg(spi, REG_PARAMP, PARAMP_500); 359 case ramp250: 360 return rf69_write_reg(spi, REG_PARAMP, PARAMP_250); 361 case ramp125: 362 return rf69_write_reg(spi, REG_PARAMP, PARAMP_125); 363 case ramp100: 364 return rf69_write_reg(spi, REG_PARAMP, PARAMP_100); 365 case ramp62: 366 return rf69_write_reg(spi, REG_PARAMP, PARAMP_62); 367 case ramp50: 368 return rf69_write_reg(spi, REG_PARAMP, PARAMP_50); 369 case ramp40: 370 return rf69_write_reg(spi, REG_PARAMP, PARAMP_40); 371 case ramp31: 372 return rf69_write_reg(spi, REG_PARAMP, PARAMP_31); 373 case ramp25: 374 return rf69_write_reg(spi, REG_PARAMP, PARAMP_25); 375 case ramp20: 376 return rf69_write_reg(spi, REG_PARAMP, PARAMP_20); 377 case ramp15: 378 return rf69_write_reg(spi, REG_PARAMP, PARAMP_15); 379 case ramp12: 380 return rf69_write_reg(spi, REG_PARAMP, PARAMP_12); 381 case ramp10: 382 return rf69_write_reg(spi, REG_PARAMP, PARAMP_10); 383 default: 384 dev_dbg(&spi->dev, "set: illegal input param"); 385 return -EINVAL; 386 } 387 } 388 389 int rf69_set_antenna_impedance(struct spi_device *spi, enum antennaImpedance antennaImpedance) 390 { 391 switch (antennaImpedance) { 392 case fiftyOhm: 393 return rf69_clear_bit(spi, REG_LNA, MASK_LNA_ZIN); 394 case twohundretOhm: 395 return rf69_set_bit(spi, REG_LNA, MASK_LNA_ZIN); 396 default: 397 dev_dbg(&spi->dev, "set: illegal input param"); 398 return -EINVAL; 399 } 400 } 401 402 int rf69_set_lna_gain(struct spi_device *spi, enum lnaGain lnaGain) 403 { 404 switch (lnaGain) { 405 case automatic: 406 return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN, LNA_GAIN_AUTO); 407 case max: 408 return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN, LNA_GAIN_MAX); 409 case max_minus_6: 410 return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN, LNA_GAIN_MAX_MINUS_6); 411 case max_minus_12: 412 return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN, LNA_GAIN_MAX_MINUS_12); 413 case max_minus_24: 414 return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN, LNA_GAIN_MAX_MINUS_24); 415 case max_minus_36: 416 return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN, LNA_GAIN_MAX_MINUS_36); 417 case max_minus_48: 418 return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN, LNA_GAIN_MAX_MINUS_48); 419 default: 420 dev_dbg(&spi->dev, "set: illegal input param"); 421 return -EINVAL; 422 } 423 } 424 425 static int rf69_set_bandwidth_intern(struct spi_device *spi, u8 reg, 426 enum mantisse mantisse, u8 exponent) 427 { 428 u8 newValue; 429 430 // check value for mantisse and exponent 431 if (exponent > 7) { 432 dev_dbg(&spi->dev, "set: illegal input param"); 433 return -EINVAL; 434 } 435 436 if ((mantisse != mantisse16) && 437 (mantisse != mantisse20) && 438 (mantisse != mantisse24)) { 439 dev_dbg(&spi->dev, "set: illegal input param"); 440 return -EINVAL; 441 } 442 443 // read old value 444 newValue = rf69_read_reg(spi, reg); 445 446 // "delete" mantisse and exponent = just keep the DCC setting 447 newValue = newValue & MASK_BW_DCC_FREQ; 448 449 // add new mantisse 450 switch (mantisse) { 451 case mantisse16: 452 newValue = newValue | BW_MANT_16; 453 break; 454 case mantisse20: 455 newValue = newValue | BW_MANT_20; 456 break; 457 case mantisse24: 458 newValue = newValue | BW_MANT_24; 459 break; 460 } 461 462 // add new exponent 463 newValue = newValue | exponent; 464 465 // write back 466 return rf69_write_reg(spi, reg, newValue); 467 } 468 469 int rf69_set_bandwidth(struct spi_device *spi, enum mantisse mantisse, u8 exponent) 470 { 471 return rf69_set_bandwidth_intern(spi, REG_RXBW, mantisse, exponent); 472 } 473 474 int rf69_set_bandwidth_during_afc(struct spi_device *spi, enum mantisse mantisse, u8 exponent) 475 { 476 return rf69_set_bandwidth_intern(spi, REG_AFCBW, mantisse, exponent); 477 } 478 479 int rf69_set_ook_threshold_dec(struct spi_device *spi, enum thresholdDecrement thresholdDecrement) 480 { 481 switch (thresholdDecrement) { 482 case dec_every8th: 483 return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, OOKPEAK_THRESHDEC_EVERY_8TH); 484 case dec_every4th: 485 return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, OOKPEAK_THRESHDEC_EVERY_4TH); 486 case dec_every2nd: 487 return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, OOKPEAK_THRESHDEC_EVERY_2ND); 488 case dec_once: 489 return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, OOKPEAK_THRESHDEC_ONCE); 490 case dec_twice: 491 return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, OOKPEAK_THRESHDEC_TWICE); 492 case dec_4times: 493 return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, OOKPEAK_THRESHDEC_4_TIMES); 494 case dec_8times: 495 return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, OOKPEAK_THRESHDEC_8_TIMES); 496 case dec_16times: 497 return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, OOKPEAK_THRESHDEC_16_TIMES); 498 default: 499 dev_dbg(&spi->dev, "set: illegal input param"); 500 return -EINVAL; 501 } 502 } 503 504 int rf69_set_dio_mapping(struct spi_device *spi, u8 DIONumber, u8 value) 505 { 506 u8 mask; 507 u8 shift; 508 u8 regaddr; 509 u8 regValue; 510 511 switch (DIONumber) { 512 case 0: 513 mask = MASK_DIO0; shift = SHIFT_DIO0; regaddr = REG_DIOMAPPING1; 514 break; 515 case 1: 516 mask = MASK_DIO1; shift = SHIFT_DIO1; regaddr = REG_DIOMAPPING1; 517 break; 518 case 2: 519 mask = MASK_DIO2; shift = SHIFT_DIO2; regaddr = REG_DIOMAPPING1; 520 break; 521 case 3: 522 mask = MASK_DIO3; shift = SHIFT_DIO3; regaddr = REG_DIOMAPPING1; 523 break; 524 case 4: 525 mask = MASK_DIO4; shift = SHIFT_DIO4; regaddr = REG_DIOMAPPING2; 526 break; 527 case 5: 528 mask = MASK_DIO5; shift = SHIFT_DIO5; regaddr = REG_DIOMAPPING2; 529 break; 530 default: 531 dev_dbg(&spi->dev, "set: illegal input param"); 532 return -EINVAL; 533 } 534 535 // read reg 536 regValue = rf69_read_reg(spi, regaddr); 537 // delete old value 538 regValue = regValue & ~mask; 539 // add new value 540 regValue = regValue | value << shift; 541 // write back 542 return rf69_write_reg(spi, regaddr, regValue); 543 } 544 545 bool rf69_get_flag(struct spi_device *spi, enum flag flag) 546 { 547 switch (flag) { 548 case modeSwitchCompleted: 549 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_MODE_READY); 550 case readyToReceive: 551 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_RX_READY); 552 case readyToSend: 553 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_TX_READY); 554 case pllLocked: 555 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_PLL_LOCK); 556 case rssiExceededThreshold: 557 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_RSSI); 558 case timeout: 559 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_TIMEOUT); 560 case automode: 561 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_AUTOMODE); 562 case syncAddressMatch: 563 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH); 564 case fifo_full: 565 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_FULL); 566 /* case fifo_not_empty: 567 * return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_NOT_EMPTY); */ 568 case fifo_empty: 569 return !(rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_NOT_EMPTY); 570 case fifo_level_below_threshold: 571 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_LEVEL); 572 case fifo_overrun: 573 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_OVERRUN); 574 case packetSent: 575 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_PACKET_SENT); 576 case payload_ready: 577 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_PAYLOAD_READY); 578 case crcOk: 579 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_CRC_OK); 580 case batteryLow: 581 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_LOW_BAT); 582 default: return false; 583 } 584 } 585 586 int rf69_set_rssi_threshold(struct spi_device *spi, u8 threshold) 587 { 588 /* no value check needed - u8 exactly matches register size */ 589 590 return rf69_write_reg(spi, REG_RSSITHRESH, threshold); 591 } 592 593 int rf69_set_preamble_length(struct spi_device *spi, u16 preambleLength) 594 { 595 int retval; 596 u8 msb, lsb; 597 598 /* no value check needed - u16 exactly matches register size */ 599 600 /* calculate reg settings */ 601 msb = (preambleLength & 0xff00) >> 8; 602 lsb = (preambleLength & 0xff); 603 604 /* transmit to chip */ 605 retval = rf69_write_reg(spi, REG_PREAMBLE_MSB, msb); 606 if (retval) 607 return retval; 608 retval = rf69_write_reg(spi, REG_PREAMBLE_LSB, lsb); 609 610 return retval; 611 } 612 613 int rf69_enable_sync(struct spi_device *spi) 614 { 615 return rf69_set_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON); 616 } 617 618 int rf69_disable_sync(struct spi_device *spi) 619 { 620 return rf69_clear_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON); 621 } 622 623 int rf69_set_fifo_fill_condition(struct spi_device *spi, enum fifo_fill_condition fifo_fill_condition) 624 { 625 switch (fifo_fill_condition) { 626 case always: 627 return rf69_set_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_FIFO_FILL_CONDITION); 628 case afterSyncInterrupt: 629 return rf69_clear_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_FIFO_FILL_CONDITION); 630 default: 631 dev_dbg(&spi->dev, "set: illegal input param"); 632 return -EINVAL; 633 } 634 } 635 636 int rf69_set_sync_size(struct spi_device *spi, u8 syncSize) 637 { 638 // check input value 639 if (syncSize > 0x07) { 640 dev_dbg(&spi->dev, "set: illegal input param"); 641 return -EINVAL; 642 } 643 644 // write value 645 return rf69_read_mod_write(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_SIZE, (syncSize << 3)); 646 } 647 648 int rf69_set_sync_values(struct spi_device *spi, u8 syncValues[8]) 649 { 650 int retval = 0; 651 652 retval += rf69_write_reg(spi, REG_SYNCVALUE1, syncValues[0]); 653 retval += rf69_write_reg(spi, REG_SYNCVALUE2, syncValues[1]); 654 retval += rf69_write_reg(spi, REG_SYNCVALUE3, syncValues[2]); 655 retval += rf69_write_reg(spi, REG_SYNCVALUE4, syncValues[3]); 656 retval += rf69_write_reg(spi, REG_SYNCVALUE5, syncValues[4]); 657 retval += rf69_write_reg(spi, REG_SYNCVALUE6, syncValues[5]); 658 retval += rf69_write_reg(spi, REG_SYNCVALUE7, syncValues[6]); 659 retval += rf69_write_reg(spi, REG_SYNCVALUE8, syncValues[7]); 660 661 return retval; 662 } 663 664 int rf69_set_packet_format(struct spi_device *spi, enum packetFormat packetFormat) 665 { 666 switch (packetFormat) { 667 case packetLengthVar: 668 return rf69_set_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE); 669 case packetLengthFix: 670 return rf69_clear_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE); 671 default: 672 dev_dbg(&spi->dev, "set: illegal input param"); 673 return -EINVAL; 674 } 675 } 676 677 int rf69_enable_crc(struct spi_device *spi) 678 { 679 return rf69_set_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON); 680 } 681 682 int rf69_disable_crc(struct spi_device *spi) 683 { 684 return rf69_clear_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON); 685 } 686 687 int rf69_set_adressFiltering(struct spi_device *spi, enum addressFiltering addressFiltering) 688 { 689 switch (addressFiltering) { 690 case filteringOff: 691 return rf69_read_mod_write(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_ADDRESSFILTERING, PACKETCONFIG1_ADDRESSFILTERING_OFF); 692 case nodeAddress: 693 return rf69_read_mod_write(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_ADDRESSFILTERING, PACKETCONFIG1_ADDRESSFILTERING_NODE); 694 case nodeOrBroadcastAddress: 695 return rf69_read_mod_write(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_ADDRESSFILTERING, PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST); 696 default: 697 dev_dbg(&spi->dev, "set: illegal input param"); 698 return -EINVAL; 699 } 700 } 701 702 int rf69_set_payload_length(struct spi_device *spi, u8 payload_length) 703 { 704 return rf69_write_reg(spi, REG_PAYLOAD_LENGTH, payload_length); 705 } 706 707 int rf69_set_node_address(struct spi_device *spi, u8 nodeAddress) 708 { 709 return rf69_write_reg(spi, REG_NODEADRS, nodeAddress); 710 } 711 712 int rf69_set_broadcast_address(struct spi_device *spi, u8 broadcastAddress) 713 { 714 return rf69_write_reg(spi, REG_BROADCASTADRS, broadcastAddress); 715 } 716 717 int rf69_set_tx_start_condition(struct spi_device *spi, enum txStartCondition txStartCondition) 718 { 719 switch (txStartCondition) { 720 case fifo_level: 721 return rf69_clear_bit(spi, REG_FIFO_THRESH, MASK_FIFO_THRESH_TXSTART); 722 case fifo_not_empty: 723 return rf69_set_bit(spi, REG_FIFO_THRESH, MASK_FIFO_THRESH_TXSTART); 724 default: 725 dev_dbg(&spi->dev, "set: illegal input param"); 726 return -EINVAL; 727 } 728 } 729 730 int rf69_set_fifo_threshold(struct spi_device *spi, u8 threshold) 731 { 732 int retval; 733 734 /* check input value */ 735 if (threshold & 0x80) { 736 dev_dbg(&spi->dev, "set: illegal input param"); 737 return -EINVAL; 738 } 739 740 /* write value */ 741 retval = rf69_read_mod_write(spi, REG_FIFO_THRESH, MASK_FIFO_THRESH_VALUE, threshold); 742 if (retval) 743 return retval; 744 745 /* access the fifo to activate new threshold 746 * retval (mis-) used as buffer here 747 */ 748 return rf69_read_fifo(spi, (u8 *)&retval, 1); 749 } 750 751 int rf69_set_dagc(struct spi_device *spi, enum dagc dagc) 752 { 753 switch (dagc) { 754 case normalMode: 755 return rf69_write_reg(spi, REG_TESTDAGC, DAGC_NORMAL); 756 case improve: 757 return rf69_write_reg(spi, REG_TESTDAGC, DAGC_IMPROVED_LOWBETA0); 758 case improve4LowModulationIndex: 759 return rf69_write_reg(spi, REG_TESTDAGC, DAGC_IMPROVED_LOWBETA1); 760 default: 761 dev_dbg(&spi->dev, "set: illegal input param"); 762 return -EINVAL; 763 } 764 } 765 766 /*-------------------------------------------------------------------------*/ 767 768 int rf69_read_fifo(struct spi_device *spi, u8 *buffer, unsigned int size) 769 { 770 #ifdef DEBUG_FIFO_ACCESS 771 int i; 772 #endif 773 struct spi_transfer transfer; 774 u8 local_buffer[FIFO_SIZE + 1]; 775 int retval; 776 777 if (size > FIFO_SIZE) { 778 dev_dbg(&spi->dev, "read fifo: passed in buffer bigger then internal buffer\n"); 779 return -EMSGSIZE; 780 } 781 782 /* prepare a bidirectional transfer */ 783 local_buffer[0] = REG_FIFO; 784 memset(&transfer, 0, sizeof(transfer)); 785 transfer.tx_buf = local_buffer; 786 transfer.rx_buf = local_buffer; 787 transfer.len = size + 1; 788 789 retval = spi_sync_transfer(spi, &transfer, 1); 790 791 #ifdef DEBUG_FIFO_ACCESS 792 for (i = 0; i < size; i++) 793 dev_dbg(&spi->dev, "%d - 0x%x\n", i, local_buffer[i + 1]); 794 #endif 795 796 memcpy(buffer, &local_buffer[1], size); 797 798 return retval; 799 } 800 801 int rf69_write_fifo(struct spi_device *spi, u8 *buffer, unsigned int size) 802 { 803 #ifdef DEBUG_FIFO_ACCESS 804 int i; 805 #endif 806 char spi_address = REG_FIFO | WRITE_BIT; 807 u8 local_buffer[FIFO_SIZE + 1]; 808 809 if (size > FIFO_SIZE) { 810 dev_dbg(&spi->dev, "read fifo: passed in buffer bigger then internal buffer\n"); 811 return -EMSGSIZE; 812 } 813 814 local_buffer[0] = spi_address; 815 memcpy(&local_buffer[1], buffer, size); 816 817 #ifdef DEBUG_FIFO_ACCESS 818 for (i = 0; i < size; i++) 819 dev_dbg(&spi->dev, "0x%x\n", buffer[i]); 820 #endif 821 822 return spi_write(spi, local_buffer, size + 1); 823 } 824 825