1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * abstraction of the spi interface of HopeRf rf69 radio module 4 * 5 * Copyright (C) 2016 Wolf-Entwicklungen 6 * Marcus Wolf <linux@wolf-entwicklungen.de> 7 */ 8 9 /* enable prosa debug info */ 10 #undef DEBUG 11 /* enable print of values on reg access */ 12 #undef DEBUG_VALUES 13 /* enable print of values on fifo access */ 14 #undef DEBUG_FIFO_ACCESS 15 16 #include <linux/types.h> 17 #include <linux/spi/spi.h> 18 19 #include "rf69.h" 20 #include "rf69_registers.h" 21 22 #define F_OSC 32000000 /* in Hz */ 23 #define FIFO_SIZE 66 /* in byte */ 24 25 /*-------------------------------------------------------------------------*/ 26 27 static u8 rf69_read_reg(struct spi_device *spi, u8 addr) 28 { 29 int retval; 30 31 retval = spi_w8r8(spi, addr); 32 33 #ifdef DEBUG_VALUES 34 if (retval < 0) 35 /* 36 * should never happen, since we already checked, 37 * that module is connected. Therefore no error 38 * handling, just an optional error message... 39 */ 40 dev_dbg(&spi->dev, "read 0x%x FAILED\n", addr); 41 else 42 dev_dbg(&spi->dev, "read 0x%x from reg 0x%x\n", retval, addr); 43 #endif 44 45 return retval; 46 } 47 48 static int rf69_write_reg(struct spi_device *spi, u8 addr, u8 value) 49 { 50 int retval; 51 char buffer[2]; 52 53 buffer[0] = addr | WRITE_BIT; 54 buffer[1] = value; 55 56 retval = spi_write(spi, &buffer, 2); 57 58 #ifdef DEBUG_VALUES 59 if (retval < 0) 60 /* 61 * should never happen, since we already checked, 62 * that module is connected. Therefore no error 63 * handling, just an optional error message... 64 */ 65 dev_dbg(&spi->dev, "write 0x%x to 0x%x FAILED\n", value, addr); 66 else 67 dev_dbg(&spi->dev, "wrote 0x%x to reg 0x%x\n", value, addr); 68 #endif 69 70 return retval; 71 } 72 73 /*-------------------------------------------------------------------------*/ 74 75 static int rf69_set_bit(struct spi_device *spi, u8 reg, u8 mask) 76 { 77 u8 tmp; 78 79 tmp = rf69_read_reg(spi, reg); 80 tmp = tmp | mask; 81 return rf69_write_reg(spi, reg, tmp); 82 } 83 84 static int rf69_clear_bit(struct spi_device *spi, u8 reg, u8 mask) 85 { 86 u8 tmp; 87 88 tmp = rf69_read_reg(spi, reg); 89 tmp = tmp & ~mask; 90 return rf69_write_reg(spi, reg, tmp); 91 } 92 93 static inline int rf69_read_mod_write(struct spi_device *spi, u8 reg, 94 u8 mask, u8 value) 95 { 96 u8 tmp; 97 98 tmp = rf69_read_reg(spi, reg); 99 tmp = (tmp & ~mask) | value; 100 return rf69_write_reg(spi, reg, tmp); 101 } 102 103 /*-------------------------------------------------------------------------*/ 104 105 int rf69_set_mode(struct spi_device *spi, enum mode mode) 106 { 107 static const u8 mode_map[] = { 108 [transmit] = OPMODE_MODE_TRANSMIT, 109 [receive] = OPMODE_MODE_RECEIVE, 110 [synthesizer] = OPMODE_MODE_SYNTHESIZER, 111 [standby] = OPMODE_MODE_STANDBY, 112 [mode_sleep] = OPMODE_MODE_SLEEP, 113 }; 114 115 if (unlikely(mode >= ARRAY_SIZE(mode_map))) { 116 dev_dbg(&spi->dev, "set: illegal mode %u", mode); 117 return -EINVAL; 118 } 119 120 return rf69_read_mod_write(spi, REG_OPMODE, MASK_OPMODE_MODE, 121 mode_map[mode]); 122 123 /* 124 * we are using packet mode, so this check is not really needed 125 * but waiting for mode ready is necessary when going from sleep 126 * because the FIFO may not be immediately available from previous mode 127 * while (_mode == RF69_MODE_SLEEP && (READ_REG(REG_IRQFLAGS1) & 128 RF_IRQFLAGS1_MODEREADY) == 0x00); // Wait for ModeReady 129 */ 130 } 131 132 int rf69_set_data_mode(struct spi_device *spi, u8 data_mode) 133 { 134 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODE, 135 data_mode); 136 } 137 138 int rf69_set_modulation(struct spi_device *spi, enum modulation modulation) 139 { 140 static const u8 modulation_map[] = { 141 [OOK] = DATAMODUL_MODULATION_TYPE_OOK, 142 [FSK] = DATAMODUL_MODULATION_TYPE_FSK, 143 }; 144 145 if (unlikely(modulation >= ARRAY_SIZE(modulation_map))) { 146 dev_dbg(&spi->dev, "set: illegal modulation %u", modulation); 147 return -EINVAL; 148 } 149 150 return rf69_read_mod_write(spi, REG_DATAMODUL, 151 MASK_DATAMODUL_MODULATION_TYPE, 152 modulation_map[modulation]); 153 } 154 155 static enum modulation rf69_get_modulation(struct spi_device *spi) 156 { 157 u8 modulation_reg; 158 159 modulation_reg = rf69_read_reg(spi, REG_DATAMODUL); 160 161 switch (modulation_reg & MASK_DATAMODUL_MODULATION_TYPE) { 162 case DATAMODUL_MODULATION_TYPE_OOK: 163 return OOK; 164 case DATAMODUL_MODULATION_TYPE_FSK: 165 return FSK; 166 default: 167 return UNDEF; 168 } 169 } 170 171 int rf69_set_modulation_shaping(struct spi_device *spi, 172 enum mod_shaping mod_shaping) 173 { 174 switch (rf69_get_modulation(spi)) { 175 case FSK: 176 switch (mod_shaping) { 177 case SHAPING_OFF: 178 return rf69_read_mod_write(spi, REG_DATAMODUL, 179 MASK_DATAMODUL_MODULATION_SHAPE, 180 DATAMODUL_MODULATION_SHAPE_NONE); 181 case SHAPING_1_0: 182 return rf69_read_mod_write(spi, REG_DATAMODUL, 183 MASK_DATAMODUL_MODULATION_SHAPE, 184 DATAMODUL_MODULATION_SHAPE_1_0); 185 case SHAPING_0_5: 186 return rf69_read_mod_write(spi, REG_DATAMODUL, 187 MASK_DATAMODUL_MODULATION_SHAPE, 188 DATAMODUL_MODULATION_SHAPE_0_5); 189 case SHAPING_0_3: 190 return rf69_read_mod_write(spi, REG_DATAMODUL, 191 MASK_DATAMODUL_MODULATION_SHAPE, 192 DATAMODUL_MODULATION_SHAPE_0_3); 193 default: 194 dev_dbg(&spi->dev, "set: illegal mod shaping for FSK %u", mod_shaping); 195 return -EINVAL; 196 } 197 case OOK: 198 switch (mod_shaping) { 199 case SHAPING_OFF: 200 return rf69_read_mod_write(spi, REG_DATAMODUL, 201 MASK_DATAMODUL_MODULATION_SHAPE, 202 DATAMODUL_MODULATION_SHAPE_NONE); 203 case SHAPING_BR: 204 return rf69_read_mod_write(spi, REG_DATAMODUL, 205 MASK_DATAMODUL_MODULATION_SHAPE, 206 DATAMODUL_MODULATION_SHAPE_BR); 207 case SHAPING_2BR: 208 return rf69_read_mod_write(spi, REG_DATAMODUL, 209 MASK_DATAMODUL_MODULATION_SHAPE, 210 DATAMODUL_MODULATION_SHAPE_2BR); 211 default: 212 dev_dbg(&spi->dev, "set: illegal mod shaping for OOK %u", mod_shaping); 213 return -EINVAL; 214 } 215 default: 216 dev_dbg(&spi->dev, "set: modulation undefined"); 217 return -EINVAL; 218 } 219 } 220 221 int rf69_set_bit_rate(struct spi_device *spi, u16 bit_rate) 222 { 223 int retval; 224 u32 bit_rate_min; 225 u32 bit_rate_reg; 226 u8 msb; 227 u8 lsb; 228 229 // check input value 230 bit_rate_min = F_OSC / 8388608; // 8388608 = 2^23; 231 if (bit_rate < bit_rate_min) { 232 dev_dbg(&spi->dev, "setBitRate: illegal input param"); 233 return -EINVAL; 234 } 235 236 // calculate reg settings 237 bit_rate_reg = (F_OSC / bit_rate); 238 239 msb = (bit_rate_reg & 0xff00) >> 8; 240 lsb = (bit_rate_reg & 0xff); 241 242 // transmit to RF 69 243 retval = rf69_write_reg(spi, REG_BITRATE_MSB, msb); 244 if (retval) 245 return retval; 246 retval = rf69_write_reg(spi, REG_BITRATE_LSB, lsb); 247 if (retval) 248 return retval; 249 250 return 0; 251 } 252 253 int rf69_set_deviation(struct spi_device *spi, u32 deviation) 254 { 255 int retval; 256 u64 f_reg; 257 u64 f_step; 258 u32 bit_rate_reg; 259 u32 bit_rate; 260 u8 msb; 261 u8 lsb; 262 u64 factor = 1000000; // to improve precision of calculation 263 264 // calculate bit rate 265 bit_rate_reg = rf69_read_reg(spi, REG_BITRATE_MSB) << 8; 266 bit_rate_reg |= rf69_read_reg(spi, REG_BITRATE_LSB); 267 bit_rate = F_OSC / bit_rate_reg; 268 269 /* 270 * frequency deviation must exceed 600 Hz but not exceed 271 * 500kHz when taking bitrate dependency into consideration 272 * to ensure proper modulation 273 */ 274 if (deviation < 600 || (deviation + (bit_rate / 2)) > 500000) { 275 dev_dbg(&spi->dev, 276 "set_deviation: illegal input param: %u", deviation); 277 return -EINVAL; 278 } 279 280 // calculat f step 281 f_step = F_OSC * factor; 282 do_div(f_step, 524288); // 524288 = 2^19 283 284 // calculate register settings 285 f_reg = deviation * factor; 286 do_div(f_reg, f_step); 287 288 msb = (f_reg & 0xff00) >> 8; 289 lsb = (f_reg & 0xff); 290 291 // check msb 292 if (msb & ~FDEVMASB_MASK) { 293 dev_dbg(&spi->dev, "set_deviation: err in calc of msb"); 294 return -EINVAL; 295 } 296 297 // write to chip 298 retval = rf69_write_reg(spi, REG_FDEV_MSB, msb); 299 if (retval) 300 return retval; 301 retval = rf69_write_reg(spi, REG_FDEV_LSB, lsb); 302 if (retval) 303 return retval; 304 305 return 0; 306 } 307 308 int rf69_set_frequency(struct spi_device *spi, u32 frequency) 309 { 310 int retval; 311 u32 f_max; 312 u64 f_reg; 313 u64 f_step; 314 u8 msb; 315 u8 mid; 316 u8 lsb; 317 u64 factor = 1000000; // to improve precision of calculation 318 319 // calculat f step 320 f_step = F_OSC * factor; 321 do_div(f_step, 524288); // 524288 = 2^19 322 323 // check input value 324 f_max = div_u64(f_step * 8388608, factor); 325 if (frequency > f_max) { 326 dev_dbg(&spi->dev, "setFrequency: illegal input param"); 327 return -EINVAL; 328 } 329 330 // calculate reg settings 331 f_reg = frequency * factor; 332 do_div(f_reg, f_step); 333 334 msb = (f_reg & 0xff0000) >> 16; 335 mid = (f_reg & 0xff00) >> 8; 336 lsb = (f_reg & 0xff); 337 338 // write to chip 339 retval = rf69_write_reg(spi, REG_FRF_MSB, msb); 340 if (retval) 341 return retval; 342 retval = rf69_write_reg(spi, REG_FRF_MID, mid); 343 if (retval) 344 return retval; 345 retval = rf69_write_reg(spi, REG_FRF_LSB, lsb); 346 if (retval) 347 return retval; 348 349 return 0; 350 } 351 352 int rf69_enable_amplifier(struct spi_device *spi, u8 amplifier_mask) 353 { 354 return rf69_set_bit(spi, REG_PALEVEL, amplifier_mask); 355 } 356 357 int rf69_disable_amplifier(struct spi_device *spi, u8 amplifier_mask) 358 { 359 return rf69_clear_bit(spi, REG_PALEVEL, amplifier_mask); 360 } 361 362 int rf69_set_output_power_level(struct spi_device *spi, u8 power_level) 363 { 364 u8 pa_level, ocp, test_pa1, test_pa2; 365 bool pa0, pa1, pa2, high_power; 366 u8 min_power_level; 367 368 // check register pa_level 369 pa_level = rf69_read_reg(spi, REG_PALEVEL); 370 pa0 = pa_level & MASK_PALEVEL_PA0; 371 pa1 = pa_level & MASK_PALEVEL_PA1; 372 pa2 = pa_level & MASK_PALEVEL_PA2; 373 374 // check high power mode 375 ocp = rf69_read_reg(spi, REG_OCP); 376 test_pa1 = rf69_read_reg(spi, REG_TESTPA1); 377 test_pa2 = rf69_read_reg(spi, REG_TESTPA2); 378 high_power = (ocp == 0x0f) && (test_pa1 == 0x5d) && (test_pa2 == 0x7c); 379 380 if (pa0 && !pa1 && !pa2) { 381 power_level += 18; 382 min_power_level = 0; 383 } else if (!pa0 && pa1 && !pa2) { 384 power_level += 18; 385 min_power_level = 16; 386 } else if (!pa0 && pa1 && pa2) { 387 if (high_power) 388 power_level += 11; 389 else 390 power_level += 14; 391 min_power_level = 16; 392 } else { 393 goto failed; 394 } 395 396 // check input value 397 if (power_level > 0x1f) 398 goto failed; 399 400 if (power_level < min_power_level) 401 goto failed; 402 403 // write value 404 return rf69_read_mod_write(spi, REG_PALEVEL, MASK_PALEVEL_OUTPUT_POWER, 405 power_level); 406 failed: 407 dev_dbg(&spi->dev, "set: illegal power level %u", power_level); 408 return -EINVAL; 409 } 410 411 int rf69_set_pa_ramp(struct spi_device *spi, enum pa_ramp pa_ramp) 412 { 413 static const u8 pa_ramp_map[] = { 414 [ramp3400] = PARAMP_3400, 415 [ramp2000] = PARAMP_2000, 416 [ramp1000] = PARAMP_1000, 417 [ramp500] = PARAMP_500, 418 [ramp250] = PARAMP_250, 419 [ramp125] = PARAMP_125, 420 [ramp100] = PARAMP_100, 421 [ramp62] = PARAMP_62, 422 [ramp50] = PARAMP_50, 423 [ramp40] = PARAMP_40, 424 [ramp31] = PARAMP_31, 425 [ramp25] = PARAMP_25, 426 [ramp20] = PARAMP_20, 427 [ramp15] = PARAMP_15, 428 [ramp10] = PARAMP_10, 429 }; 430 431 if (unlikely(pa_ramp >= ARRAY_SIZE(pa_ramp_map))) { 432 dev_dbg(&spi->dev, "set: illegal pa_ramp %u", pa_ramp); 433 return -EINVAL; 434 } 435 436 return rf69_write_reg(spi, REG_PARAMP, pa_ramp_map[pa_ramp]); 437 } 438 439 int rf69_set_antenna_impedance(struct spi_device *spi, 440 enum antenna_impedance antenna_impedance) 441 { 442 switch (antenna_impedance) { 443 case fifty_ohm: 444 return rf69_clear_bit(spi, REG_LNA, MASK_LNA_ZIN); 445 case two_hundred_ohm: 446 return rf69_set_bit(spi, REG_LNA, MASK_LNA_ZIN); 447 default: 448 dev_dbg(&spi->dev, "set: illegal antenna impedance %u", antenna_impedance); 449 return -EINVAL; 450 } 451 } 452 453 int rf69_set_lna_gain(struct spi_device *spi, enum lna_gain lna_gain) 454 { 455 static const u8 lna_gain_map[] = { 456 [automatic] = LNA_GAIN_AUTO, 457 [max] = LNA_GAIN_MAX, 458 [max_minus_6] = LNA_GAIN_MAX_MINUS_6, 459 [max_minus_12] = LNA_GAIN_MAX_MINUS_12, 460 [max_minus_24] = LNA_GAIN_MAX_MINUS_24, 461 [max_minus_36] = LNA_GAIN_MAX_MINUS_36, 462 [max_minus_48] = LNA_GAIN_MAX_MINUS_48, 463 }; 464 465 if (unlikely(lna_gain >= ARRAY_SIZE(lna_gain_map))) { 466 dev_dbg(&spi->dev, "set: illegal lna gain %u", lna_gain); 467 return -EINVAL; 468 } 469 470 return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN, 471 lna_gain_map[lna_gain]); 472 } 473 474 static int rf69_set_bandwidth_intern(struct spi_device *spi, u8 reg, 475 enum mantisse mantisse, u8 exponent) 476 { 477 u8 bandwidth; 478 479 // check value for mantisse and exponent 480 if (exponent > 7) { 481 dev_dbg(&spi->dev, "set: illegal bandwidth exponent %u", exponent); 482 return -EINVAL; 483 } 484 485 if (mantisse != mantisse16 && 486 mantisse != mantisse20 && 487 mantisse != mantisse24) { 488 dev_dbg(&spi->dev, "set: illegal bandwidth mantisse %u", mantisse); 489 return -EINVAL; 490 } 491 492 // read old value 493 bandwidth = rf69_read_reg(spi, reg); 494 495 // "delete" mantisse and exponent = just keep the DCC setting 496 bandwidth = bandwidth & MASK_BW_DCC_FREQ; 497 498 // add new mantisse 499 switch (mantisse) { 500 case mantisse16: 501 bandwidth = bandwidth | BW_MANT_16; 502 break; 503 case mantisse20: 504 bandwidth = bandwidth | BW_MANT_20; 505 break; 506 case mantisse24: 507 bandwidth = bandwidth | BW_MANT_24; 508 break; 509 } 510 511 // add new exponent 512 bandwidth = bandwidth | exponent; 513 514 // write back 515 return rf69_write_reg(spi, reg, bandwidth); 516 } 517 518 int rf69_set_bandwidth(struct spi_device *spi, enum mantisse mantisse, 519 u8 exponent) 520 { 521 return rf69_set_bandwidth_intern(spi, REG_RXBW, mantisse, exponent); 522 } 523 524 int rf69_set_bandwidth_during_afc(struct spi_device *spi, 525 enum mantisse mantisse, 526 u8 exponent) 527 { 528 return rf69_set_bandwidth_intern(spi, REG_AFCBW, mantisse, exponent); 529 } 530 531 int rf69_set_ook_threshold_dec(struct spi_device *spi, 532 enum threshold_decrement threshold_decrement) 533 { 534 static const u8 td_map[] = { 535 [dec_every8th] = OOKPEAK_THRESHDEC_EVERY_8TH, 536 [dec_every4th] = OOKPEAK_THRESHDEC_EVERY_4TH, 537 [dec_every2nd] = OOKPEAK_THRESHDEC_EVERY_2ND, 538 [dec_once] = OOKPEAK_THRESHDEC_ONCE, 539 [dec_twice] = OOKPEAK_THRESHDEC_TWICE, 540 [dec_4times] = OOKPEAK_THRESHDEC_4_TIMES, 541 [dec_8times] = OOKPEAK_THRESHDEC_8_TIMES, 542 [dec_16times] = OOKPEAK_THRESHDEC_16_TIMES, 543 }; 544 545 if (unlikely(threshold_decrement >= ARRAY_SIZE(td_map))) { 546 dev_dbg(&spi->dev, "set: illegal OOK threshold decrement %u", threshold_decrement); 547 return -EINVAL; 548 } 549 550 return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, 551 td_map[threshold_decrement]); 552 } 553 554 int rf69_set_dio_mapping(struct spi_device *spi, u8 dio_number, u8 value) 555 { 556 u8 mask; 557 u8 shift; 558 u8 dio_addr; 559 u8 dio_value; 560 561 switch (dio_number) { 562 case 0: 563 mask = MASK_DIO0; 564 shift = SHIFT_DIO0; 565 dio_addr = REG_DIOMAPPING1; 566 break; 567 case 1: 568 mask = MASK_DIO1; 569 shift = SHIFT_DIO1; 570 dio_addr = REG_DIOMAPPING1; 571 break; 572 case 2: 573 mask = MASK_DIO2; 574 shift = SHIFT_DIO2; 575 dio_addr = REG_DIOMAPPING1; 576 break; 577 case 3: 578 mask = MASK_DIO3; 579 shift = SHIFT_DIO3; 580 dio_addr = REG_DIOMAPPING1; 581 break; 582 case 4: 583 mask = MASK_DIO4; 584 shift = SHIFT_DIO4; 585 dio_addr = REG_DIOMAPPING2; 586 break; 587 case 5: 588 mask = MASK_DIO5; 589 shift = SHIFT_DIO5; 590 dio_addr = REG_DIOMAPPING2; 591 break; 592 default: 593 dev_dbg(&spi->dev, "set: illegal dio number %u", dio_number); 594 return -EINVAL; 595 } 596 597 // read reg 598 dio_value = rf69_read_reg(spi, dio_addr); 599 // delete old value 600 dio_value = dio_value & ~mask; 601 // add new value 602 dio_value = dio_value | value << shift; 603 // write back 604 return rf69_write_reg(spi, dio_addr, dio_value); 605 } 606 607 bool rf69_get_flag(struct spi_device *spi, enum flag flag) 608 { 609 switch (flag) { 610 case mode_switch_completed: 611 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_MODE_READY); 612 case ready_to_receive: 613 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_RX_READY); 614 case ready_to_send: 615 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_TX_READY); 616 case pll_locked: 617 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_PLL_LOCK); 618 case rssi_exceeded_threshold: 619 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_RSSI); 620 case timeout: 621 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_TIMEOUT); 622 case automode: 623 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_AUTOMODE); 624 case sync_address_match: 625 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH); 626 case fifo_full: 627 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_FULL); 628 /* 629 * case fifo_not_empty: 630 * return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_NOT_EMPTY); 631 */ 632 case fifo_empty: 633 return !(rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_NOT_EMPTY); 634 case fifo_level_below_threshold: 635 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_LEVEL); 636 case fifo_overrun: 637 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_OVERRUN); 638 case packet_sent: 639 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_PACKET_SENT); 640 case payload_ready: 641 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_PAYLOAD_READY); 642 case crc_ok: 643 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_CRC_OK); 644 case battery_low: 645 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_LOW_BAT); 646 default: return false; 647 } 648 } 649 650 int rf69_set_rssi_threshold(struct spi_device *spi, u8 threshold) 651 { 652 /* no value check needed - u8 exactly matches register size */ 653 654 return rf69_write_reg(spi, REG_RSSITHRESH, threshold); 655 } 656 657 int rf69_set_preamble_length(struct spi_device *spi, u16 preamble_length) 658 { 659 int retval; 660 u8 msb, lsb; 661 662 /* no value check needed - u16 exactly matches register size */ 663 664 /* calculate reg settings */ 665 msb = (preamble_length & 0xff00) >> 8; 666 lsb = (preamble_length & 0xff); 667 668 /* transmit to chip */ 669 retval = rf69_write_reg(spi, REG_PREAMBLE_MSB, msb); 670 if (retval) 671 return retval; 672 return rf69_write_reg(spi, REG_PREAMBLE_LSB, lsb); 673 } 674 675 int rf69_enable_sync(struct spi_device *spi) 676 { 677 return rf69_set_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON); 678 } 679 680 int rf69_disable_sync(struct spi_device *spi) 681 { 682 return rf69_clear_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON); 683 } 684 685 int rf69_set_fifo_fill_condition(struct spi_device *spi, 686 enum fifo_fill_condition fifo_fill_condition) 687 { 688 switch (fifo_fill_condition) { 689 case always: 690 return rf69_set_bit(spi, REG_SYNC_CONFIG, 691 MASK_SYNC_CONFIG_FIFO_FILL_CONDITION); 692 case after_sync_interrupt: 693 return rf69_clear_bit(spi, REG_SYNC_CONFIG, 694 MASK_SYNC_CONFIG_FIFO_FILL_CONDITION); 695 default: 696 dev_dbg(&spi->dev, "set: illegal fifo fill condition %u", fifo_fill_condition); 697 return -EINVAL; 698 } 699 } 700 701 int rf69_set_sync_size(struct spi_device *spi, u8 sync_size) 702 { 703 // check input value 704 if (sync_size > 0x07) { 705 dev_dbg(&spi->dev, "set: illegal sync size %u", sync_size); 706 return -EINVAL; 707 } 708 709 // write value 710 return rf69_read_mod_write(spi, REG_SYNC_CONFIG, 711 MASK_SYNC_CONFIG_SYNC_SIZE, 712 (sync_size << 3)); 713 } 714 715 int rf69_set_sync_values(struct spi_device *spi, u8 sync_values[8]) 716 { 717 int retval = 0; 718 719 retval += rf69_write_reg(spi, REG_SYNCVALUE1, sync_values[0]); 720 retval += rf69_write_reg(spi, REG_SYNCVALUE2, sync_values[1]); 721 retval += rf69_write_reg(spi, REG_SYNCVALUE3, sync_values[2]); 722 retval += rf69_write_reg(spi, REG_SYNCVALUE4, sync_values[3]); 723 retval += rf69_write_reg(spi, REG_SYNCVALUE5, sync_values[4]); 724 retval += rf69_write_reg(spi, REG_SYNCVALUE6, sync_values[5]); 725 retval += rf69_write_reg(spi, REG_SYNCVALUE7, sync_values[6]); 726 retval += rf69_write_reg(spi, REG_SYNCVALUE8, sync_values[7]); 727 728 return retval; 729 } 730 731 int rf69_set_packet_format(struct spi_device *spi, 732 enum packet_format packet_format) 733 { 734 switch (packet_format) { 735 case packet_length_var: 736 return rf69_set_bit(spi, REG_PACKETCONFIG1, 737 MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE); 738 case packet_length_fix: 739 return rf69_clear_bit(spi, REG_PACKETCONFIG1, 740 MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE); 741 default: 742 dev_dbg(&spi->dev, "set: illegal packet format %u", packet_format); 743 return -EINVAL; 744 } 745 } 746 747 int rf69_enable_crc(struct spi_device *spi) 748 { 749 return rf69_set_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON); 750 } 751 752 int rf69_disable_crc(struct spi_device *spi) 753 { 754 return rf69_clear_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON); 755 } 756 757 int rf69_set_address_filtering(struct spi_device *spi, 758 enum address_filtering address_filtering) 759 { 760 static const u8 af_map[] = { 761 [filtering_off] = PACKETCONFIG1_ADDRESSFILTERING_OFF, 762 [node_address] = PACKETCONFIG1_ADDRESSFILTERING_NODE, 763 [node_or_broadcast_address] = 764 PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST, 765 }; 766 767 if (unlikely(address_filtering >= ARRAY_SIZE(af_map))) { 768 dev_dbg(&spi->dev, "set: illegal address filtering %u", address_filtering); 769 return -EINVAL; 770 } 771 772 return rf69_read_mod_write(spi, REG_PACKETCONFIG1, 773 MASK_PACKETCONFIG1_ADDRESSFILTERING, 774 af_map[address_filtering]); 775 } 776 777 int rf69_set_payload_length(struct spi_device *spi, u8 payload_length) 778 { 779 return rf69_write_reg(spi, REG_PAYLOAD_LENGTH, payload_length); 780 } 781 782 int rf69_set_node_address(struct spi_device *spi, u8 node_address) 783 { 784 return rf69_write_reg(spi, REG_NODEADRS, node_address); 785 } 786 787 int rf69_set_broadcast_address(struct spi_device *spi, u8 broadcast_address) 788 { 789 return rf69_write_reg(spi, REG_BROADCASTADRS, broadcast_address); 790 } 791 792 int rf69_set_tx_start_condition(struct spi_device *spi, 793 enum tx_start_condition tx_start_condition) 794 { 795 switch (tx_start_condition) { 796 case fifo_level: 797 return rf69_clear_bit(spi, REG_FIFO_THRESH, 798 MASK_FIFO_THRESH_TXSTART); 799 case fifo_not_empty: 800 return rf69_set_bit(spi, REG_FIFO_THRESH, 801 MASK_FIFO_THRESH_TXSTART); 802 default: 803 dev_dbg(&spi->dev, "set: illegal tx start condition %u", tx_start_condition); 804 return -EINVAL; 805 } 806 } 807 808 int rf69_set_fifo_threshold(struct spi_device *spi, u8 threshold) 809 { 810 int retval; 811 812 /* check input value */ 813 if (threshold & 0x80) { 814 dev_dbg(&spi->dev, "set: illegal fifo threshold %u", threshold); 815 return -EINVAL; 816 } 817 818 /* write value */ 819 retval = rf69_read_mod_write(spi, REG_FIFO_THRESH, 820 MASK_FIFO_THRESH_VALUE, 821 threshold); 822 if (retval) 823 return retval; 824 825 /* 826 * access the fifo to activate new threshold 827 * retval (mis-) used as buffer here 828 */ 829 return rf69_read_fifo(spi, (u8 *)&retval, 1); 830 } 831 832 int rf69_set_dagc(struct spi_device *spi, enum dagc dagc) 833 { 834 static const u8 dagc_map[] = { 835 [normal_mode] = DAGC_NORMAL, 836 [improve] = DAGC_IMPROVED_LOWBETA0, 837 [improve_for_low_modulation_index] = DAGC_IMPROVED_LOWBETA1, 838 }; 839 840 if (unlikely(dagc >= ARRAY_SIZE(dagc_map))) { 841 dev_dbg(&spi->dev, "set: illegal dagc %u", dagc); 842 return -EINVAL; 843 } 844 845 return rf69_write_reg(spi, REG_TESTDAGC, dagc_map[dagc]); 846 } 847 848 /*-------------------------------------------------------------------------*/ 849 850 int rf69_read_fifo(struct spi_device *spi, u8 *buffer, unsigned int size) 851 { 852 #ifdef DEBUG_FIFO_ACCESS 853 int i; 854 #endif 855 struct spi_transfer transfer; 856 u8 local_buffer[FIFO_SIZE + 1]; 857 int retval; 858 859 if (size > FIFO_SIZE) { 860 dev_dbg(&spi->dev, 861 "read fifo: passed in buffer bigger then internal buffer\n"); 862 return -EMSGSIZE; 863 } 864 865 /* prepare a bidirectional transfer */ 866 local_buffer[0] = REG_FIFO; 867 memset(&transfer, 0, sizeof(transfer)); 868 transfer.tx_buf = local_buffer; 869 transfer.rx_buf = local_buffer; 870 transfer.len = size + 1; 871 872 retval = spi_sync_transfer(spi, &transfer, 1); 873 874 #ifdef DEBUG_FIFO_ACCESS 875 for (i = 0; i < size; i++) 876 dev_dbg(&spi->dev, "%d - 0x%x\n", i, local_buffer[i + 1]); 877 #endif 878 879 memcpy(buffer, &local_buffer[1], size); 880 881 return retval; 882 } 883 884 int rf69_write_fifo(struct spi_device *spi, u8 *buffer, unsigned int size) 885 { 886 #ifdef DEBUG_FIFO_ACCESS 887 int i; 888 #endif 889 u8 local_buffer[FIFO_SIZE + 1]; 890 891 if (size > FIFO_SIZE) { 892 dev_dbg(&spi->dev, 893 "read fifo: passed in buffer bigger then internal buffer\n"); 894 return -EMSGSIZE; 895 } 896 897 local_buffer[0] = REG_FIFO | WRITE_BIT; 898 memcpy(&local_buffer[1], buffer, size); 899 900 #ifdef DEBUG_FIFO_ACCESS 901 for (i = 0; i < size; i++) 902 dev_dbg(&spi->dev, "0x%x\n", buffer[i]); 903 #endif 904 905 return spi_write(spi, local_buffer, size + 1); 906 } 907 908