1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * abstraction of the spi interface of HopeRf rf69 radio module 4 * 5 * Copyright (C) 2016 Wolf-Entwicklungen 6 * Marcus Wolf <linux@wolf-entwicklungen.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 /* enable prosa debug info */ 20 #undef DEBUG 21 /* enable print of values on reg access */ 22 #undef DEBUG_VALUES 23 /* enable print of values on fifo access */ 24 #undef DEBUG_FIFO_ACCESS 25 26 #include <linux/types.h> 27 #include <linux/spi/spi.h> 28 29 #include "rf69.h" 30 #include "rf69_registers.h" 31 32 #define F_OSC 32000000 /* in Hz */ 33 #define FIFO_SIZE 66 /* in byte */ 34 35 /*-------------------------------------------------------------------------*/ 36 37 static u8 rf69_read_reg(struct spi_device *spi, u8 addr) 38 { 39 int retval; 40 41 retval = spi_w8r8(spi, addr); 42 43 #ifdef DEBUG_VALUES 44 if (retval < 0) 45 /* 46 * should never happen, since we already checked, 47 * that module is connected. Therefore no error 48 * handling, just an optional error message... 49 */ 50 dev_dbg(&spi->dev, "read 0x%x FAILED\n", addr); 51 else 52 dev_dbg(&spi->dev, "read 0x%x from reg 0x%x\n", retval, addr); 53 #endif 54 55 return retval; 56 } 57 58 static int rf69_write_reg(struct spi_device *spi, u8 addr, u8 value) 59 { 60 int retval; 61 char buffer[2]; 62 63 buffer[0] = addr | WRITE_BIT; 64 buffer[1] = value; 65 66 retval = spi_write(spi, &buffer, 2); 67 68 #ifdef DEBUG_VALUES 69 if (retval < 0) 70 /* 71 * should never happen, since we already checked, 72 * that module is connected. Therefore no error 73 * handling, just an optional error message... 74 */ 75 dev_dbg(&spi->dev, "write 0x%x to 0x%x FAILED\n", value, addr); 76 else 77 dev_dbg(&spi->dev, "wrote 0x%x to reg 0x%x\n", value, addr); 78 #endif 79 80 return retval; 81 } 82 83 /*-------------------------------------------------------------------------*/ 84 85 static int rf69_set_bit(struct spi_device *spi, u8 reg, u8 mask) 86 { 87 u8 tmp; 88 89 tmp = rf69_read_reg(spi, reg); 90 tmp = tmp | mask; 91 return rf69_write_reg(spi, reg, tmp); 92 } 93 94 static int rf69_clear_bit(struct spi_device *spi, u8 reg, u8 mask) 95 { 96 u8 tmp; 97 98 tmp = rf69_read_reg(spi, reg); 99 tmp = tmp & ~mask; 100 return rf69_write_reg(spi, reg, tmp); 101 } 102 103 static inline int rf69_read_mod_write(struct spi_device *spi, u8 reg, 104 u8 mask, u8 value) 105 { 106 u8 tmp; 107 108 tmp = rf69_read_reg(spi, reg); 109 tmp = (tmp & ~mask) | value; 110 return rf69_write_reg(spi, reg, tmp); 111 } 112 113 /*-------------------------------------------------------------------------*/ 114 115 int rf69_set_mode(struct spi_device *spi, enum mode mode) 116 { 117 static const u8 mode_map[] = { 118 [transmit] = OPMODE_MODE_TRANSMIT, 119 [receive] = OPMODE_MODE_RECEIVE, 120 [synthesizer] = OPMODE_MODE_SYNTHESIZER, 121 [standby] = OPMODE_MODE_STANDBY, 122 [mode_sleep] = OPMODE_MODE_SLEEP, 123 }; 124 125 if (unlikely(mode >= ARRAY_SIZE(mode_map))) { 126 dev_dbg(&spi->dev, "set: illegal input param"); 127 return -EINVAL; 128 } 129 130 return rf69_read_mod_write(spi, REG_OPMODE, MASK_OPMODE_MODE, 131 mode_map[mode]); 132 133 /* 134 * we are using packet mode, so this check is not really needed 135 * but waiting for mode ready is necessary when going from sleep 136 * because the FIFO may not be immediately available from previous mode 137 * while (_mode == RF69_MODE_SLEEP && (READ_REG(REG_IRQFLAGS1) & 138 RF_IRQFLAGS1_MODEREADY) == 0x00); // Wait for ModeReady 139 */ 140 } 141 142 int rf69_set_data_mode(struct spi_device *spi, u8 data_mode) 143 { 144 return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODE, 145 data_mode); 146 } 147 148 int rf69_set_modulation(struct spi_device *spi, enum modulation modulation) 149 { 150 static const u8 modulation_map[] = { 151 [OOK] = DATAMODUL_MODULATION_TYPE_OOK, 152 [FSK] = DATAMODUL_MODULATION_TYPE_FSK, 153 }; 154 155 if (unlikely(modulation >= ARRAY_SIZE(modulation_map))) { 156 dev_dbg(&spi->dev, "set: illegal input param"); 157 return -EINVAL; 158 } 159 160 return rf69_read_mod_write(spi, REG_DATAMODUL, 161 MASK_DATAMODUL_MODULATION_TYPE, 162 modulation_map[modulation]); 163 } 164 165 static enum modulation rf69_get_modulation(struct spi_device *spi) 166 { 167 u8 modulation_reg; 168 169 modulation_reg = rf69_read_reg(spi, REG_DATAMODUL); 170 171 switch (modulation_reg & MASK_DATAMODUL_MODULATION_TYPE) { 172 case DATAMODUL_MODULATION_TYPE_OOK: 173 return OOK; 174 case DATAMODUL_MODULATION_TYPE_FSK: 175 return FSK; 176 default: 177 return UNDEF; 178 } 179 } 180 181 int rf69_set_modulation_shaping(struct spi_device *spi, 182 enum mod_shaping mod_shaping) 183 { 184 switch (rf69_get_modulation(spi)) { 185 case FSK: 186 switch (mod_shaping) { 187 case SHAPING_OFF: 188 return rf69_read_mod_write(spi, REG_DATAMODUL, 189 MASK_DATAMODUL_MODULATION_SHAPE, 190 DATAMODUL_MODULATION_SHAPE_NONE); 191 case SHAPING_1_0: 192 return rf69_read_mod_write(spi, REG_DATAMODUL, 193 MASK_DATAMODUL_MODULATION_SHAPE, 194 DATAMODUL_MODULATION_SHAPE_1_0); 195 case SHAPING_0_5: 196 return rf69_read_mod_write(spi, REG_DATAMODUL, 197 MASK_DATAMODUL_MODULATION_SHAPE, 198 DATAMODUL_MODULATION_SHAPE_0_5); 199 case SHAPING_0_3: 200 return rf69_read_mod_write(spi, REG_DATAMODUL, 201 MASK_DATAMODUL_MODULATION_SHAPE, 202 DATAMODUL_MODULATION_SHAPE_0_3); 203 default: 204 dev_dbg(&spi->dev, "set: illegal input param"); 205 return -EINVAL; 206 } 207 case OOK: 208 switch (mod_shaping) { 209 case SHAPING_OFF: 210 return rf69_read_mod_write(spi, REG_DATAMODUL, 211 MASK_DATAMODUL_MODULATION_SHAPE, 212 DATAMODUL_MODULATION_SHAPE_NONE); 213 case SHAPING_BR: 214 return rf69_read_mod_write(spi, REG_DATAMODUL, 215 MASK_DATAMODUL_MODULATION_SHAPE, 216 DATAMODUL_MODULATION_SHAPE_BR); 217 case SHAPING_2BR: 218 return rf69_read_mod_write(spi, REG_DATAMODUL, 219 MASK_DATAMODUL_MODULATION_SHAPE, 220 DATAMODUL_MODULATION_SHAPE_2BR); 221 default: 222 dev_dbg(&spi->dev, "set: illegal input param"); 223 return -EINVAL; 224 } 225 default: 226 dev_dbg(&spi->dev, "set: modulation undefined"); 227 return -EINVAL; 228 } 229 } 230 231 int rf69_set_bit_rate(struct spi_device *spi, u16 bit_rate) 232 { 233 int retval; 234 u32 bit_rate_min; 235 u32 bit_rate_reg; 236 u8 msb; 237 u8 lsb; 238 239 // check input value 240 bit_rate_min = F_OSC / 8388608; // 8388608 = 2^23; 241 if (bit_rate < bit_rate_min) { 242 dev_dbg(&spi->dev, "setBitRate: illegal input param"); 243 return -EINVAL; 244 } 245 246 // calculate reg settings 247 bit_rate_reg = (F_OSC / bit_rate); 248 249 msb = (bit_rate_reg & 0xff00) >> 8; 250 lsb = (bit_rate_reg & 0xff); 251 252 // transmit to RF 69 253 retval = rf69_write_reg(spi, REG_BITRATE_MSB, msb); 254 if (retval) 255 return retval; 256 retval = rf69_write_reg(spi, REG_BITRATE_LSB, lsb); 257 if (retval) 258 return retval; 259 260 return 0; 261 } 262 263 int rf69_set_deviation(struct spi_device *spi, u32 deviation) 264 { 265 int retval; 266 u64 f_reg; 267 u64 f_step; 268 u8 msb; 269 u8 lsb; 270 u64 factor = 1000000; // to improve precision of calculation 271 272 // TODO: Dependency to bitrate 273 if (deviation < 600 || deviation > 500000) { 274 dev_dbg(&spi->dev, "set_deviation: illegal input param"); 275 return -EINVAL; 276 } 277 278 // calculat f step 279 f_step = F_OSC * factor; 280 do_div(f_step, 524288); // 524288 = 2^19 281 282 // calculate register settings 283 f_reg = deviation * factor; 284 do_div(f_reg, f_step); 285 286 msb = (f_reg & 0xff00) >> 8; 287 lsb = (f_reg & 0xff); 288 289 // check msb 290 if (msb & ~FDEVMASB_MASK) { 291 dev_dbg(&spi->dev, "set_deviation: err in calc of msb"); 292 return -EINVAL; 293 } 294 295 // write to chip 296 retval = rf69_write_reg(spi, REG_FDEV_MSB, msb); 297 if (retval) 298 return retval; 299 retval = rf69_write_reg(spi, REG_FDEV_LSB, lsb); 300 if (retval) 301 return retval; 302 303 return 0; 304 } 305 306 int rf69_set_frequency(struct spi_device *spi, u32 frequency) 307 { 308 int retval; 309 u32 f_max; 310 u64 f_reg; 311 u64 f_step; 312 u8 msb; 313 u8 mid; 314 u8 lsb; 315 u64 factor = 1000000; // to improve precision of calculation 316 317 // calculat f step 318 f_step = F_OSC * factor; 319 do_div(f_step, 524288); // 524288 = 2^19 320 321 // check input value 322 f_max = div_u64(f_step * 8388608, factor); 323 if (frequency > f_max) { 324 dev_dbg(&spi->dev, "setFrequency: illegal input param"); 325 return -EINVAL; 326 } 327 328 // calculate reg settings 329 f_reg = frequency * factor; 330 do_div(f_reg, f_step); 331 332 msb = (f_reg & 0xff0000) >> 16; 333 mid = (f_reg & 0xff00) >> 8; 334 lsb = (f_reg & 0xff); 335 336 // write to chip 337 retval = rf69_write_reg(spi, REG_FRF_MSB, msb); 338 if (retval) 339 return retval; 340 retval = rf69_write_reg(spi, REG_FRF_MID, mid); 341 if (retval) 342 return retval; 343 retval = rf69_write_reg(spi, REG_FRF_LSB, lsb); 344 if (retval) 345 return retval; 346 347 return 0; 348 } 349 350 int rf69_enable_amplifier(struct spi_device *spi, u8 amplifier_mask) 351 { 352 return rf69_set_bit(spi, REG_PALEVEL, amplifier_mask); 353 } 354 355 int rf69_disable_amplifier(struct spi_device *spi, u8 amplifier_mask) 356 { 357 return rf69_clear_bit(spi, REG_PALEVEL, amplifier_mask); 358 } 359 360 int rf69_set_output_power_level(struct spi_device *spi, u8 power_level) 361 { 362 // TODO: Dependency to PA0,1,2 setting 363 power_level += 18; 364 365 // check input value 366 if (power_level > 0x1f) { 367 dev_dbg(&spi->dev, "set: illegal input param"); 368 return -EINVAL; 369 } 370 371 // write value 372 return rf69_read_mod_write(spi, REG_PALEVEL, MASK_PALEVEL_OUTPUT_POWER, 373 power_level); 374 } 375 376 int rf69_set_pa_ramp(struct spi_device *spi, enum pa_ramp pa_ramp) 377 { 378 static const u8 pa_ramp_map[] = { 379 [ramp3400] = PARAMP_3400, 380 [ramp2000] = PARAMP_2000, 381 [ramp1000] = PARAMP_1000, 382 [ramp500] = PARAMP_500, 383 [ramp250] = PARAMP_250, 384 [ramp125] = PARAMP_125, 385 [ramp100] = PARAMP_100, 386 [ramp62] = PARAMP_62, 387 [ramp50] = PARAMP_50, 388 [ramp40] = PARAMP_40, 389 [ramp31] = PARAMP_31, 390 [ramp25] = PARAMP_25, 391 [ramp20] = PARAMP_20, 392 [ramp15] = PARAMP_15, 393 [ramp10] = PARAMP_10, 394 }; 395 396 if (unlikely(pa_ramp >= ARRAY_SIZE(pa_ramp_map))) { 397 dev_dbg(&spi->dev, "set: illegal input param"); 398 return -EINVAL; 399 } 400 401 return rf69_write_reg(spi, REG_PARAMP, pa_ramp_map[pa_ramp]); 402 } 403 404 int rf69_set_antenna_impedance(struct spi_device *spi, 405 enum antenna_impedance antenna_impedance) 406 { 407 switch (antenna_impedance) { 408 case fifty_ohm: 409 return rf69_clear_bit(spi, REG_LNA, MASK_LNA_ZIN); 410 case two_hundred_ohm: 411 return rf69_set_bit(spi, REG_LNA, MASK_LNA_ZIN); 412 default: 413 dev_dbg(&spi->dev, "set: illegal input param"); 414 return -EINVAL; 415 } 416 } 417 418 int rf69_set_lna_gain(struct spi_device *spi, enum lna_gain lna_gain) 419 { 420 static const u8 lna_gain_map[] = { 421 [automatic] = LNA_GAIN_AUTO, 422 [max] = LNA_GAIN_MAX, 423 [max_minus_6] = LNA_GAIN_MAX_MINUS_6, 424 [max_minus_12] = LNA_GAIN_MAX_MINUS_12, 425 [max_minus_24] = LNA_GAIN_MAX_MINUS_24, 426 [max_minus_36] = LNA_GAIN_MAX_MINUS_36, 427 [max_minus_48] = LNA_GAIN_MAX_MINUS_48, 428 }; 429 430 if (unlikely(lna_gain >= ARRAY_SIZE(lna_gain_map))) { 431 dev_dbg(&spi->dev, "set: illegal input param"); 432 return -EINVAL; 433 } 434 435 return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN, 436 lna_gain_map[lna_gain]); 437 } 438 439 static int rf69_set_bandwidth_intern(struct spi_device *spi, u8 reg, 440 enum mantisse mantisse, u8 exponent) 441 { 442 u8 bandwidth; 443 444 // check value for mantisse and exponent 445 if (exponent > 7) { 446 dev_dbg(&spi->dev, "set: illegal input param"); 447 return -EINVAL; 448 } 449 450 if ((mantisse != mantisse16) && 451 (mantisse != mantisse20) && 452 (mantisse != mantisse24)) { 453 dev_dbg(&spi->dev, "set: illegal input param"); 454 return -EINVAL; 455 } 456 457 // read old value 458 bandwidth = rf69_read_reg(spi, reg); 459 460 // "delete" mantisse and exponent = just keep the DCC setting 461 bandwidth = bandwidth & MASK_BW_DCC_FREQ; 462 463 // add new mantisse 464 switch (mantisse) { 465 case mantisse16: 466 bandwidth = bandwidth | BW_MANT_16; 467 break; 468 case mantisse20: 469 bandwidth = bandwidth | BW_MANT_20; 470 break; 471 case mantisse24: 472 bandwidth = bandwidth | BW_MANT_24; 473 break; 474 } 475 476 // add new exponent 477 bandwidth = bandwidth | exponent; 478 479 // write back 480 return rf69_write_reg(spi, reg, bandwidth); 481 } 482 483 int rf69_set_bandwidth(struct spi_device *spi, enum mantisse mantisse, 484 u8 exponent) 485 { 486 return rf69_set_bandwidth_intern(spi, REG_RXBW, mantisse, exponent); 487 } 488 489 int rf69_set_bandwidth_during_afc(struct spi_device *spi, 490 enum mantisse mantisse, 491 u8 exponent) 492 { 493 return rf69_set_bandwidth_intern(spi, REG_AFCBW, mantisse, exponent); 494 } 495 496 int rf69_set_ook_threshold_dec(struct spi_device *spi, 497 enum threshold_decrement threshold_decrement) 498 { 499 static const u8 td_map[] = { 500 [dec_every8th] = OOKPEAK_THRESHDEC_EVERY_8TH, 501 [dec_every4th] = OOKPEAK_THRESHDEC_EVERY_4TH, 502 [dec_every2nd] = OOKPEAK_THRESHDEC_EVERY_2ND, 503 [dec_once] = OOKPEAK_THRESHDEC_ONCE, 504 [dec_twice] = OOKPEAK_THRESHDEC_TWICE, 505 [dec_4times] = OOKPEAK_THRESHDEC_4_TIMES, 506 [dec_8times] = OOKPEAK_THRESHDEC_8_TIMES, 507 [dec_16times] = OOKPEAK_THRESHDEC_16_TIMES, 508 }; 509 510 if (unlikely(threshold_decrement >= ARRAY_SIZE(td_map))) { 511 dev_dbg(&spi->dev, "set: illegal input param"); 512 return -EINVAL; 513 } 514 515 return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, 516 td_map[threshold_decrement]); 517 } 518 519 int rf69_set_dio_mapping(struct spi_device *spi, u8 dio_number, u8 value) 520 { 521 u8 mask; 522 u8 shift; 523 u8 dio_addr; 524 u8 dio_value; 525 526 switch (dio_number) { 527 case 0: 528 mask = MASK_DIO0; 529 shift = SHIFT_DIO0; 530 dio_addr = REG_DIOMAPPING1; 531 break; 532 case 1: 533 mask = MASK_DIO1; 534 shift = SHIFT_DIO1; 535 dio_addr = REG_DIOMAPPING1; 536 break; 537 case 2: 538 mask = MASK_DIO2; 539 shift = SHIFT_DIO2; 540 dio_addr = REG_DIOMAPPING1; 541 break; 542 case 3: 543 mask = MASK_DIO3; 544 shift = SHIFT_DIO3; 545 dio_addr = REG_DIOMAPPING1; 546 break; 547 case 4: 548 mask = MASK_DIO4; 549 shift = SHIFT_DIO4; 550 dio_addr = REG_DIOMAPPING2; 551 break; 552 case 5: 553 mask = MASK_DIO5; 554 shift = SHIFT_DIO5; 555 dio_addr = REG_DIOMAPPING2; 556 break; 557 default: 558 dev_dbg(&spi->dev, "set: illegal input param"); 559 return -EINVAL; 560 } 561 562 // read reg 563 dio_value = rf69_read_reg(spi, dio_addr); 564 // delete old value 565 dio_value = dio_value & ~mask; 566 // add new value 567 dio_value = dio_value | value << shift; 568 // write back 569 return rf69_write_reg(spi, dio_addr, dio_value); 570 } 571 572 bool rf69_get_flag(struct spi_device *spi, enum flag flag) 573 { 574 switch (flag) { 575 case mode_switch_completed: 576 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_MODE_READY); 577 case ready_to_receive: 578 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_RX_READY); 579 case ready_to_send: 580 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_TX_READY); 581 case pll_locked: 582 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_PLL_LOCK); 583 case rssi_exceeded_threshold: 584 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_RSSI); 585 case timeout: 586 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_TIMEOUT); 587 case automode: 588 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_AUTOMODE); 589 case sync_address_match: 590 return (rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH); 591 case fifo_full: 592 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_FULL); 593 /* 594 * case fifo_not_empty: 595 * return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_NOT_EMPTY); 596 */ 597 case fifo_empty: 598 return !(rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_NOT_EMPTY); 599 case fifo_level_below_threshold: 600 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_LEVEL); 601 case fifo_overrun: 602 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_FIFO_OVERRUN); 603 case packet_sent: 604 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_PACKET_SENT); 605 case payload_ready: 606 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_PAYLOAD_READY); 607 case crc_ok: 608 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_CRC_OK); 609 case battery_low: 610 return (rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_LOW_BAT); 611 default: return false; 612 } 613 } 614 615 int rf69_set_rssi_threshold(struct spi_device *spi, u8 threshold) 616 { 617 /* no value check needed - u8 exactly matches register size */ 618 619 return rf69_write_reg(spi, REG_RSSITHRESH, threshold); 620 } 621 622 int rf69_set_preamble_length(struct spi_device *spi, u16 preamble_length) 623 { 624 int retval; 625 u8 msb, lsb; 626 627 /* no value check needed - u16 exactly matches register size */ 628 629 /* calculate reg settings */ 630 msb = (preamble_length & 0xff00) >> 8; 631 lsb = (preamble_length & 0xff); 632 633 /* transmit to chip */ 634 retval = rf69_write_reg(spi, REG_PREAMBLE_MSB, msb); 635 if (retval) 636 return retval; 637 retval = rf69_write_reg(spi, REG_PREAMBLE_LSB, lsb); 638 639 return retval; 640 } 641 642 int rf69_enable_sync(struct spi_device *spi) 643 { 644 return rf69_set_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON); 645 } 646 647 int rf69_disable_sync(struct spi_device *spi) 648 { 649 return rf69_clear_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON); 650 } 651 652 int rf69_set_fifo_fill_condition(struct spi_device *spi, 653 enum fifo_fill_condition fifo_fill_condition) 654 { 655 switch (fifo_fill_condition) { 656 case always: 657 return rf69_set_bit(spi, REG_SYNC_CONFIG, 658 MASK_SYNC_CONFIG_FIFO_FILL_CONDITION); 659 case after_sync_interrupt: 660 return rf69_clear_bit(spi, REG_SYNC_CONFIG, 661 MASK_SYNC_CONFIG_FIFO_FILL_CONDITION); 662 default: 663 dev_dbg(&spi->dev, "set: illegal input param"); 664 return -EINVAL; 665 } 666 } 667 668 int rf69_set_sync_size(struct spi_device *spi, u8 sync_size) 669 { 670 // check input value 671 if (sync_size > 0x07) { 672 dev_dbg(&spi->dev, "set: illegal input param"); 673 return -EINVAL; 674 } 675 676 // write value 677 return rf69_read_mod_write(spi, REG_SYNC_CONFIG, 678 MASK_SYNC_CONFIG_SYNC_SIZE, 679 (sync_size << 3)); 680 } 681 682 int rf69_set_sync_values(struct spi_device *spi, u8 sync_values[8]) 683 { 684 int retval = 0; 685 686 retval += rf69_write_reg(spi, REG_SYNCVALUE1, sync_values[0]); 687 retval += rf69_write_reg(spi, REG_SYNCVALUE2, sync_values[1]); 688 retval += rf69_write_reg(spi, REG_SYNCVALUE3, sync_values[2]); 689 retval += rf69_write_reg(spi, REG_SYNCVALUE4, sync_values[3]); 690 retval += rf69_write_reg(spi, REG_SYNCVALUE5, sync_values[4]); 691 retval += rf69_write_reg(spi, REG_SYNCVALUE6, sync_values[5]); 692 retval += rf69_write_reg(spi, REG_SYNCVALUE7, sync_values[6]); 693 retval += rf69_write_reg(spi, REG_SYNCVALUE8, sync_values[7]); 694 695 return retval; 696 } 697 698 int rf69_set_packet_format(struct spi_device *spi, 699 enum packet_format packet_format) 700 { 701 switch (packet_format) { 702 case packet_length_var: 703 return rf69_set_bit(spi, REG_PACKETCONFIG1, 704 MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE); 705 case packet_length_fix: 706 return rf69_clear_bit(spi, REG_PACKETCONFIG1, 707 MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE); 708 default: 709 dev_dbg(&spi->dev, "set: illegal input param"); 710 return -EINVAL; 711 } 712 } 713 714 int rf69_enable_crc(struct spi_device *spi) 715 { 716 return rf69_set_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON); 717 } 718 719 int rf69_disable_crc(struct spi_device *spi) 720 { 721 return rf69_clear_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON); 722 } 723 724 int rf69_set_address_filtering(struct spi_device *spi, 725 enum address_filtering address_filtering) 726 { 727 static const u8 af_map[] = { 728 [filtering_off] = PACKETCONFIG1_ADDRESSFILTERING_OFF, 729 [node_address] = PACKETCONFIG1_ADDRESSFILTERING_NODE, 730 [node_or_broadcast_address] = 731 PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST, 732 }; 733 734 if (unlikely(address_filtering >= ARRAY_SIZE(af_map))) { 735 dev_dbg(&spi->dev, "set: illegal input param"); 736 return -EINVAL; 737 } 738 739 return rf69_read_mod_write(spi, REG_PACKETCONFIG1, 740 MASK_PACKETCONFIG1_ADDRESSFILTERING, 741 af_map[address_filtering]); 742 } 743 744 int rf69_set_payload_length(struct spi_device *spi, u8 payload_length) 745 { 746 return rf69_write_reg(spi, REG_PAYLOAD_LENGTH, payload_length); 747 } 748 749 int rf69_set_node_address(struct spi_device *spi, u8 node_address) 750 { 751 return rf69_write_reg(spi, REG_NODEADRS, node_address); 752 } 753 754 int rf69_set_broadcast_address(struct spi_device *spi, u8 broadcast_address) 755 { 756 return rf69_write_reg(spi, REG_BROADCASTADRS, broadcast_address); 757 } 758 759 int rf69_set_tx_start_condition(struct spi_device *spi, 760 enum tx_start_condition tx_start_condition) 761 { 762 switch (tx_start_condition) { 763 case fifo_level: 764 return rf69_clear_bit(spi, REG_FIFO_THRESH, 765 MASK_FIFO_THRESH_TXSTART); 766 case fifo_not_empty: 767 return rf69_set_bit(spi, REG_FIFO_THRESH, 768 MASK_FIFO_THRESH_TXSTART); 769 default: 770 dev_dbg(&spi->dev, "set: illegal input param"); 771 return -EINVAL; 772 } 773 } 774 775 int rf69_set_fifo_threshold(struct spi_device *spi, u8 threshold) 776 { 777 int retval; 778 779 /* check input value */ 780 if (threshold & 0x80) { 781 dev_dbg(&spi->dev, "set: illegal input param"); 782 return -EINVAL; 783 } 784 785 /* write value */ 786 retval = rf69_read_mod_write(spi, REG_FIFO_THRESH, 787 MASK_FIFO_THRESH_VALUE, 788 threshold); 789 if (retval) 790 return retval; 791 792 /* 793 * access the fifo to activate new threshold 794 * retval (mis-) used as buffer here 795 */ 796 return rf69_read_fifo(spi, (u8 *)&retval, 1); 797 } 798 799 int rf69_set_dagc(struct spi_device *spi, enum dagc dagc) 800 { 801 static const u8 dagc_map[] = { 802 [normal_mode] = DAGC_NORMAL, 803 [improve] = DAGC_IMPROVED_LOWBETA0, 804 [improve_for_low_modulation_index] = DAGC_IMPROVED_LOWBETA1, 805 }; 806 807 if (unlikely(dagc >= ARRAY_SIZE(dagc_map))) { 808 dev_dbg(&spi->dev, "set: illegal input param"); 809 return -EINVAL; 810 } 811 812 return rf69_write_reg(spi, REG_TESTDAGC, dagc_map[dagc]); 813 } 814 815 /*-------------------------------------------------------------------------*/ 816 817 int rf69_read_fifo(struct spi_device *spi, u8 *buffer, unsigned int size) 818 { 819 #ifdef DEBUG_FIFO_ACCESS 820 int i; 821 #endif 822 struct spi_transfer transfer; 823 u8 local_buffer[FIFO_SIZE + 1]; 824 int retval; 825 826 if (size > FIFO_SIZE) { 827 dev_dbg(&spi->dev, 828 "read fifo: passed in buffer bigger then internal buffer\n"); 829 return -EMSGSIZE; 830 } 831 832 /* prepare a bidirectional transfer */ 833 local_buffer[0] = REG_FIFO; 834 memset(&transfer, 0, sizeof(transfer)); 835 transfer.tx_buf = local_buffer; 836 transfer.rx_buf = local_buffer; 837 transfer.len = size + 1; 838 839 retval = spi_sync_transfer(spi, &transfer, 1); 840 841 #ifdef DEBUG_FIFO_ACCESS 842 for (i = 0; i < size; i++) 843 dev_dbg(&spi->dev, "%d - 0x%x\n", i, local_buffer[i + 1]); 844 #endif 845 846 memcpy(buffer, &local_buffer[1], size); 847 848 return retval; 849 } 850 851 int rf69_write_fifo(struct spi_device *spi, u8 *buffer, unsigned int size) 852 { 853 #ifdef DEBUG_FIFO_ACCESS 854 int i; 855 #endif 856 u8 local_buffer[FIFO_SIZE + 1]; 857 858 if (size > FIFO_SIZE) { 859 dev_dbg(&spi->dev, 860 "read fifo: passed in buffer bigger then internal buffer\n"); 861 return -EMSGSIZE; 862 } 863 864 local_buffer[0] = REG_FIFO | WRITE_BIT; 865 memcpy(&local_buffer[1], buffer, size); 866 867 #ifdef DEBUG_FIFO_ACCESS 868 for (i = 0; i < size; i++) 869 dev_dbg(&spi->dev, "0x%x\n", buffer[i]); 870 #endif 871 872 return spi_write(spi, local_buffer, size + 1); 873 } 874 875