1 /* 2 * Copyright (c) 2009,2010 One Laptop per Child 3 * 4 * This program is free software. You can redistribute it and/or 5 * modify it under the terms of version 2 of the GNU General Public 6 * License as published by the Free Software Foundation. 7 */ 8 9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 10 11 #include <linux/acpi.h> 12 #include <linux/delay.h> 13 #include <linux/gpio.h> 14 #include <asm/olpc.h> 15 16 /* TODO: this eventually belongs in linux/vx855.h */ 17 #define NR_VX855_GPI 14 18 #define NR_VX855_GPO 13 19 #define NR_VX855_GPIO 15 20 21 #define VX855_GPI(n) (n) 22 #define VX855_GPO(n) (NR_VX855_GPI + (n)) 23 #define VX855_GPIO(n) (NR_VX855_GPI + NR_VX855_GPO + (n)) 24 25 #include "olpc_dcon.h" 26 27 /* Hardware setup on the XO 1.5: 28 * DCONLOAD connects to VX855_GPIO1 (not SMBCK2) 29 * DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver 30 * DCONSTAT0 connects to VX855_GPI10 (not SSPISDI) 31 * DCONSTAT1 connects to VX855_GPI11 (not nSSPISS) 32 * DCONIRQ connects to VX855_GPIO12 33 * DCONSMBDATA connects to VX855 graphics CRTSPD 34 * DCONSMBCLK connects to VX855 graphics CRTSPCLK 35 */ 36 37 #define VX855_GENL_PURPOSE_OUTPUT 0x44c /* PMIO_Rx4c-4f */ 38 #define VX855_GPI_STATUS_CHG 0x450 /* PMIO_Rx50 */ 39 #define VX855_GPI_SCI_SMI 0x452 /* PMIO_Rx52 */ 40 #define BIT_GPIO12 0x40 41 42 #define PREFIX "OLPC DCON:" 43 44 static void dcon_clear_irq(void) 45 { 46 /* irq status will appear in PMIO_Rx50[6] (RW1C) on gpio12 */ 47 outb(BIT_GPIO12, VX855_GPI_STATUS_CHG); 48 } 49 50 static int dcon_was_irq(void) 51 { 52 u8 tmp; 53 54 /* irq status will appear in PMIO_Rx50[6] on gpio12 */ 55 tmp = inb(VX855_GPI_STATUS_CHG); 56 57 return !!(tmp & BIT_GPIO12); 58 } 59 60 static int dcon_init_xo_1_5(struct dcon_priv *dcon) 61 { 62 unsigned int irq; 63 64 dcon_clear_irq(); 65 66 /* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */ 67 outb(inb(VX855_GPI_SCI_SMI) | BIT_GPIO12, VX855_GPI_SCI_SMI); 68 69 /* Determine the current state of DCONLOAD, likely set by firmware */ 70 /* GPIO1 */ 71 dcon->curr_src = (inl(VX855_GENL_PURPOSE_OUTPUT) & 0x1000) ? 72 DCON_SOURCE_CPU : DCON_SOURCE_DCON; 73 dcon->pending_src = dcon->curr_src; 74 75 /* we're sharing the IRQ with ACPI */ 76 irq = acpi_gbl_FADT.sci_interrupt; 77 if (request_irq(irq, &dcon_interrupt, IRQF_SHARED, "DCON", dcon)) { 78 pr_err("DCON (IRQ%d) allocation failed\n", irq); 79 return 1; 80 } 81 82 return 0; 83 } 84 85 static void set_i2c_line(int sda, int scl) 86 { 87 unsigned char tmp; 88 unsigned int port = 0x26; 89 90 /* FIXME: This directly accesses the CRT GPIO controller !!! */ 91 outb(port, 0x3c4); 92 tmp = inb(0x3c5); 93 94 if (scl) 95 tmp |= 0x20; 96 else 97 tmp &= ~0x20; 98 99 if (sda) 100 tmp |= 0x10; 101 else 102 tmp &= ~0x10; 103 104 tmp |= 0x01; 105 106 outb(port, 0x3c4); 107 outb(tmp, 0x3c5); 108 } 109 110 static void dcon_wiggle_xo_1_5(void) 111 { 112 int x; 113 114 /* 115 * According to HiMax, when powering the DCON up we should hold 116 * SMB_DATA high for 8 SMB_CLK cycles. This will force the DCON 117 * state machine to reset to a (sane) initial state. Mitch Bradley 118 * did some testing and discovered that holding for 16 SMB_CLK cycles 119 * worked a lot more reliably, so that's what we do here. 120 */ 121 set_i2c_line(1, 1); 122 123 for (x = 0; x < 16; x++) { 124 udelay(5); 125 set_i2c_line(1, 0); 126 udelay(5); 127 set_i2c_line(1, 1); 128 } 129 udelay(5); 130 131 /* set PMIO_Rx52[6] to enable SCI/SMI on gpio12 */ 132 outb(inb(VX855_GPI_SCI_SMI) | BIT_GPIO12, VX855_GPI_SCI_SMI); 133 } 134 135 static void dcon_set_dconload_xo_1_5(int val) 136 { 137 gpio_set_value(VX855_GPIO(1), val); 138 } 139 140 static int dcon_read_status_xo_1_5(u8 *status) 141 { 142 if (!dcon_was_irq()) 143 return -1; 144 145 /* i believe this is the same as "inb(0x44b) & 3" */ 146 *status = gpio_get_value(VX855_GPI(10)); 147 *status |= gpio_get_value(VX855_GPI(11)) << 1; 148 149 dcon_clear_irq(); 150 151 return 0; 152 } 153 154 struct dcon_platform_data dcon_pdata_xo_1_5 = { 155 .init = dcon_init_xo_1_5, 156 .bus_stabilize_wiggle = dcon_wiggle_xo_1_5, 157 .set_dconload = dcon_set_dconload_xo_1_5, 158 .read_status = dcon_read_status_xo_1_5, 159 }; 160