1 /* 2 * NVEC: NVIDIA compliant embedded controller interface 3 * 4 * Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net> 5 * 6 * Authors: Pierre-Hugues Husson <phhusson@free.fr> 7 * Ilya Petrov <ilya.muromec@gmail.com> 8 * Marc Dietrich <marvin24@gmx.de> 9 * Julian Andres Klode <jak@jak-linux.org> 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 * 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/atomic.h> 20 #include <linux/clk.h> 21 #include <linux/completion.h> 22 #include <linux/delay.h> 23 #include <linux/err.h> 24 #include <linux/gpio.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/irq.h> 28 #include <linux/of.h> 29 #include <linux/of_gpio.h> 30 #include <linux/list.h> 31 #include <linux/mfd/core.h> 32 #include <linux/mutex.h> 33 #include <linux/notifier.h> 34 #include <linux/slab.h> 35 #include <linux/spinlock.h> 36 #include <linux/workqueue.h> 37 38 #include "nvec.h" 39 40 #define I2C_CNFG 0x00 41 #define I2C_CNFG_PACKET_MODE_EN (1 << 10) 42 #define I2C_CNFG_NEW_MASTER_SFM (1 << 11) 43 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 44 45 #define I2C_SL_CNFG 0x20 46 #define I2C_SL_NEWSL (1 << 2) 47 #define I2C_SL_NACK (1 << 1) 48 #define I2C_SL_RESP (1 << 0) 49 #define I2C_SL_IRQ (1 << 3) 50 #define END_TRANS (1 << 4) 51 #define RCVD (1 << 2) 52 #define RNW (1 << 1) 53 54 #define I2C_SL_RCVD 0x24 55 #define I2C_SL_STATUS 0x28 56 #define I2C_SL_ADDR1 0x2c 57 #define I2C_SL_ADDR2 0x30 58 #define I2C_SL_DELAY_COUNT 0x3c 59 60 /** 61 * enum nvec_msg_category - Message categories for nvec_msg_alloc() 62 * @NVEC_MSG_RX: The message is an incoming message (from EC) 63 * @NVEC_MSG_TX: The message is an outgoing message (to EC) 64 */ 65 enum nvec_msg_category { 66 NVEC_MSG_RX, 67 NVEC_MSG_TX, 68 }; 69 70 enum nvec_sleep_subcmds { 71 GLOBAL_EVENTS, 72 AP_PWR_DOWN, 73 AP_SUSPEND, 74 }; 75 76 #define CNF_EVENT_REPORTING 0x01 77 #define GET_FIRMWARE_VERSION 0x15 78 #define LID_SWITCH BIT(1) 79 #define PWR_BUTTON BIT(15) 80 81 static struct nvec_chip *nvec_power_handle; 82 83 static const struct mfd_cell nvec_devices[] = { 84 { 85 .name = "nvec-kbd", 86 }, 87 { 88 .name = "nvec-mouse", 89 }, 90 { 91 .name = "nvec-power", 92 .id = 0, 93 }, 94 { 95 .name = "nvec-power", 96 .id = 1, 97 }, 98 { 99 .name = "nvec-paz00", 100 }, 101 }; 102 103 /** 104 * nvec_register_notifier - Register a notifier with nvec 105 * @nvec: A &struct nvec_chip 106 * @nb: The notifier block to register 107 * 108 * Registers a notifier with @nvec. The notifier will be added to an atomic 109 * notifier chain that is called for all received messages except those that 110 * correspond to a request initiated by nvec_write_sync(). 111 */ 112 int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb, 113 unsigned int events) 114 { 115 return atomic_notifier_chain_register(&nvec->notifier_list, nb); 116 } 117 EXPORT_SYMBOL_GPL(nvec_register_notifier); 118 119 /** 120 * nvec_unregister_notifier - Unregister a notifier with nvec 121 * @nvec: A &struct nvec_chip 122 * @nb: The notifier block to unregister 123 * 124 * Unregisters a notifier with @nvec. The notifier will be removed from the 125 * atomic notifier chain. 126 */ 127 int nvec_unregister_notifier(struct nvec_chip *nvec, struct notifier_block *nb) 128 { 129 return atomic_notifier_chain_unregister(&nvec->notifier_list, nb); 130 } 131 EXPORT_SYMBOL_GPL(nvec_unregister_notifier); 132 133 /** 134 * nvec_status_notifier - The final notifier 135 * 136 * Prints a message about control events not handled in the notifier 137 * chain. 138 */ 139 static int nvec_status_notifier(struct notifier_block *nb, 140 unsigned long event_type, void *data) 141 { 142 struct nvec_chip *nvec = container_of(nb, struct nvec_chip, 143 nvec_status_notifier); 144 unsigned char *msg = (unsigned char *)data; 145 146 if (event_type != NVEC_CNTL) 147 return NOTIFY_DONE; 148 149 dev_warn(nvec->dev, "unhandled msg type %ld\n", event_type); 150 print_hex_dump(KERN_WARNING, "payload: ", DUMP_PREFIX_NONE, 16, 1, 151 msg, msg[1] + 2, true); 152 153 return NOTIFY_OK; 154 } 155 156 /** 157 * nvec_msg_alloc: 158 * @nvec: A &struct nvec_chip 159 * @category: Pool category, see &enum nvec_msg_category 160 * 161 * Allocate a single &struct nvec_msg object from the message pool of 162 * @nvec. The result shall be passed to nvec_msg_free() if no longer 163 * used. 164 * 165 * Outgoing messages are placed in the upper 75% of the pool, keeping the 166 * lower 25% available for RX buffers only. The reason is to prevent a 167 * situation where all buffers are full and a message is thus endlessly 168 * retried because the response could never be processed. 169 */ 170 static struct nvec_msg *nvec_msg_alloc(struct nvec_chip *nvec, 171 enum nvec_msg_category category) 172 { 173 int i = (category == NVEC_MSG_TX) ? (NVEC_POOL_SIZE / 4) : 0; 174 175 for (; i < NVEC_POOL_SIZE; i++) { 176 if (atomic_xchg(&nvec->msg_pool[i].used, 1) == 0) { 177 dev_vdbg(nvec->dev, "INFO: Allocate %i\n", i); 178 return &nvec->msg_pool[i]; 179 } 180 } 181 182 dev_err(nvec->dev, "could not allocate %s buffer\n", 183 (category == NVEC_MSG_TX) ? "TX" : "RX"); 184 185 return NULL; 186 } 187 188 /** 189 * nvec_msg_free: 190 * @nvec: A &struct nvec_chip 191 * @msg: A message (must be allocated by nvec_msg_alloc() and belong to @nvec) 192 * 193 * Free the given message 194 */ 195 void nvec_msg_free(struct nvec_chip *nvec, struct nvec_msg *msg) 196 { 197 if (msg != &nvec->tx_scratch) 198 dev_vdbg(nvec->dev, "INFO: Free %ti\n", msg - nvec->msg_pool); 199 atomic_set(&msg->used, 0); 200 } 201 EXPORT_SYMBOL_GPL(nvec_msg_free); 202 203 /** 204 * nvec_msg_is_event - Return %true if @msg is an event 205 * @msg: A message 206 */ 207 static bool nvec_msg_is_event(struct nvec_msg *msg) 208 { 209 return msg->data[0] >> 7; 210 } 211 212 /** 213 * nvec_msg_size - Get the size of a message 214 * @msg: The message to get the size for 215 * 216 * This only works for received messages, not for outgoing messages. 217 */ 218 static size_t nvec_msg_size(struct nvec_msg *msg) 219 { 220 bool is_event = nvec_msg_is_event(msg); 221 int event_length = (msg->data[0] & 0x60) >> 5; 222 223 /* for variable size, payload size in byte 1 + count (1) + cmd (1) */ 224 if (!is_event || event_length == NVEC_VAR_SIZE) 225 return (msg->pos || msg->size) ? (msg->data[1] + 2) : 0; 226 else if (event_length == NVEC_2BYTES) 227 return 2; 228 else if (event_length == NVEC_3BYTES) 229 return 3; 230 return 0; 231 } 232 233 /** 234 * nvec_gpio_set_value - Set the GPIO value 235 * @nvec: A &struct nvec_chip 236 * @value: The value to write (0 or 1) 237 * 238 * Like gpio_set_value(), but generating debugging information 239 */ 240 static void nvec_gpio_set_value(struct nvec_chip *nvec, int value) 241 { 242 dev_dbg(nvec->dev, "GPIO changed from %u to %u\n", 243 gpio_get_value(nvec->gpio), value); 244 gpio_set_value(nvec->gpio, value); 245 } 246 247 /** 248 * nvec_write_async - Asynchronously write a message to NVEC 249 * @nvec: An nvec_chip instance 250 * @data: The message data, starting with the request type 251 * @size: The size of @data 252 * 253 * Queue a single message to be transferred to the embedded controller 254 * and return immediately. 255 * 256 * Returns: 0 on success, a negative error code on failure. If a failure 257 * occurred, the nvec driver may print an error. 258 */ 259 int nvec_write_async(struct nvec_chip *nvec, const unsigned char *data, 260 short size) 261 { 262 struct nvec_msg *msg; 263 unsigned long flags; 264 265 msg = nvec_msg_alloc(nvec, NVEC_MSG_TX); 266 267 if (msg == NULL) 268 return -ENOMEM; 269 270 msg->data[0] = size; 271 memcpy(msg->data + 1, data, size); 272 msg->size = size + 1; 273 274 spin_lock_irqsave(&nvec->tx_lock, flags); 275 list_add_tail(&msg->node, &nvec->tx_data); 276 spin_unlock_irqrestore(&nvec->tx_lock, flags); 277 278 schedule_work(&nvec->tx_work); 279 280 return 0; 281 } 282 EXPORT_SYMBOL(nvec_write_async); 283 284 /** 285 * nvec_write_sync - Write a message to nvec and read the response 286 * @nvec: An &struct nvec_chip 287 * @data: The data to write 288 * @size: The size of @data 289 * 290 * This is similar to nvec_write_async(), but waits for the 291 * request to be answered before returning. This function 292 * uses a mutex and can thus not be called from e.g. 293 * interrupt handlers. 294 * 295 * Returns: A pointer to the response message on success, 296 * %NULL on failure. Free with nvec_msg_free() once no longer 297 * used. 298 */ 299 struct nvec_msg *nvec_write_sync(struct nvec_chip *nvec, 300 const unsigned char *data, short size) 301 { 302 struct nvec_msg *msg; 303 304 mutex_lock(&nvec->sync_write_mutex); 305 306 nvec->sync_write_pending = (data[1] << 8) + data[0]; 307 308 if (nvec_write_async(nvec, data, size) < 0) { 309 mutex_unlock(&nvec->sync_write_mutex); 310 return NULL; 311 } 312 313 dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n", 314 nvec->sync_write_pending); 315 if (!(wait_for_completion_timeout(&nvec->sync_write, 316 msecs_to_jiffies(2000)))) { 317 dev_warn(nvec->dev, "timeout waiting for sync write to complete\n"); 318 mutex_unlock(&nvec->sync_write_mutex); 319 return NULL; 320 } 321 322 dev_dbg(nvec->dev, "nvec_sync_write: pong!\n"); 323 324 msg = nvec->last_sync_msg; 325 326 mutex_unlock(&nvec->sync_write_mutex); 327 328 return msg; 329 } 330 EXPORT_SYMBOL(nvec_write_sync); 331 332 /** 333 * nvec_toggle_global_events - enables or disables global event reporting 334 * @nvec: nvec handle 335 * @state: true for enable, false for disable 336 * 337 * This switches on/off global event reports by the embedded controller. 338 */ 339 static void nvec_toggle_global_events(struct nvec_chip *nvec, bool state) 340 { 341 unsigned char global_events[] = { NVEC_SLEEP, GLOBAL_EVENTS, state }; 342 343 nvec_write_async(nvec, global_events, 3); 344 } 345 346 /** 347 * nvec_event_mask - fill the command string with event bitfield 348 * ev: points to event command string 349 * mask: bit to insert into the event mask 350 * 351 * Configure event command expects a 32 bit bitfield which describes 352 * which events to enable. The bitfield has the following structure 353 * (from highest byte to lowest): 354 * system state bits 7-0 355 * system state bits 15-8 356 * oem system state bits 7-0 357 * oem system state bits 15-8 358 */ 359 static void nvec_event_mask(char *ev, u32 mask) 360 { 361 ev[3] = mask >> 16 & 0xff; 362 ev[4] = mask >> 24 & 0xff; 363 ev[5] = mask >> 0 & 0xff; 364 ev[6] = mask >> 8 & 0xff; 365 } 366 367 /** 368 * nvec_request_master - Process outgoing messages 369 * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip) 370 * 371 * Processes all outgoing requests by sending the request and awaiting the 372 * response, then continuing with the next request. Once a request has a 373 * matching response, it will be freed and removed from the list. 374 */ 375 static void nvec_request_master(struct work_struct *work) 376 { 377 struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work); 378 unsigned long flags; 379 long err; 380 struct nvec_msg *msg; 381 382 spin_lock_irqsave(&nvec->tx_lock, flags); 383 while (!list_empty(&nvec->tx_data)) { 384 msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node); 385 spin_unlock_irqrestore(&nvec->tx_lock, flags); 386 nvec_gpio_set_value(nvec, 0); 387 err = wait_for_completion_interruptible_timeout( 388 &nvec->ec_transfer, msecs_to_jiffies(5000)); 389 390 if (err == 0) { 391 dev_warn(nvec->dev, "timeout waiting for ec transfer\n"); 392 nvec_gpio_set_value(nvec, 1); 393 msg->pos = 0; 394 } 395 396 spin_lock_irqsave(&nvec->tx_lock, flags); 397 398 if (err > 0) { 399 list_del_init(&msg->node); 400 nvec_msg_free(nvec, msg); 401 } 402 } 403 spin_unlock_irqrestore(&nvec->tx_lock, flags); 404 } 405 406 /** 407 * parse_msg - Print some information and call the notifiers on an RX message 408 * @nvec: A &struct nvec_chip 409 * @msg: A message received by @nvec 410 * 411 * Paarse some pieces of the message and then call the chain of notifiers 412 * registered via nvec_register_notifier. 413 */ 414 static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg) 415 { 416 if ((msg->data[0] & 1 << 7) == 0 && msg->data[3]) { 417 dev_err(nvec->dev, "ec responded %*ph\n", 4, msg->data); 418 return -EINVAL; 419 } 420 421 if ((msg->data[0] >> 7) == 1 && (msg->data[0] & 0x0f) == 5) 422 print_hex_dump(KERN_WARNING, "ec system event ", 423 DUMP_PREFIX_NONE, 16, 1, msg->data, 424 msg->data[1] + 2, true); 425 426 atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f, 427 msg->data); 428 429 return 0; 430 } 431 432 /** 433 * nvec_dispatch - Process messages received from the EC 434 * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip) 435 * 436 * Process messages previously received from the EC and put into the RX 437 * queue of the &struct nvec_chip instance associated with @work. 438 */ 439 static void nvec_dispatch(struct work_struct *work) 440 { 441 struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work); 442 unsigned long flags; 443 struct nvec_msg *msg; 444 445 spin_lock_irqsave(&nvec->rx_lock, flags); 446 while (!list_empty(&nvec->rx_data)) { 447 msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node); 448 list_del_init(&msg->node); 449 spin_unlock_irqrestore(&nvec->rx_lock, flags); 450 451 if (nvec->sync_write_pending == 452 (msg->data[2] << 8) + msg->data[0]) { 453 dev_dbg(nvec->dev, "sync write completed!\n"); 454 nvec->sync_write_pending = 0; 455 nvec->last_sync_msg = msg; 456 complete(&nvec->sync_write); 457 } else { 458 parse_msg(nvec, msg); 459 nvec_msg_free(nvec, msg); 460 } 461 spin_lock_irqsave(&nvec->rx_lock, flags); 462 } 463 spin_unlock_irqrestore(&nvec->rx_lock, flags); 464 } 465 466 /** 467 * nvec_tx_completed - Complete the current transfer 468 * @nvec: A &struct nvec_chip 469 * 470 * This is called when we have received an END_TRANS on a TX transfer. 471 */ 472 static void nvec_tx_completed(struct nvec_chip *nvec) 473 { 474 /* We got an END_TRANS, let's skip this, maybe there's an event */ 475 if (nvec->tx->pos != nvec->tx->size) { 476 dev_err(nvec->dev, "premature END_TRANS, resending\n"); 477 nvec->tx->pos = 0; 478 nvec_gpio_set_value(nvec, 0); 479 } else { 480 nvec->state = 0; 481 } 482 } 483 484 /** 485 * nvec_rx_completed - Complete the current transfer 486 * @nvec: A &struct nvec_chip 487 * 488 * This is called when we have received an END_TRANS on a RX transfer. 489 */ 490 static void nvec_rx_completed(struct nvec_chip *nvec) 491 { 492 if (nvec->rx->pos != nvec_msg_size(nvec->rx)) { 493 dev_err(nvec->dev, "RX incomplete: Expected %u bytes, got %u\n", 494 (uint) nvec_msg_size(nvec->rx), 495 (uint) nvec->rx->pos); 496 497 nvec_msg_free(nvec, nvec->rx); 498 nvec->state = 0; 499 500 /* Battery quirk - Often incomplete, and likes to crash */ 501 if (nvec->rx->data[0] == NVEC_BAT) 502 complete(&nvec->ec_transfer); 503 504 return; 505 } 506 507 spin_lock(&nvec->rx_lock); 508 509 /* 510 * Add the received data to the work list and move the ring buffer 511 * pointer to the next entry. 512 */ 513 list_add_tail(&nvec->rx->node, &nvec->rx_data); 514 515 spin_unlock(&nvec->rx_lock); 516 517 nvec->state = 0; 518 519 if (!nvec_msg_is_event(nvec->rx)) 520 complete(&nvec->ec_transfer); 521 522 schedule_work(&nvec->rx_work); 523 } 524 525 /** 526 * nvec_invalid_flags - Send an error message about invalid flags and jump 527 * @nvec: The nvec device 528 * @status: The status flags 529 * @reset: Whether we shall jump to state 0. 530 */ 531 static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status, 532 bool reset) 533 { 534 dev_err(nvec->dev, "unexpected status flags 0x%02x during state %i\n", 535 status, nvec->state); 536 if (reset) 537 nvec->state = 0; 538 } 539 540 /** 541 * nvec_tx_set - Set the message to transfer (nvec->tx) 542 * @nvec: A &struct nvec_chip 543 * 544 * Gets the first entry from the tx_data list of @nvec and sets the 545 * tx member to it. If the tx_data list is empty, this uses the 546 * tx_scratch message to send a no operation message. 547 */ 548 static void nvec_tx_set(struct nvec_chip *nvec) 549 { 550 spin_lock(&nvec->tx_lock); 551 if (list_empty(&nvec->tx_data)) { 552 dev_err(nvec->dev, "empty tx - sending no-op\n"); 553 memcpy(nvec->tx_scratch.data, "\x02\x07\x02", 3); 554 nvec->tx_scratch.size = 3; 555 nvec->tx_scratch.pos = 0; 556 nvec->tx = &nvec->tx_scratch; 557 list_add_tail(&nvec->tx->node, &nvec->tx_data); 558 } else { 559 nvec->tx = list_first_entry(&nvec->tx_data, struct nvec_msg, 560 node); 561 nvec->tx->pos = 0; 562 } 563 spin_unlock(&nvec->tx_lock); 564 565 dev_dbg(nvec->dev, "Sending message of length %u, command 0x%x\n", 566 (uint)nvec->tx->size, nvec->tx->data[1]); 567 } 568 569 /** 570 * nvec_interrupt - Interrupt handler 571 * @irq: The IRQ 572 * @dev: The nvec device 573 * 574 * Interrupt handler that fills our RX buffers and empties our TX 575 * buffers. This uses a finite state machine with ridiculous amounts 576 * of error checking, in order to be fairly reliable. 577 */ 578 static irqreturn_t nvec_interrupt(int irq, void *dev) 579 { 580 unsigned long status; 581 unsigned int received = 0; 582 unsigned char to_send = 0xff; 583 const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW; 584 struct nvec_chip *nvec = dev; 585 unsigned int state = nvec->state; 586 587 status = readl(nvec->base + I2C_SL_STATUS); 588 589 /* Filter out some errors */ 590 if ((status & irq_mask) == 0 && (status & ~irq_mask) != 0) { 591 dev_err(nvec->dev, "unexpected irq mask %lx\n", status); 592 return IRQ_HANDLED; 593 } 594 if ((status & I2C_SL_IRQ) == 0) { 595 dev_err(nvec->dev, "Spurious IRQ\n"); 596 return IRQ_HANDLED; 597 } 598 599 /* The EC did not request a read, so it send us something, read it */ 600 if ((status & RNW) == 0) { 601 received = readl(nvec->base + I2C_SL_RCVD); 602 if (status & RCVD) 603 writel(0, nvec->base + I2C_SL_RCVD); 604 } 605 606 if (status == (I2C_SL_IRQ | RCVD)) 607 nvec->state = 0; 608 609 switch (nvec->state) { 610 case 0: /* Verify that its a transfer start, the rest later */ 611 if (status != (I2C_SL_IRQ | RCVD)) 612 nvec_invalid_flags(nvec, status, false); 613 break; 614 case 1: /* command byte */ 615 if (status != I2C_SL_IRQ) { 616 nvec_invalid_flags(nvec, status, true); 617 } else { 618 nvec->rx = nvec_msg_alloc(nvec, NVEC_MSG_RX); 619 /* Should not happen in a normal world */ 620 if (unlikely(nvec->rx == NULL)) { 621 nvec->state = 0; 622 break; 623 } 624 nvec->rx->data[0] = received; 625 nvec->rx->pos = 1; 626 nvec->state = 2; 627 } 628 break; 629 case 2: /* first byte after command */ 630 if (status == (I2C_SL_IRQ | RNW | RCVD)) { 631 udelay(33); 632 if (nvec->rx->data[0] != 0x01) { 633 dev_err(nvec->dev, 634 "Read without prior read command\n"); 635 nvec->state = 0; 636 break; 637 } 638 nvec_msg_free(nvec, nvec->rx); 639 nvec->state = 3; 640 nvec_tx_set(nvec); 641 BUG_ON(nvec->tx->size < 1); 642 to_send = nvec->tx->data[0]; 643 nvec->tx->pos = 1; 644 } else if (status == (I2C_SL_IRQ)) { 645 BUG_ON(nvec->rx == NULL); 646 nvec->rx->data[1] = received; 647 nvec->rx->pos = 2; 648 nvec->state = 4; 649 } else { 650 nvec_invalid_flags(nvec, status, true); 651 } 652 break; 653 case 3: /* EC does a block read, we transmit data */ 654 if (status & END_TRANS) { 655 nvec_tx_completed(nvec); 656 } else if ((status & RNW) == 0 || (status & RCVD)) { 657 nvec_invalid_flags(nvec, status, true); 658 } else if (nvec->tx && nvec->tx->pos < nvec->tx->size) { 659 to_send = nvec->tx->data[nvec->tx->pos++]; 660 } else { 661 dev_err(nvec->dev, "tx buffer underflow on %p (%u > %u)\n", 662 nvec->tx, 663 (uint) (nvec->tx ? nvec->tx->pos : 0), 664 (uint) (nvec->tx ? nvec->tx->size : 0)); 665 nvec->state = 0; 666 } 667 break; 668 case 4: /* EC does some write, we read the data */ 669 if ((status & (END_TRANS | RNW)) == END_TRANS) 670 nvec_rx_completed(nvec); 671 else if (status & (RNW | RCVD)) 672 nvec_invalid_flags(nvec, status, true); 673 else if (nvec->rx && nvec->rx->pos < NVEC_MSG_SIZE) 674 nvec->rx->data[nvec->rx->pos++] = received; 675 else 676 dev_err(nvec->dev, 677 "RX buffer overflow on %p: Trying to write byte %u of %u\n", 678 nvec->rx, nvec->rx ? nvec->rx->pos : 0, 679 NVEC_MSG_SIZE); 680 break; 681 default: 682 nvec->state = 0; 683 } 684 685 /* If we are told that a new transfer starts, verify it */ 686 if ((status & (RCVD | RNW)) == RCVD) { 687 if (received != nvec->i2c_addr) 688 dev_err(nvec->dev, 689 "received address 0x%02x, expected 0x%02x\n", 690 received, nvec->i2c_addr); 691 nvec->state = 1; 692 } 693 694 /* Send data if requested, but not on end of transmission */ 695 if ((status & (RNW | END_TRANS)) == RNW) 696 writel(to_send, nvec->base + I2C_SL_RCVD); 697 698 /* If we have send the first byte */ 699 if (status == (I2C_SL_IRQ | RNW | RCVD)) 700 nvec_gpio_set_value(nvec, 1); 701 702 dev_dbg(nvec->dev, 703 "Handled: %s 0x%02x, %s 0x%02x in state %u [%s%s%s]\n", 704 (status & RNW) == 0 ? "received" : "R=", 705 received, 706 (status & (RNW | END_TRANS)) ? "sent" : "S=", 707 to_send, 708 state, 709 status & END_TRANS ? " END_TRANS" : "", 710 status & RCVD ? " RCVD" : "", 711 status & RNW ? " RNW" : ""); 712 713 /* 714 * TODO: A correct fix needs to be found for this. 715 * 716 * We experience less incomplete messages with this delay than without 717 * it, but we don't know why. Help is appreciated. 718 */ 719 udelay(100); 720 721 return IRQ_HANDLED; 722 } 723 724 static void tegra_init_i2c_slave(struct nvec_chip *nvec) 725 { 726 u32 val; 727 728 clk_prepare_enable(nvec->i2c_clk); 729 730 reset_control_assert(nvec->rst); 731 udelay(2); 732 reset_control_deassert(nvec->rst); 733 734 val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN | 735 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 736 writel(val, nvec->base + I2C_CNFG); 737 738 clk_set_rate(nvec->i2c_clk, 8 * 80000); 739 740 writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG); 741 writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT); 742 743 writel(nvec->i2c_addr >> 1, nvec->base + I2C_SL_ADDR1); 744 writel(0, nvec->base + I2C_SL_ADDR2); 745 746 enable_irq(nvec->irq); 747 } 748 749 #ifdef CONFIG_PM_SLEEP 750 static void nvec_disable_i2c_slave(struct nvec_chip *nvec) 751 { 752 disable_irq(nvec->irq); 753 writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG); 754 clk_disable_unprepare(nvec->i2c_clk); 755 } 756 #endif 757 758 static void nvec_power_off(void) 759 { 760 char ap_pwr_down[] = { NVEC_SLEEP, AP_PWR_DOWN }; 761 762 nvec_toggle_global_events(nvec_power_handle, false); 763 nvec_write_async(nvec_power_handle, ap_pwr_down, 2); 764 } 765 766 /* 767 * Parse common device tree data 768 */ 769 static int nvec_i2c_parse_dt_pdata(struct nvec_chip *nvec) 770 { 771 nvec->gpio = of_get_named_gpio(nvec->dev->of_node, "request-gpios", 0); 772 773 if (nvec->gpio < 0) { 774 dev_err(nvec->dev, "no gpio specified"); 775 return -ENODEV; 776 } 777 778 if (of_property_read_u32(nvec->dev->of_node, "slave-addr", 779 &nvec->i2c_addr)) { 780 dev_err(nvec->dev, "no i2c address specified"); 781 return -ENODEV; 782 } 783 784 return 0; 785 } 786 787 static int tegra_nvec_probe(struct platform_device *pdev) 788 { 789 int err, ret; 790 struct clk *i2c_clk; 791 struct nvec_chip *nvec; 792 struct nvec_msg *msg; 793 struct resource *res; 794 void __iomem *base; 795 char get_firmware_version[] = { NVEC_CNTL, GET_FIRMWARE_VERSION }, 796 unmute_speakers[] = { NVEC_OEM0, 0x10, 0x59, 0x95 }, 797 enable_event[7] = { NVEC_SYS, CNF_EVENT_REPORTING, true }; 798 799 if (!pdev->dev.of_node) { 800 dev_err(&pdev->dev, "must be instantiated using device tree\n"); 801 return -ENODEV; 802 } 803 804 nvec = devm_kzalloc(&pdev->dev, sizeof(struct nvec_chip), GFP_KERNEL); 805 if (!nvec) 806 return -ENOMEM; 807 808 platform_set_drvdata(pdev, nvec); 809 nvec->dev = &pdev->dev; 810 811 err = nvec_i2c_parse_dt_pdata(nvec); 812 if (err < 0) 813 return err; 814 815 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 816 base = devm_ioremap_resource(&pdev->dev, res); 817 if (IS_ERR(base)) 818 return PTR_ERR(base); 819 820 nvec->irq = platform_get_irq(pdev, 0); 821 if (nvec->irq < 0) { 822 dev_err(&pdev->dev, "no irq resource?\n"); 823 return -ENODEV; 824 } 825 826 i2c_clk = devm_clk_get(&pdev->dev, "div-clk"); 827 if (IS_ERR(i2c_clk)) { 828 dev_err(nvec->dev, "failed to get controller clock\n"); 829 return -ENODEV; 830 } 831 832 nvec->rst = devm_reset_control_get(&pdev->dev, "i2c"); 833 if (IS_ERR(nvec->rst)) { 834 dev_err(nvec->dev, "failed to get controller reset\n"); 835 return PTR_ERR(nvec->rst); 836 } 837 838 nvec->base = base; 839 nvec->i2c_clk = i2c_clk; 840 nvec->rx = &nvec->msg_pool[0]; 841 842 ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list); 843 844 init_completion(&nvec->sync_write); 845 init_completion(&nvec->ec_transfer); 846 mutex_init(&nvec->sync_write_mutex); 847 spin_lock_init(&nvec->tx_lock); 848 spin_lock_init(&nvec->rx_lock); 849 INIT_LIST_HEAD(&nvec->rx_data); 850 INIT_LIST_HEAD(&nvec->tx_data); 851 INIT_WORK(&nvec->rx_work, nvec_dispatch); 852 INIT_WORK(&nvec->tx_work, nvec_request_master); 853 854 err = devm_gpio_request_one(&pdev->dev, nvec->gpio, GPIOF_OUT_INIT_HIGH, 855 "nvec gpio"); 856 if (err < 0) { 857 dev_err(nvec->dev, "couldn't request gpio\n"); 858 return -ENODEV; 859 } 860 861 err = devm_request_irq(&pdev->dev, nvec->irq, nvec_interrupt, 0, 862 "nvec", nvec); 863 if (err) { 864 dev_err(nvec->dev, "couldn't request irq\n"); 865 return -ENODEV; 866 } 867 disable_irq(nvec->irq); 868 869 tegra_init_i2c_slave(nvec); 870 871 /* enable event reporting */ 872 nvec_toggle_global_events(nvec, true); 873 874 nvec->nvec_status_notifier.notifier_call = nvec_status_notifier; 875 nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0); 876 877 nvec_power_handle = nvec; 878 pm_power_off = nvec_power_off; 879 880 /* Get Firmware Version */ 881 msg = nvec_write_sync(nvec, get_firmware_version, 2); 882 883 if (msg) { 884 dev_warn(nvec->dev, "ec firmware version %02x.%02x.%02x / %02x\n", 885 msg->data[4], msg->data[5], msg->data[6], msg->data[7]); 886 887 nvec_msg_free(nvec, msg); 888 } 889 890 ret = mfd_add_devices(nvec->dev, 0, nvec_devices, 891 ARRAY_SIZE(nvec_devices), NULL, 0, NULL); 892 if (ret) 893 dev_err(nvec->dev, "error adding subdevices\n"); 894 895 /* unmute speakers? */ 896 nvec_write_async(nvec, unmute_speakers, 4); 897 898 /* enable lid switch event */ 899 nvec_event_mask(enable_event, LID_SWITCH); 900 nvec_write_async(nvec, enable_event, 7); 901 902 /* enable power button event */ 903 nvec_event_mask(enable_event, PWR_BUTTON); 904 nvec_write_async(nvec, enable_event, 7); 905 906 return 0; 907 } 908 909 static int tegra_nvec_remove(struct platform_device *pdev) 910 { 911 struct nvec_chip *nvec = platform_get_drvdata(pdev); 912 913 nvec_toggle_global_events(nvec, false); 914 mfd_remove_devices(nvec->dev); 915 nvec_unregister_notifier(nvec, &nvec->nvec_status_notifier); 916 cancel_work_sync(&nvec->rx_work); 917 cancel_work_sync(&nvec->tx_work); 918 /* FIXME: needs check whether nvec is responsible for power off */ 919 pm_power_off = NULL; 920 921 return 0; 922 } 923 924 #ifdef CONFIG_PM_SLEEP 925 static int nvec_suspend(struct device *dev) 926 { 927 struct platform_device *pdev = to_platform_device(dev); 928 struct nvec_chip *nvec = platform_get_drvdata(pdev); 929 struct nvec_msg *msg; 930 char ap_suspend[] = { NVEC_SLEEP, AP_SUSPEND }; 931 932 dev_dbg(nvec->dev, "suspending\n"); 933 934 /* keep these sync or you'll break suspend */ 935 nvec_toggle_global_events(nvec, false); 936 937 msg = nvec_write_sync(nvec, ap_suspend, sizeof(ap_suspend)); 938 nvec_msg_free(nvec, msg); 939 940 nvec_disable_i2c_slave(nvec); 941 942 return 0; 943 } 944 945 static int nvec_resume(struct device *dev) 946 { 947 struct platform_device *pdev = to_platform_device(dev); 948 struct nvec_chip *nvec = platform_get_drvdata(pdev); 949 950 dev_dbg(nvec->dev, "resuming\n"); 951 tegra_init_i2c_slave(nvec); 952 nvec_toggle_global_events(nvec, true); 953 954 return 0; 955 } 956 #endif 957 958 static SIMPLE_DEV_PM_OPS(nvec_pm_ops, nvec_suspend, nvec_resume); 959 960 /* Match table for of_platform binding */ 961 static const struct of_device_id nvidia_nvec_of_match[] = { 962 { .compatible = "nvidia,nvec", }, 963 {}, 964 }; 965 MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match); 966 967 static struct platform_driver nvec_device_driver = { 968 .probe = tegra_nvec_probe, 969 .remove = tegra_nvec_remove, 970 .driver = { 971 .name = "nvec", 972 .pm = &nvec_pm_ops, 973 .of_match_table = nvidia_nvec_of_match, 974 } 975 }; 976 977 module_platform_driver(nvec_device_driver); 978 979 MODULE_ALIAS("platform:nvec"); 980 MODULE_DESCRIPTION("NVIDIA compliant embedded controller interface"); 981 MODULE_AUTHOR("Marc Dietrich <marvin24@gmx.de>"); 982 MODULE_LICENSE("GPL"); 983