1 /* 2 * NVEC: NVIDIA compliant embedded controller interface 3 * 4 * Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net> 5 * 6 * Authors: Pierre-Hugues Husson <phhusson@free.fr> 7 * Ilya Petrov <ilya.muromec@gmail.com> 8 * Marc Dietrich <marvin24@gmx.de> 9 * Julian Andres Klode <jak@jak-linux.org> 10 * 11 * This file is subject to the terms and conditions of the GNU General Public 12 * License. See the file "COPYING" in the main directory of this archive 13 * for more details. 14 * 15 */ 16 17 /* #define DEBUG */ 18 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/atomic.h> 22 #include <linux/clk.h> 23 #include <linux/completion.h> 24 #include <linux/delay.h> 25 #include <linux/err.h> 26 #include <linux/gpio.h> 27 #include <linux/interrupt.h> 28 #include <linux/io.h> 29 #include <linux/irq.h> 30 #include <linux/of.h> 31 #include <linux/of_gpio.h> 32 #include <linux/list.h> 33 #include <linux/mfd/core.h> 34 #include <linux/mutex.h> 35 #include <linux/notifier.h> 36 #include <linux/platform_device.h> 37 #include <linux/slab.h> 38 #include <linux/spinlock.h> 39 #include <linux/workqueue.h> 40 #include <linux/clk/tegra.h> 41 42 #include "nvec.h" 43 44 #define I2C_CNFG 0x00 45 #define I2C_CNFG_PACKET_MODE_EN (1<<10) 46 #define I2C_CNFG_NEW_MASTER_SFM (1<<11) 47 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12 48 49 #define I2C_SL_CNFG 0x20 50 #define I2C_SL_NEWSL (1<<2) 51 #define I2C_SL_NACK (1<<1) 52 #define I2C_SL_RESP (1<<0) 53 #define I2C_SL_IRQ (1<<3) 54 #define END_TRANS (1<<4) 55 #define RCVD (1<<2) 56 #define RNW (1<<1) 57 58 #define I2C_SL_RCVD 0x24 59 #define I2C_SL_STATUS 0x28 60 #define I2C_SL_ADDR1 0x2c 61 #define I2C_SL_ADDR2 0x30 62 #define I2C_SL_DELAY_COUNT 0x3c 63 64 /** 65 * enum nvec_msg_category - Message categories for nvec_msg_alloc() 66 * @NVEC_MSG_RX: The message is an incoming message (from EC) 67 * @NVEC_MSG_TX: The message is an outgoing message (to EC) 68 */ 69 enum nvec_msg_category { 70 NVEC_MSG_RX, 71 NVEC_MSG_TX, 72 }; 73 74 static const unsigned char EC_DISABLE_EVENT_REPORTING[3] = "\x04\x00\x00"; 75 static const unsigned char EC_ENABLE_EVENT_REPORTING[3] = "\x04\x00\x01"; 76 static const unsigned char EC_GET_FIRMWARE_VERSION[2] = "\x07\x15"; 77 78 static struct nvec_chip *nvec_power_handle; 79 80 static struct mfd_cell nvec_devices[] = { 81 { 82 .name = "nvec-kbd", 83 .id = 1, 84 }, 85 { 86 .name = "nvec-mouse", 87 .id = 1, 88 }, 89 { 90 .name = "nvec-power", 91 .id = 1, 92 }, 93 { 94 .name = "nvec-power", 95 .id = 2, 96 }, 97 { 98 .name = "nvec-paz00", 99 .id = 1, 100 }, 101 }; 102 103 /** 104 * nvec_register_notifier - Register a notifier with nvec 105 * @nvec: A &struct nvec_chip 106 * @nb: The notifier block to register 107 * 108 * Registers a notifier with @nvec. The notifier will be added to an atomic 109 * notifier chain that is called for all received messages except those that 110 * correspond to a request initiated by nvec_write_sync(). 111 */ 112 int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb, 113 unsigned int events) 114 { 115 return atomic_notifier_chain_register(&nvec->notifier_list, nb); 116 } 117 EXPORT_SYMBOL_GPL(nvec_register_notifier); 118 119 /** 120 * nvec_status_notifier - The final notifier 121 * 122 * Prints a message about control events not handled in the notifier 123 * chain. 124 */ 125 static int nvec_status_notifier(struct notifier_block *nb, 126 unsigned long event_type, void *data) 127 { 128 struct nvec_chip *nvec = container_of(nb, struct nvec_chip, 129 nvec_status_notifier); 130 unsigned char *msg = (unsigned char *)data; 131 132 if (event_type != NVEC_CNTL) 133 return NOTIFY_DONE; 134 135 dev_warn(nvec->dev, "unhandled msg type %ld\n", event_type); 136 print_hex_dump(KERN_WARNING, "payload: ", DUMP_PREFIX_NONE, 16, 1, 137 msg, msg[1] + 2, true); 138 139 return NOTIFY_OK; 140 } 141 142 /** 143 * nvec_msg_alloc: 144 * @nvec: A &struct nvec_chip 145 * @category: Pool category, see &enum nvec_msg_category 146 * 147 * Allocate a single &struct nvec_msg object from the message pool of 148 * @nvec. The result shall be passed to nvec_msg_free() if no longer 149 * used. 150 * 151 * Outgoing messages are placed in the upper 75% of the pool, keeping the 152 * lower 25% available for RX buffers only. The reason is to prevent a 153 * situation where all buffers are full and a message is thus endlessly 154 * retried because the response could never be processed. 155 */ 156 static struct nvec_msg *nvec_msg_alloc(struct nvec_chip *nvec, 157 enum nvec_msg_category category) 158 { 159 int i = (category == NVEC_MSG_TX) ? (NVEC_POOL_SIZE / 4) : 0; 160 161 for (; i < NVEC_POOL_SIZE; i++) { 162 if (atomic_xchg(&nvec->msg_pool[i].used, 1) == 0) { 163 dev_vdbg(nvec->dev, "INFO: Allocate %i\n", i); 164 return &nvec->msg_pool[i]; 165 } 166 } 167 168 dev_err(nvec->dev, "could not allocate %s buffer\n", 169 (category == NVEC_MSG_TX) ? "TX" : "RX"); 170 171 return NULL; 172 } 173 174 /** 175 * nvec_msg_free: 176 * @nvec: A &struct nvec_chip 177 * @msg: A message (must be allocated by nvec_msg_alloc() and belong to @nvec) 178 * 179 * Free the given message 180 */ 181 inline void nvec_msg_free(struct nvec_chip *nvec, struct nvec_msg *msg) 182 { 183 if (msg != &nvec->tx_scratch) 184 dev_vdbg(nvec->dev, "INFO: Free %ti\n", msg - nvec->msg_pool); 185 atomic_set(&msg->used, 0); 186 } 187 EXPORT_SYMBOL_GPL(nvec_msg_free); 188 189 /** 190 * nvec_msg_is_event - Return %true if @msg is an event 191 * @msg: A message 192 */ 193 static bool nvec_msg_is_event(struct nvec_msg *msg) 194 { 195 return msg->data[0] >> 7; 196 } 197 198 /** 199 * nvec_msg_size - Get the size of a message 200 * @msg: The message to get the size for 201 * 202 * This only works for received messages, not for outgoing messages. 203 */ 204 static size_t nvec_msg_size(struct nvec_msg *msg) 205 { 206 bool is_event = nvec_msg_is_event(msg); 207 int event_length = (msg->data[0] & 0x60) >> 5; 208 209 /* for variable size, payload size in byte 1 + count (1) + cmd (1) */ 210 if (!is_event || event_length == NVEC_VAR_SIZE) 211 return (msg->pos || msg->size) ? (msg->data[1] + 2) : 0; 212 else if (event_length == NVEC_2BYTES) 213 return 2; 214 else if (event_length == NVEC_3BYTES) 215 return 3; 216 else 217 return 0; 218 } 219 220 /** 221 * nvec_gpio_set_value - Set the GPIO value 222 * @nvec: A &struct nvec_chip 223 * @value: The value to write (0 or 1) 224 * 225 * Like gpio_set_value(), but generating debugging information 226 */ 227 static void nvec_gpio_set_value(struct nvec_chip *nvec, int value) 228 { 229 dev_dbg(nvec->dev, "GPIO changed from %u to %u\n", 230 gpio_get_value(nvec->gpio), value); 231 gpio_set_value(nvec->gpio, value); 232 } 233 234 /** 235 * nvec_write_async - Asynchronously write a message to NVEC 236 * @nvec: An nvec_chip instance 237 * @data: The message data, starting with the request type 238 * @size: The size of @data 239 * 240 * Queue a single message to be transferred to the embedded controller 241 * and return immediately. 242 * 243 * Returns: 0 on success, a negative error code on failure. If a failure 244 * occured, the nvec driver may print an error. 245 */ 246 int nvec_write_async(struct nvec_chip *nvec, const unsigned char *data, 247 short size) 248 { 249 struct nvec_msg *msg; 250 unsigned long flags; 251 252 msg = nvec_msg_alloc(nvec, NVEC_MSG_TX); 253 254 if (msg == NULL) 255 return -ENOMEM; 256 257 msg->data[0] = size; 258 memcpy(msg->data + 1, data, size); 259 msg->size = size + 1; 260 261 spin_lock_irqsave(&nvec->tx_lock, flags); 262 list_add_tail(&msg->node, &nvec->tx_data); 263 spin_unlock_irqrestore(&nvec->tx_lock, flags); 264 265 schedule_work(&nvec->tx_work); 266 267 return 0; 268 } 269 EXPORT_SYMBOL(nvec_write_async); 270 271 /** 272 * nvec_write_sync - Write a message to nvec and read the response 273 * @nvec: An &struct nvec_chip 274 * @data: The data to write 275 * @size: The size of @data 276 * 277 * This is similar to nvec_write_async(), but waits for the 278 * request to be answered before returning. This function 279 * uses a mutex and can thus not be called from e.g. 280 * interrupt handlers. 281 * 282 * Returns: A pointer to the response message on success, 283 * %NULL on failure. Free with nvec_msg_free() once no longer 284 * used. 285 */ 286 struct nvec_msg *nvec_write_sync(struct nvec_chip *nvec, 287 const unsigned char *data, short size) 288 { 289 struct nvec_msg *msg; 290 291 mutex_lock(&nvec->sync_write_mutex); 292 293 nvec->sync_write_pending = (data[1] << 8) + data[0]; 294 295 if (nvec_write_async(nvec, data, size) < 0) { 296 mutex_unlock(&nvec->sync_write_mutex); 297 return NULL; 298 } 299 300 dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n", 301 nvec->sync_write_pending); 302 if (!(wait_for_completion_timeout(&nvec->sync_write, 303 msecs_to_jiffies(2000)))) { 304 dev_warn(nvec->dev, "timeout waiting for sync write to complete\n"); 305 mutex_unlock(&nvec->sync_write_mutex); 306 return NULL; 307 } 308 309 dev_dbg(nvec->dev, "nvec_sync_write: pong!\n"); 310 311 msg = nvec->last_sync_msg; 312 313 mutex_unlock(&nvec->sync_write_mutex); 314 315 return msg; 316 } 317 EXPORT_SYMBOL(nvec_write_sync); 318 319 /** 320 * nvec_request_master - Process outgoing messages 321 * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip) 322 * 323 * Processes all outgoing requests by sending the request and awaiting the 324 * response, then continuing with the next request. Once a request has a 325 * matching response, it will be freed and removed from the list. 326 */ 327 static void nvec_request_master(struct work_struct *work) 328 { 329 struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work); 330 unsigned long flags; 331 long err; 332 struct nvec_msg *msg; 333 334 spin_lock_irqsave(&nvec->tx_lock, flags); 335 while (!list_empty(&nvec->tx_data)) { 336 msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node); 337 spin_unlock_irqrestore(&nvec->tx_lock, flags); 338 nvec_gpio_set_value(nvec, 0); 339 err = wait_for_completion_interruptible_timeout( 340 &nvec->ec_transfer, msecs_to_jiffies(5000)); 341 342 if (err == 0) { 343 dev_warn(nvec->dev, "timeout waiting for ec transfer\n"); 344 nvec_gpio_set_value(nvec, 1); 345 msg->pos = 0; 346 } 347 348 spin_lock_irqsave(&nvec->tx_lock, flags); 349 350 if (err > 0) { 351 list_del_init(&msg->node); 352 nvec_msg_free(nvec, msg); 353 } 354 } 355 spin_unlock_irqrestore(&nvec->tx_lock, flags); 356 } 357 358 /** 359 * parse_msg - Print some information and call the notifiers on an RX message 360 * @nvec: A &struct nvec_chip 361 * @msg: A message received by @nvec 362 * 363 * Paarse some pieces of the message and then call the chain of notifiers 364 * registered via nvec_register_notifier. 365 */ 366 static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg) 367 { 368 if ((msg->data[0] & 1 << 7) == 0 && msg->data[3]) { 369 dev_err(nvec->dev, "ec responded %*ph\n", 4, msg->data); 370 return -EINVAL; 371 } 372 373 if ((msg->data[0] >> 7) == 1 && (msg->data[0] & 0x0f) == 5) 374 print_hex_dump(KERN_WARNING, "ec system event ", 375 DUMP_PREFIX_NONE, 16, 1, msg->data, 376 msg->data[1] + 2, true); 377 378 atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f, 379 msg->data); 380 381 return 0; 382 } 383 384 /** 385 * nvec_dispatch - Process messages received from the EC 386 * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip) 387 * 388 * Process messages previously received from the EC and put into the RX 389 * queue of the &struct nvec_chip instance associated with @work. 390 */ 391 static void nvec_dispatch(struct work_struct *work) 392 { 393 struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work); 394 unsigned long flags; 395 struct nvec_msg *msg; 396 397 spin_lock_irqsave(&nvec->rx_lock, flags); 398 while (!list_empty(&nvec->rx_data)) { 399 msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node); 400 list_del_init(&msg->node); 401 spin_unlock_irqrestore(&nvec->rx_lock, flags); 402 403 if (nvec->sync_write_pending == 404 (msg->data[2] << 8) + msg->data[0]) { 405 dev_dbg(nvec->dev, "sync write completed!\n"); 406 nvec->sync_write_pending = 0; 407 nvec->last_sync_msg = msg; 408 complete(&nvec->sync_write); 409 } else { 410 parse_msg(nvec, msg); 411 nvec_msg_free(nvec, msg); 412 } 413 spin_lock_irqsave(&nvec->rx_lock, flags); 414 } 415 spin_unlock_irqrestore(&nvec->rx_lock, flags); 416 } 417 418 /** 419 * nvec_tx_completed - Complete the current transfer 420 * @nvec: A &struct nvec_chip 421 * 422 * This is called when we have received an END_TRANS on a TX transfer. 423 */ 424 static void nvec_tx_completed(struct nvec_chip *nvec) 425 { 426 /* We got an END_TRANS, let's skip this, maybe there's an event */ 427 if (nvec->tx->pos != nvec->tx->size) { 428 dev_err(nvec->dev, "premature END_TRANS, resending\n"); 429 nvec->tx->pos = 0; 430 nvec_gpio_set_value(nvec, 0); 431 } else { 432 nvec->state = 0; 433 } 434 } 435 436 /** 437 * nvec_rx_completed - Complete the current transfer 438 * @nvec: A &struct nvec_chip 439 * 440 * This is called when we have received an END_TRANS on a RX transfer. 441 */ 442 static void nvec_rx_completed(struct nvec_chip *nvec) 443 { 444 if (nvec->rx->pos != nvec_msg_size(nvec->rx)) { 445 dev_err(nvec->dev, "RX incomplete: Expected %u bytes, got %u\n", 446 (uint) nvec_msg_size(nvec->rx), 447 (uint) nvec->rx->pos); 448 449 nvec_msg_free(nvec, nvec->rx); 450 nvec->state = 0; 451 452 /* Battery quirk - Often incomplete, and likes to crash */ 453 if (nvec->rx->data[0] == NVEC_BAT) 454 complete(&nvec->ec_transfer); 455 456 return; 457 } 458 459 spin_lock(&nvec->rx_lock); 460 461 /* add the received data to the work list 462 and move the ring buffer pointer to the next entry */ 463 list_add_tail(&nvec->rx->node, &nvec->rx_data); 464 465 spin_unlock(&nvec->rx_lock); 466 467 nvec->state = 0; 468 469 if (!nvec_msg_is_event(nvec->rx)) 470 complete(&nvec->ec_transfer); 471 472 schedule_work(&nvec->rx_work); 473 } 474 475 /** 476 * nvec_invalid_flags - Send an error message about invalid flags and jump 477 * @nvec: The nvec device 478 * @status: The status flags 479 * @reset: Whether we shall jump to state 0. 480 */ 481 static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status, 482 bool reset) 483 { 484 dev_err(nvec->dev, "unexpected status flags 0x%02x during state %i\n", 485 status, nvec->state); 486 if (reset) 487 nvec->state = 0; 488 } 489 490 /** 491 * nvec_tx_set - Set the message to transfer (nvec->tx) 492 * @nvec: A &struct nvec_chip 493 * 494 * Gets the first entry from the tx_data list of @nvec and sets the 495 * tx member to it. If the tx_data list is empty, this uses the 496 * tx_scratch message to send a no operation message. 497 */ 498 static void nvec_tx_set(struct nvec_chip *nvec) 499 { 500 spin_lock(&nvec->tx_lock); 501 if (list_empty(&nvec->tx_data)) { 502 dev_err(nvec->dev, "empty tx - sending no-op\n"); 503 memcpy(nvec->tx_scratch.data, "\x02\x07\x02", 3); 504 nvec->tx_scratch.size = 3; 505 nvec->tx_scratch.pos = 0; 506 nvec->tx = &nvec->tx_scratch; 507 list_add_tail(&nvec->tx->node, &nvec->tx_data); 508 } else { 509 nvec->tx = list_first_entry(&nvec->tx_data, struct nvec_msg, 510 node); 511 nvec->tx->pos = 0; 512 } 513 spin_unlock(&nvec->tx_lock); 514 515 dev_dbg(nvec->dev, "Sending message of length %u, command 0x%x\n", 516 (uint)nvec->tx->size, nvec->tx->data[1]); 517 } 518 519 /** 520 * nvec_interrupt - Interrupt handler 521 * @irq: The IRQ 522 * @dev: The nvec device 523 * 524 * Interrupt handler that fills our RX buffers and empties our TX 525 * buffers. This uses a finite state machine with ridiculous amounts 526 * of error checking, in order to be fairly reliable. 527 */ 528 static irqreturn_t nvec_interrupt(int irq, void *dev) 529 { 530 unsigned long status; 531 unsigned int received = 0; 532 unsigned char to_send = 0xff; 533 const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW; 534 struct nvec_chip *nvec = dev; 535 unsigned int state = nvec->state; 536 537 status = readl(nvec->base + I2C_SL_STATUS); 538 539 /* Filter out some errors */ 540 if ((status & irq_mask) == 0 && (status & ~irq_mask) != 0) { 541 dev_err(nvec->dev, "unexpected irq mask %lx\n", status); 542 return IRQ_HANDLED; 543 } 544 if ((status & I2C_SL_IRQ) == 0) { 545 dev_err(nvec->dev, "Spurious IRQ\n"); 546 return IRQ_HANDLED; 547 } 548 549 /* The EC did not request a read, so it send us something, read it */ 550 if ((status & RNW) == 0) { 551 received = readl(nvec->base + I2C_SL_RCVD); 552 if (status & RCVD) 553 writel(0, nvec->base + I2C_SL_RCVD); 554 } 555 556 if (status == (I2C_SL_IRQ | RCVD)) 557 nvec->state = 0; 558 559 switch (nvec->state) { 560 case 0: /* Verify that its a transfer start, the rest later */ 561 if (status != (I2C_SL_IRQ | RCVD)) 562 nvec_invalid_flags(nvec, status, false); 563 break; 564 case 1: /* command byte */ 565 if (status != I2C_SL_IRQ) { 566 nvec_invalid_flags(nvec, status, true); 567 } else { 568 nvec->rx = nvec_msg_alloc(nvec, NVEC_MSG_RX); 569 /* Should not happen in a normal world */ 570 if (unlikely(nvec->rx == NULL)) { 571 nvec->state = 0; 572 break; 573 } 574 nvec->rx->data[0] = received; 575 nvec->rx->pos = 1; 576 nvec->state = 2; 577 } 578 break; 579 case 2: /* first byte after command */ 580 if (status == (I2C_SL_IRQ | RNW | RCVD)) { 581 udelay(33); 582 if (nvec->rx->data[0] != 0x01) { 583 dev_err(nvec->dev, 584 "Read without prior read command\n"); 585 nvec->state = 0; 586 break; 587 } 588 nvec_msg_free(nvec, nvec->rx); 589 nvec->state = 3; 590 nvec_tx_set(nvec); 591 BUG_ON(nvec->tx->size < 1); 592 to_send = nvec->tx->data[0]; 593 nvec->tx->pos = 1; 594 } else if (status == (I2C_SL_IRQ)) { 595 BUG_ON(nvec->rx == NULL); 596 nvec->rx->data[1] = received; 597 nvec->rx->pos = 2; 598 nvec->state = 4; 599 } else { 600 nvec_invalid_flags(nvec, status, true); 601 } 602 break; 603 case 3: /* EC does a block read, we transmit data */ 604 if (status & END_TRANS) { 605 nvec_tx_completed(nvec); 606 } else if ((status & RNW) == 0 || (status & RCVD)) { 607 nvec_invalid_flags(nvec, status, true); 608 } else if (nvec->tx && nvec->tx->pos < nvec->tx->size) { 609 to_send = nvec->tx->data[nvec->tx->pos++]; 610 } else { 611 dev_err(nvec->dev, "tx buffer underflow on %p (%u > %u)\n", 612 nvec->tx, 613 (uint) (nvec->tx ? nvec->tx->pos : 0), 614 (uint) (nvec->tx ? nvec->tx->size : 0)); 615 nvec->state = 0; 616 } 617 break; 618 case 4: /* EC does some write, we read the data */ 619 if ((status & (END_TRANS | RNW)) == END_TRANS) 620 nvec_rx_completed(nvec); 621 else if (status & (RNW | RCVD)) 622 nvec_invalid_flags(nvec, status, true); 623 else if (nvec->rx && nvec->rx->pos < NVEC_MSG_SIZE) 624 nvec->rx->data[nvec->rx->pos++] = received; 625 else 626 dev_err(nvec->dev, 627 "RX buffer overflow on %p: " 628 "Trying to write byte %u of %u\n", 629 nvec->rx, nvec->rx->pos, NVEC_MSG_SIZE); 630 break; 631 default: 632 nvec->state = 0; 633 } 634 635 /* If we are told that a new transfer starts, verify it */ 636 if ((status & (RCVD | RNW)) == RCVD) { 637 if (received != nvec->i2c_addr) 638 dev_err(nvec->dev, 639 "received address 0x%02x, expected 0x%02x\n", 640 received, nvec->i2c_addr); 641 nvec->state = 1; 642 } 643 644 /* Send data if requested, but not on end of transmission */ 645 if ((status & (RNW | END_TRANS)) == RNW) 646 writel(to_send, nvec->base + I2C_SL_RCVD); 647 648 /* If we have send the first byte */ 649 if (status == (I2C_SL_IRQ | RNW | RCVD)) 650 nvec_gpio_set_value(nvec, 1); 651 652 dev_dbg(nvec->dev, 653 "Handled: %s 0x%02x, %s 0x%02x in state %u [%s%s%s]\n", 654 (status & RNW) == 0 ? "received" : "R=", 655 received, 656 (status & (RNW | END_TRANS)) ? "sent" : "S=", 657 to_send, 658 state, 659 status & END_TRANS ? " END_TRANS" : "", 660 status & RCVD ? " RCVD" : "", 661 status & RNW ? " RNW" : ""); 662 663 664 /* 665 * TODO: A correct fix needs to be found for this. 666 * 667 * We experience less incomplete messages with this delay than without 668 * it, but we don't know why. Help is appreciated. 669 */ 670 udelay(100); 671 672 return IRQ_HANDLED; 673 } 674 675 static void tegra_init_i2c_slave(struct nvec_chip *nvec) 676 { 677 u32 val; 678 679 clk_prepare_enable(nvec->i2c_clk); 680 681 tegra_periph_reset_assert(nvec->i2c_clk); 682 udelay(2); 683 tegra_periph_reset_deassert(nvec->i2c_clk); 684 685 val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN | 686 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT); 687 writel(val, nvec->base + I2C_CNFG); 688 689 clk_set_rate(nvec->i2c_clk, 8 * 80000); 690 691 writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG); 692 writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT); 693 694 writel(nvec->i2c_addr>>1, nvec->base + I2C_SL_ADDR1); 695 writel(0, nvec->base + I2C_SL_ADDR2); 696 697 enable_irq(nvec->irq); 698 699 clk_disable_unprepare(nvec->i2c_clk); 700 } 701 702 #ifdef CONFIG_PM_SLEEP 703 static void nvec_disable_i2c_slave(struct nvec_chip *nvec) 704 { 705 disable_irq(nvec->irq); 706 writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG); 707 clk_disable_unprepare(nvec->i2c_clk); 708 } 709 #endif 710 711 static void nvec_power_off(void) 712 { 713 nvec_write_async(nvec_power_handle, EC_DISABLE_EVENT_REPORTING, 3); 714 nvec_write_async(nvec_power_handle, "\x04\x01", 2); 715 } 716 717 static int tegra_nvec_probe(struct platform_device *pdev) 718 { 719 int err, ret; 720 struct clk *i2c_clk; 721 struct nvec_platform_data *pdata = pdev->dev.platform_data; 722 struct nvec_chip *nvec; 723 struct nvec_msg *msg; 724 struct resource *res; 725 void __iomem *base; 726 727 nvec = devm_kzalloc(&pdev->dev, sizeof(struct nvec_chip), GFP_KERNEL); 728 if (nvec == NULL) { 729 dev_err(&pdev->dev, "failed to reserve memory\n"); 730 return -ENOMEM; 731 } 732 platform_set_drvdata(pdev, nvec); 733 nvec->dev = &pdev->dev; 734 735 if (pdata) { 736 nvec->gpio = pdata->gpio; 737 nvec->i2c_addr = pdata->i2c_addr; 738 } else if (nvec->dev->of_node) { 739 nvec->gpio = of_get_named_gpio(nvec->dev->of_node, 740 "request-gpios", 0); 741 if (nvec->gpio < 0) { 742 dev_err(&pdev->dev, "no gpio specified"); 743 return -ENODEV; 744 } 745 if (of_property_read_u32(nvec->dev->of_node, 746 "slave-addr", &nvec->i2c_addr)) { 747 dev_err(&pdev->dev, "no i2c address specified"); 748 return -ENODEV; 749 } 750 } else { 751 dev_err(&pdev->dev, "no platform data\n"); 752 return -ENODEV; 753 } 754 755 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 756 if (!res) { 757 dev_err(&pdev->dev, "no mem resource?\n"); 758 return -ENODEV; 759 } 760 761 base = devm_request_and_ioremap(&pdev->dev, res); 762 if (!base) { 763 dev_err(&pdev->dev, "Can't ioremap I2C region\n"); 764 return -ENOMEM; 765 } 766 767 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 768 if (!res) { 769 dev_err(&pdev->dev, "no irq resource?\n"); 770 return -ENODEV; 771 } 772 773 i2c_clk = clk_get_sys("tegra-i2c.2", "div-clk"); 774 if (IS_ERR(i2c_clk)) { 775 dev_err(nvec->dev, "failed to get controller clock\n"); 776 return -ENODEV; 777 } 778 779 nvec->base = base; 780 nvec->irq = res->start; 781 nvec->i2c_clk = i2c_clk; 782 nvec->rx = &nvec->msg_pool[0]; 783 784 ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list); 785 786 init_completion(&nvec->sync_write); 787 init_completion(&nvec->ec_transfer); 788 mutex_init(&nvec->sync_write_mutex); 789 spin_lock_init(&nvec->tx_lock); 790 spin_lock_init(&nvec->rx_lock); 791 INIT_LIST_HEAD(&nvec->rx_data); 792 INIT_LIST_HEAD(&nvec->tx_data); 793 INIT_WORK(&nvec->rx_work, nvec_dispatch); 794 INIT_WORK(&nvec->tx_work, nvec_request_master); 795 796 err = devm_gpio_request_one(&pdev->dev, nvec->gpio, GPIOF_OUT_INIT_HIGH, 797 "nvec gpio"); 798 if (err < 0) { 799 dev_err(nvec->dev, "couldn't request gpio\n"); 800 return -ENODEV; 801 } 802 803 err = devm_request_irq(&pdev->dev, nvec->irq, nvec_interrupt, 0, 804 "nvec", nvec); 805 if (err) { 806 dev_err(nvec->dev, "couldn't request irq\n"); 807 return -ENODEV; 808 } 809 disable_irq(nvec->irq); 810 811 tegra_init_i2c_slave(nvec); 812 813 clk_prepare_enable(i2c_clk); 814 815 816 /* enable event reporting */ 817 nvec_write_async(nvec, EC_ENABLE_EVENT_REPORTING, 818 sizeof(EC_ENABLE_EVENT_REPORTING)); 819 820 nvec->nvec_status_notifier.notifier_call = nvec_status_notifier; 821 nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0); 822 823 nvec_power_handle = nvec; 824 pm_power_off = nvec_power_off; 825 826 /* Get Firmware Version */ 827 msg = nvec_write_sync(nvec, EC_GET_FIRMWARE_VERSION, 828 sizeof(EC_GET_FIRMWARE_VERSION)); 829 830 if (msg) { 831 dev_warn(nvec->dev, "ec firmware version %02x.%02x.%02x / %02x\n", 832 msg->data[4], msg->data[5], msg->data[6], msg->data[7]); 833 834 nvec_msg_free(nvec, msg); 835 } 836 837 ret = mfd_add_devices(nvec->dev, -1, nvec_devices, 838 ARRAY_SIZE(nvec_devices), base, 0, NULL); 839 if (ret) 840 dev_err(nvec->dev, "error adding subdevices\n"); 841 842 /* unmute speakers? */ 843 nvec_write_async(nvec, "\x0d\x10\x59\x95", 4); 844 845 /* enable lid switch event */ 846 nvec_write_async(nvec, "\x01\x01\x01\x00\x00\x02\x00", 7); 847 848 /* enable power button event */ 849 nvec_write_async(nvec, "\x01\x01\x01\x00\x00\x80\x00", 7); 850 851 return 0; 852 } 853 854 static int tegra_nvec_remove(struct platform_device *pdev) 855 { 856 struct nvec_chip *nvec = platform_get_drvdata(pdev); 857 858 nvec_write_async(nvec, EC_DISABLE_EVENT_REPORTING, 3); 859 mfd_remove_devices(nvec->dev); 860 cancel_work_sync(&nvec->rx_work); 861 cancel_work_sync(&nvec->tx_work); 862 863 return 0; 864 } 865 866 #ifdef CONFIG_PM_SLEEP 867 static int nvec_suspend(struct device *dev) 868 { 869 struct platform_device *pdev = to_platform_device(dev); 870 struct nvec_chip *nvec = platform_get_drvdata(pdev); 871 struct nvec_msg *msg; 872 873 dev_dbg(nvec->dev, "suspending\n"); 874 875 /* keep these sync or you'll break suspend */ 876 msg = nvec_write_sync(nvec, EC_DISABLE_EVENT_REPORTING, 3); 877 nvec_msg_free(nvec, msg); 878 msg = nvec_write_sync(nvec, "\x04\x02", 2); 879 nvec_msg_free(nvec, msg); 880 881 nvec_disable_i2c_slave(nvec); 882 883 return 0; 884 } 885 886 static int nvec_resume(struct device *dev) 887 { 888 struct platform_device *pdev = to_platform_device(dev); 889 struct nvec_chip *nvec = platform_get_drvdata(pdev); 890 891 dev_dbg(nvec->dev, "resuming\n"); 892 tegra_init_i2c_slave(nvec); 893 nvec_write_async(nvec, EC_ENABLE_EVENT_REPORTING, 3); 894 895 return 0; 896 } 897 #endif 898 899 static const SIMPLE_DEV_PM_OPS(nvec_pm_ops, nvec_suspend, nvec_resume); 900 901 /* Match table for of_platform binding */ 902 static const struct of_device_id nvidia_nvec_of_match[] = { 903 { .compatible = "nvidia,nvec", }, 904 {}, 905 }; 906 MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match); 907 908 static struct platform_driver nvec_device_driver = { 909 .probe = tegra_nvec_probe, 910 .remove = tegra_nvec_remove, 911 .driver = { 912 .name = "nvec", 913 .owner = THIS_MODULE, 914 .pm = &nvec_pm_ops, 915 .of_match_table = nvidia_nvec_of_match, 916 } 917 }; 918 919 module_platform_driver(nvec_device_driver); 920 921 MODULE_ALIAS("platform:nvec"); 922 MODULE_DESCRIPTION("NVIDIA compliant embedded controller interface"); 923 MODULE_AUTHOR("Marc Dietrich <marvin24@gmx.de>"); 924 MODULE_LICENSE("GPL"); 925