1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * dim2.c - MediaLB DIM2 Hardware Dependent Module 4 * 5 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/module.h> 11 #include <linux/of_platform.h> 12 #include <linux/printk.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/platform_device.h> 16 #include <linux/interrupt.h> 17 #include <linux/slab.h> 18 #include <linux/io.h> 19 #include <linux/clk.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/sched.h> 22 #include <linux/kthread.h> 23 24 #include "most/core.h" 25 #include "hal.h" 26 #include "errors.h" 27 #include "sysfs.h" 28 29 #define DMA_CHANNELS (32 - 1) /* channel 0 is a system channel */ 30 31 #define MAX_BUFFERS_PACKET 32 32 #define MAX_BUFFERS_STREAMING 32 33 #define MAX_BUF_SIZE_PACKET 2048 34 #define MAX_BUF_SIZE_STREAMING (8 * 1024) 35 36 /* 37 * The parameter representing the number of frames per sub-buffer for 38 * synchronous channels. Valid values: [0 .. 6]. 39 * 40 * The values 0, 1, 2, 3, 4, 5, 6 represent corresponding number of frames per 41 * sub-buffer 1, 2, 4, 8, 16, 32, 64. 42 */ 43 static u8 fcnt = 4; /* (1 << fcnt) frames per subbuffer */ 44 module_param(fcnt, byte, 0000); 45 MODULE_PARM_DESC(fcnt, "Num of frames per sub-buffer for sync channels as a power of 2"); 46 47 static DEFINE_SPINLOCK(dim_lock); 48 49 static void dim2_tasklet_fn(unsigned long data); 50 static DECLARE_TASKLET(dim2_tasklet, dim2_tasklet_fn, 0); 51 52 /** 53 * struct hdm_channel - private structure to keep channel specific data 54 * @is_initialized: identifier to know whether the channel is initialized 55 * @ch: HAL specific channel data 56 * @pending_list: list to keep MBO's before starting transfer 57 * @started_list: list to keep MBO's after starting transfer 58 * @direction: channel direction (TX or RX) 59 * @data_type: channel data type 60 */ 61 struct hdm_channel { 62 char name[sizeof "caNNN"]; 63 bool is_initialized; 64 struct dim_channel ch; 65 u16 *reset_dbr_size; 66 struct list_head pending_list; /* before dim_enqueue_buffer() */ 67 struct list_head started_list; /* after dim_enqueue_buffer() */ 68 enum most_channel_direction direction; 69 enum most_channel_data_type data_type; 70 }; 71 72 /** 73 * struct dim2_hdm - private structure to keep interface specific data 74 * @hch: an array of channel specific data 75 * @most_iface: most interface structure 76 * @capabilities: an array of channel capability data 77 * @io_base: I/O register base address 78 * @netinfo_task: thread to deliver network status 79 * @netinfo_waitq: waitq for the thread to sleep 80 * @deliver_netinfo: to identify whether network status received 81 * @mac_addrs: INIC mac address 82 * @link_state: network link state 83 * @atx_idx: index of async tx channel 84 */ 85 struct dim2_hdm { 86 struct device dev; 87 struct hdm_channel hch[DMA_CHANNELS]; 88 struct most_channel_capability capabilities[DMA_CHANNELS]; 89 struct most_interface most_iface; 90 char name[16 + sizeof "dim2-"]; 91 void __iomem *io_base; 92 u8 clk_speed; 93 struct clk *clk; 94 struct clk *clk_pll; 95 struct task_struct *netinfo_task; 96 wait_queue_head_t netinfo_waitq; 97 int deliver_netinfo; 98 unsigned char mac_addrs[6]; 99 unsigned char link_state; 100 int atx_idx; 101 struct medialb_bus bus; 102 void (*on_netinfo)(struct most_interface *most_iface, 103 unsigned char link_state, unsigned char *addrs); 104 void (*disable_platform)(struct platform_device *); 105 }; 106 107 struct dim2_platform_data { 108 int (*enable)(struct platform_device *); 109 void (*disable)(struct platform_device *); 110 }; 111 112 #define iface_to_hdm(iface) container_of(iface, struct dim2_hdm, most_iface) 113 114 /* Macro to identify a network status message */ 115 #define PACKET_IS_NET_INFO(p) \ 116 (((p)[1] == 0x18) && ((p)[2] == 0x05) && ((p)[3] == 0x0C) && \ 117 ((p)[13] == 0x3C) && ((p)[14] == 0x00) && ((p)[15] == 0x0A)) 118 119 bool dim2_sysfs_get_state_cb(void) 120 { 121 bool state; 122 unsigned long flags; 123 124 spin_lock_irqsave(&dim_lock, flags); 125 state = dim_get_lock_state(); 126 spin_unlock_irqrestore(&dim_lock, flags); 127 128 return state; 129 } 130 131 /** 132 * dimcb_io_read - callback from HAL to read an I/O register 133 * @ptr32: register address 134 */ 135 u32 dimcb_io_read(u32 __iomem *ptr32) 136 { 137 return readl(ptr32); 138 } 139 140 /** 141 * dimcb_io_write - callback from HAL to write value to an I/O register 142 * @ptr32: register address 143 * @value: value to write 144 */ 145 void dimcb_io_write(u32 __iomem *ptr32, u32 value) 146 { 147 writel(value, ptr32); 148 } 149 150 /** 151 * dimcb_on_error - callback from HAL to report miscommunication between 152 * HDM and HAL 153 * @error_id: Error ID 154 * @error_message: Error message. Some text in a free format 155 */ 156 void dimcb_on_error(u8 error_id, const char *error_message) 157 { 158 pr_err("%s: error_id - %d, error_message - %s\n", __func__, error_id, 159 error_message); 160 } 161 162 /** 163 * try_start_dim_transfer - try to transfer a buffer on a channel 164 * @hdm_ch: channel specific data 165 * 166 * Transfer a buffer from pending_list if the channel is ready 167 */ 168 static int try_start_dim_transfer(struct hdm_channel *hdm_ch) 169 { 170 u16 buf_size; 171 struct list_head *head = &hdm_ch->pending_list; 172 struct mbo *mbo; 173 unsigned long flags; 174 struct dim_ch_state_t st; 175 176 BUG_ON(!hdm_ch); 177 BUG_ON(!hdm_ch->is_initialized); 178 179 spin_lock_irqsave(&dim_lock, flags); 180 if (list_empty(head)) { 181 spin_unlock_irqrestore(&dim_lock, flags); 182 return -EAGAIN; 183 } 184 185 if (!dim_get_channel_state(&hdm_ch->ch, &st)->ready) { 186 spin_unlock_irqrestore(&dim_lock, flags); 187 return -EAGAIN; 188 } 189 190 mbo = list_first_entry(head, struct mbo, list); 191 buf_size = mbo->buffer_length; 192 193 if (dim_dbr_space(&hdm_ch->ch) < buf_size) { 194 spin_unlock_irqrestore(&dim_lock, flags); 195 return -EAGAIN; 196 } 197 198 BUG_ON(mbo->bus_address == 0); 199 if (!dim_enqueue_buffer(&hdm_ch->ch, mbo->bus_address, buf_size)) { 200 list_del(head->next); 201 spin_unlock_irqrestore(&dim_lock, flags); 202 mbo->processed_length = 0; 203 mbo->status = MBO_E_INVAL; 204 mbo->complete(mbo); 205 return -EFAULT; 206 } 207 208 list_move_tail(head->next, &hdm_ch->started_list); 209 spin_unlock_irqrestore(&dim_lock, flags); 210 211 return 0; 212 } 213 214 /** 215 * deliver_netinfo_thread - thread to deliver network status to mostcore 216 * @data: private data 217 * 218 * Wait for network status and deliver it to mostcore once it is received 219 */ 220 static int deliver_netinfo_thread(void *data) 221 { 222 struct dim2_hdm *dev = data; 223 224 while (!kthread_should_stop()) { 225 wait_event_interruptible(dev->netinfo_waitq, 226 dev->deliver_netinfo || 227 kthread_should_stop()); 228 229 if (dev->deliver_netinfo) { 230 dev->deliver_netinfo--; 231 if (dev->on_netinfo) { 232 dev->on_netinfo(&dev->most_iface, 233 dev->link_state, 234 dev->mac_addrs); 235 } 236 } 237 } 238 239 return 0; 240 } 241 242 /** 243 * retrieve_netinfo - retrieve network status from received buffer 244 * @dev: private data 245 * @mbo: received MBO 246 * 247 * Parse the message in buffer and get node address, link state, MAC address. 248 * Wake up a thread to deliver this status to mostcore 249 */ 250 static void retrieve_netinfo(struct dim2_hdm *dev, struct mbo *mbo) 251 { 252 u8 *data = mbo->virt_address; 253 254 pr_info("Node Address: 0x%03x\n", (u16)data[16] << 8 | data[17]); 255 dev->link_state = data[18]; 256 pr_info("NIState: %d\n", dev->link_state); 257 memcpy(dev->mac_addrs, data + 19, 6); 258 dev->deliver_netinfo++; 259 wake_up_interruptible(&dev->netinfo_waitq); 260 } 261 262 /** 263 * service_done_flag - handle completed buffers 264 * @dev: private data 265 * @ch_idx: channel index 266 * 267 * Return back the completed buffers to mostcore, using completion callback 268 */ 269 static void service_done_flag(struct dim2_hdm *dev, int ch_idx) 270 { 271 struct hdm_channel *hdm_ch = dev->hch + ch_idx; 272 struct dim_ch_state_t st; 273 struct list_head *head; 274 struct mbo *mbo; 275 int done_buffers; 276 unsigned long flags; 277 u8 *data; 278 279 BUG_ON(!hdm_ch); 280 BUG_ON(!hdm_ch->is_initialized); 281 282 spin_lock_irqsave(&dim_lock, flags); 283 284 done_buffers = dim_get_channel_state(&hdm_ch->ch, &st)->done_buffers; 285 if (!done_buffers) { 286 spin_unlock_irqrestore(&dim_lock, flags); 287 return; 288 } 289 290 if (!dim_detach_buffers(&hdm_ch->ch, done_buffers)) { 291 spin_unlock_irqrestore(&dim_lock, flags); 292 return; 293 } 294 spin_unlock_irqrestore(&dim_lock, flags); 295 296 head = &hdm_ch->started_list; 297 298 while (done_buffers) { 299 spin_lock_irqsave(&dim_lock, flags); 300 if (list_empty(head)) { 301 spin_unlock_irqrestore(&dim_lock, flags); 302 pr_crit("hard error: started_mbo list is empty whereas DIM2 has sent buffers\n"); 303 break; 304 } 305 306 mbo = list_first_entry(head, struct mbo, list); 307 list_del(head->next); 308 spin_unlock_irqrestore(&dim_lock, flags); 309 310 data = mbo->virt_address; 311 312 if (hdm_ch->data_type == MOST_CH_ASYNC && 313 hdm_ch->direction == MOST_CH_RX && 314 PACKET_IS_NET_INFO(data)) { 315 retrieve_netinfo(dev, mbo); 316 317 spin_lock_irqsave(&dim_lock, flags); 318 list_add_tail(&mbo->list, &hdm_ch->pending_list); 319 spin_unlock_irqrestore(&dim_lock, flags); 320 } else { 321 if (hdm_ch->data_type == MOST_CH_CONTROL || 322 hdm_ch->data_type == MOST_CH_ASYNC) { 323 u32 const data_size = 324 (u32)data[0] * 256 + data[1] + 2; 325 326 mbo->processed_length = 327 min_t(u32, data_size, 328 mbo->buffer_length); 329 } else { 330 mbo->processed_length = mbo->buffer_length; 331 } 332 mbo->status = MBO_SUCCESS; 333 mbo->complete(mbo); 334 } 335 336 done_buffers--; 337 } 338 } 339 340 static struct dim_channel **get_active_channels(struct dim2_hdm *dev, 341 struct dim_channel **buffer) 342 { 343 int idx = 0; 344 int ch_idx; 345 346 for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) { 347 if (dev->hch[ch_idx].is_initialized) 348 buffer[idx++] = &dev->hch[ch_idx].ch; 349 } 350 buffer[idx++] = NULL; 351 352 return buffer; 353 } 354 355 static irqreturn_t dim2_mlb_isr(int irq, void *_dev) 356 { 357 struct dim2_hdm *dev = _dev; 358 unsigned long flags; 359 360 spin_lock_irqsave(&dim_lock, flags); 361 dim_service_mlb_int_irq(); 362 spin_unlock_irqrestore(&dim_lock, flags); 363 364 if (dev->atx_idx >= 0 && dev->hch[dev->atx_idx].is_initialized) 365 while (!try_start_dim_transfer(dev->hch + dev->atx_idx)) 366 continue; 367 368 return IRQ_HANDLED; 369 } 370 371 /** 372 * dim2_tasklet_fn - tasklet function 373 * @data: private data 374 * 375 * Service each initialized channel, if needed 376 */ 377 static void dim2_tasklet_fn(unsigned long data) 378 { 379 struct dim2_hdm *dev = (struct dim2_hdm *)data; 380 unsigned long flags; 381 int ch_idx; 382 383 for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) { 384 if (!dev->hch[ch_idx].is_initialized) 385 continue; 386 387 spin_lock_irqsave(&dim_lock, flags); 388 dim_service_channel(&dev->hch[ch_idx].ch); 389 spin_unlock_irqrestore(&dim_lock, flags); 390 391 service_done_flag(dev, ch_idx); 392 while (!try_start_dim_transfer(dev->hch + ch_idx)) 393 continue; 394 } 395 } 396 397 /** 398 * dim2_ahb_isr - interrupt service routine 399 * @irq: irq number 400 * @_dev: private data 401 * 402 * Acknowledge the interrupt and schedule a tasklet to service channels. 403 * Return IRQ_HANDLED. 404 */ 405 static irqreturn_t dim2_ahb_isr(int irq, void *_dev) 406 { 407 struct dim2_hdm *dev = _dev; 408 struct dim_channel *buffer[DMA_CHANNELS + 1]; 409 unsigned long flags; 410 411 spin_lock_irqsave(&dim_lock, flags); 412 dim_service_ahb_int_irq(get_active_channels(dev, buffer)); 413 spin_unlock_irqrestore(&dim_lock, flags); 414 415 dim2_tasklet.data = (unsigned long)dev; 416 tasklet_schedule(&dim2_tasklet); 417 return IRQ_HANDLED; 418 } 419 420 /** 421 * complete_all_mbos - complete MBO's in a list 422 * @head: list head 423 * 424 * Delete all the entries in list and return back MBO's to mostcore using 425 * completion call back. 426 */ 427 static void complete_all_mbos(struct list_head *head) 428 { 429 unsigned long flags; 430 struct mbo *mbo; 431 432 for (;;) { 433 spin_lock_irqsave(&dim_lock, flags); 434 if (list_empty(head)) { 435 spin_unlock_irqrestore(&dim_lock, flags); 436 break; 437 } 438 439 mbo = list_first_entry(head, struct mbo, list); 440 list_del(head->next); 441 spin_unlock_irqrestore(&dim_lock, flags); 442 443 mbo->processed_length = 0; 444 mbo->status = MBO_E_CLOSE; 445 mbo->complete(mbo); 446 } 447 } 448 449 /** 450 * configure_channel - initialize a channel 451 * @iface: interface the channel belongs to 452 * @channel: channel to be configured 453 * @channel_config: structure that holds the configuration information 454 * 455 * Receives configuration information from mostcore and initialize 456 * the corresponding channel. Return 0 on success, negative on failure. 457 */ 458 static int configure_channel(struct most_interface *most_iface, int ch_idx, 459 struct most_channel_config *ccfg) 460 { 461 struct dim2_hdm *dev = iface_to_hdm(most_iface); 462 bool const is_tx = ccfg->direction == MOST_CH_TX; 463 u16 const sub_size = ccfg->subbuffer_size; 464 u16 const buf_size = ccfg->buffer_size; 465 u16 new_size; 466 unsigned long flags; 467 u8 hal_ret; 468 int const ch_addr = ch_idx * 2 + 2; 469 struct hdm_channel *const hdm_ch = dev->hch + ch_idx; 470 471 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS); 472 473 if (hdm_ch->is_initialized) 474 return -EPERM; 475 476 /* do not reset if the property was set by user, see poison_channel */ 477 hdm_ch->reset_dbr_size = ccfg->dbr_size ? NULL : &ccfg->dbr_size; 478 479 /* zero value is default dbr_size, see dim2 hal */ 480 hdm_ch->ch.dbr_size = ccfg->dbr_size; 481 482 switch (ccfg->data_type) { 483 case MOST_CH_CONTROL: 484 new_size = dim_norm_ctrl_async_buffer_size(buf_size); 485 if (new_size == 0) { 486 pr_err("%s: too small buffer size\n", hdm_ch->name); 487 return -EINVAL; 488 } 489 ccfg->buffer_size = new_size; 490 if (new_size != buf_size) 491 pr_warn("%s: fixed buffer size (%d -> %d)\n", 492 hdm_ch->name, buf_size, new_size); 493 spin_lock_irqsave(&dim_lock, flags); 494 hal_ret = dim_init_control(&hdm_ch->ch, is_tx, ch_addr, 495 is_tx ? new_size * 2 : new_size); 496 break; 497 case MOST_CH_ASYNC: 498 new_size = dim_norm_ctrl_async_buffer_size(buf_size); 499 if (new_size == 0) { 500 pr_err("%s: too small buffer size\n", hdm_ch->name); 501 return -EINVAL; 502 } 503 ccfg->buffer_size = new_size; 504 if (new_size != buf_size) 505 pr_warn("%s: fixed buffer size (%d -> %d)\n", 506 hdm_ch->name, buf_size, new_size); 507 spin_lock_irqsave(&dim_lock, flags); 508 hal_ret = dim_init_async(&hdm_ch->ch, is_tx, ch_addr, 509 is_tx ? new_size * 2 : new_size); 510 break; 511 case MOST_CH_ISOC: 512 new_size = dim_norm_isoc_buffer_size(buf_size, sub_size); 513 if (new_size == 0) { 514 pr_err("%s: invalid sub-buffer size or too small buffer size\n", 515 hdm_ch->name); 516 return -EINVAL; 517 } 518 ccfg->buffer_size = new_size; 519 if (new_size != buf_size) 520 pr_warn("%s: fixed buffer size (%d -> %d)\n", 521 hdm_ch->name, buf_size, new_size); 522 spin_lock_irqsave(&dim_lock, flags); 523 hal_ret = dim_init_isoc(&hdm_ch->ch, is_tx, ch_addr, sub_size); 524 break; 525 case MOST_CH_SYNC: 526 new_size = dim_norm_sync_buffer_size(buf_size, sub_size); 527 if (new_size == 0) { 528 pr_err("%s: invalid sub-buffer size or too small buffer size\n", 529 hdm_ch->name); 530 return -EINVAL; 531 } 532 ccfg->buffer_size = new_size; 533 if (new_size != buf_size) 534 pr_warn("%s: fixed buffer size (%d -> %d)\n", 535 hdm_ch->name, buf_size, new_size); 536 spin_lock_irqsave(&dim_lock, flags); 537 hal_ret = dim_init_sync(&hdm_ch->ch, is_tx, ch_addr, sub_size); 538 break; 539 default: 540 pr_err("%s: configure failed, bad channel type: %d\n", 541 hdm_ch->name, ccfg->data_type); 542 return -EINVAL; 543 } 544 545 if (hal_ret != DIM_NO_ERROR) { 546 spin_unlock_irqrestore(&dim_lock, flags); 547 pr_err("%s: configure failed (%d), type: %d, is_tx: %d\n", 548 hdm_ch->name, hal_ret, ccfg->data_type, (int)is_tx); 549 return -ENODEV; 550 } 551 552 hdm_ch->data_type = ccfg->data_type; 553 hdm_ch->direction = ccfg->direction; 554 hdm_ch->is_initialized = true; 555 556 if (hdm_ch->data_type == MOST_CH_ASYNC && 557 hdm_ch->direction == MOST_CH_TX && 558 dev->atx_idx < 0) 559 dev->atx_idx = ch_idx; 560 561 spin_unlock_irqrestore(&dim_lock, flags); 562 ccfg->dbr_size = hdm_ch->ch.dbr_size; 563 564 return 0; 565 } 566 567 /** 568 * enqueue - enqueue a buffer for data transfer 569 * @iface: intended interface 570 * @channel: ID of the channel the buffer is intended for 571 * @mbo: pointer to the buffer object 572 * 573 * Push the buffer into pending_list and try to transfer one buffer from 574 * pending_list. Return 0 on success, negative on failure. 575 */ 576 static int enqueue(struct most_interface *most_iface, int ch_idx, 577 struct mbo *mbo) 578 { 579 struct dim2_hdm *dev = iface_to_hdm(most_iface); 580 struct hdm_channel *hdm_ch = dev->hch + ch_idx; 581 unsigned long flags; 582 583 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS); 584 585 if (!hdm_ch->is_initialized) 586 return -EPERM; 587 588 if (mbo->bus_address == 0) 589 return -EFAULT; 590 591 spin_lock_irqsave(&dim_lock, flags); 592 list_add_tail(&mbo->list, &hdm_ch->pending_list); 593 spin_unlock_irqrestore(&dim_lock, flags); 594 595 (void)try_start_dim_transfer(hdm_ch); 596 597 return 0; 598 } 599 600 /** 601 * request_netinfo - triggers retrieving of network info 602 * @iface: pointer to the interface 603 * @channel_id: corresponding channel ID 604 * 605 * Send a command to INIC which triggers retrieving of network info by means of 606 * "Message exchange over MDP/MEP". Return 0 on success, negative on failure. 607 */ 608 static void request_netinfo(struct most_interface *most_iface, int ch_idx, 609 void (*on_netinfo)(struct most_interface *, 610 unsigned char, unsigned char *)) 611 { 612 struct dim2_hdm *dev = iface_to_hdm(most_iface); 613 struct mbo *mbo; 614 u8 *data; 615 616 dev->on_netinfo = on_netinfo; 617 if (!on_netinfo) 618 return; 619 620 if (dev->atx_idx < 0) { 621 pr_err("Async Tx Not initialized\n"); 622 return; 623 } 624 625 mbo = most_get_mbo(&dev->most_iface, dev->atx_idx, NULL); 626 if (!mbo) 627 return; 628 629 mbo->buffer_length = 5; 630 631 data = mbo->virt_address; 632 633 data[0] = 0x00; /* PML High byte */ 634 data[1] = 0x03; /* PML Low byte */ 635 data[2] = 0x02; /* PMHL */ 636 data[3] = 0x08; /* FPH */ 637 data[4] = 0x40; /* FMF (FIFO cmd msg - Triggers NAOverMDP) */ 638 639 most_submit_mbo(mbo); 640 } 641 642 /** 643 * poison_channel - poison buffers of a channel 644 * @iface: pointer to the interface the channel to be poisoned belongs to 645 * @channel_id: corresponding channel ID 646 * 647 * Destroy a channel and complete all the buffers in both started_list & 648 * pending_list. Return 0 on success, negative on failure. 649 */ 650 static int poison_channel(struct most_interface *most_iface, int ch_idx) 651 { 652 struct dim2_hdm *dev = iface_to_hdm(most_iface); 653 struct hdm_channel *hdm_ch = dev->hch + ch_idx; 654 unsigned long flags; 655 u8 hal_ret; 656 int ret = 0; 657 658 BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS); 659 660 if (!hdm_ch->is_initialized) 661 return -EPERM; 662 663 tasklet_disable(&dim2_tasklet); 664 spin_lock_irqsave(&dim_lock, flags); 665 hal_ret = dim_destroy_channel(&hdm_ch->ch); 666 hdm_ch->is_initialized = false; 667 if (ch_idx == dev->atx_idx) 668 dev->atx_idx = -1; 669 spin_unlock_irqrestore(&dim_lock, flags); 670 tasklet_enable(&dim2_tasklet); 671 if (hal_ret != DIM_NO_ERROR) { 672 pr_err("HAL Failed to close channel %s\n", hdm_ch->name); 673 ret = -EFAULT; 674 } 675 676 complete_all_mbos(&hdm_ch->started_list); 677 complete_all_mbos(&hdm_ch->pending_list); 678 if (hdm_ch->reset_dbr_size) 679 *hdm_ch->reset_dbr_size = 0; 680 681 return ret; 682 } 683 684 static void *dma_alloc(struct mbo *mbo, u32 size) 685 { 686 struct device *dev = mbo->ifp->driver_dev; 687 688 return dma_alloc_coherent(dev, size, &mbo->bus_address, GFP_KERNEL); 689 } 690 691 static void dma_free(struct mbo *mbo, u32 size) 692 { 693 struct device *dev = mbo->ifp->driver_dev; 694 695 dma_free_coherent(dev, size, mbo->virt_address, mbo->bus_address); 696 } 697 698 static const struct of_device_id dim2_of_match[]; 699 700 static struct { 701 const char *clock_speed; 702 u8 clk_speed; 703 } clk_mt[] = { 704 { "256fs", CLK_256FS }, 705 { "512fs", CLK_512FS }, 706 { "1024fs", CLK_1024FS }, 707 { "2048fs", CLK_2048FS }, 708 { "3072fs", CLK_3072FS }, 709 { "4096fs", CLK_4096FS }, 710 { "6144fs", CLK_6144FS }, 711 { "8192fs", CLK_8192FS }, 712 }; 713 714 /** 715 * get_dim2_clk_speed - converts string to DIM2 clock speed value 716 * 717 * @clock_speed: string in the format "{NUMBER}fs" 718 * @val: pointer to get one of the CLK_{NUMBER}FS values 719 * 720 * By success stores one of the CLK_{NUMBER}FS in the *val and returns 0, 721 * otherwise returns -EINVAL. 722 */ 723 static int get_dim2_clk_speed(const char *clock_speed, u8 *val) 724 { 725 int i; 726 727 for (i = 0; i < ARRAY_SIZE(clk_mt); i++) { 728 if (!strcmp(clock_speed, clk_mt[i].clock_speed)) { 729 *val = clk_mt[i].clk_speed; 730 return 0; 731 } 732 } 733 return -EINVAL; 734 } 735 736 /* 737 * dim2_probe - dim2 probe handler 738 * @pdev: platform device structure 739 * 740 * Register the dim2 interface with mostcore and initialize it. 741 * Return 0 on success, negative on failure. 742 */ 743 static int dim2_probe(struct platform_device *pdev) 744 { 745 const struct dim2_platform_data *pdata; 746 const struct of_device_id *of_id; 747 const char *clock_speed; 748 struct dim2_hdm *dev; 749 struct resource *res; 750 int ret, i; 751 u8 hal_ret; 752 int irq; 753 754 enum { MLB_INT_IDX, AHB0_INT_IDX }; 755 756 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 757 if (!dev) 758 return -ENOMEM; 759 760 dev->atx_idx = -1; 761 762 platform_set_drvdata(pdev, dev); 763 764 ret = of_property_read_string(pdev->dev.of_node, 765 "microchip,clock-speed", &clock_speed); 766 if (ret) { 767 dev_err(&pdev->dev, "missing dt property clock-speed\n"); 768 return ret; 769 } 770 771 ret = get_dim2_clk_speed(clock_speed, &dev->clk_speed); 772 if (ret) { 773 dev_err(&pdev->dev, "bad dt property clock-speed\n"); 774 return ret; 775 } 776 777 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 778 dev->io_base = devm_ioremap_resource(&pdev->dev, res); 779 if (IS_ERR(dev->io_base)) 780 return PTR_ERR(dev->io_base); 781 782 of_id = of_match_node(dim2_of_match, pdev->dev.of_node); 783 pdata = of_id->data; 784 ret = pdata && pdata->enable ? pdata->enable(pdev) : 0; 785 if (ret) 786 return ret; 787 788 dev->disable_platform = pdata ? pdata->disable : 0; 789 790 dev_info(&pdev->dev, "sync: num of frames per sub-buffer: %u\n", fcnt); 791 hal_ret = dim_startup(dev->io_base, dev->clk_speed, fcnt); 792 if (hal_ret != DIM_NO_ERROR) { 793 dev_err(&pdev->dev, "dim_startup failed: %d\n", hal_ret); 794 ret = -ENODEV; 795 goto err_disable_platform; 796 } 797 798 irq = platform_get_irq(pdev, AHB0_INT_IDX); 799 if (irq < 0) { 800 dev_err(&pdev->dev, "failed to get ahb0_int irq: %d\n", irq); 801 ret = irq; 802 goto err_shutdown_dim; 803 } 804 805 ret = devm_request_irq(&pdev->dev, irq, dim2_ahb_isr, 0, 806 "dim2_ahb0_int", dev); 807 if (ret) { 808 dev_err(&pdev->dev, "failed to request ahb0_int irq %d\n", irq); 809 goto err_shutdown_dim; 810 } 811 812 irq = platform_get_irq(pdev, MLB_INT_IDX); 813 if (irq < 0) { 814 dev_err(&pdev->dev, "failed to get mlb_int irq: %d\n", irq); 815 ret = irq; 816 goto err_shutdown_dim; 817 } 818 819 ret = devm_request_irq(&pdev->dev, irq, dim2_mlb_isr, 0, 820 "dim2_mlb_int", dev); 821 if (ret) { 822 dev_err(&pdev->dev, "failed to request mlb_int irq %d\n", irq); 823 goto err_shutdown_dim; 824 } 825 826 init_waitqueue_head(&dev->netinfo_waitq); 827 dev->deliver_netinfo = 0; 828 dev->netinfo_task = kthread_run(&deliver_netinfo_thread, dev, 829 "dim2_netinfo"); 830 if (IS_ERR(dev->netinfo_task)) { 831 ret = PTR_ERR(dev->netinfo_task); 832 goto err_shutdown_dim; 833 } 834 835 for (i = 0; i < DMA_CHANNELS; i++) { 836 struct most_channel_capability *cap = dev->capabilities + i; 837 struct hdm_channel *hdm_ch = dev->hch + i; 838 839 INIT_LIST_HEAD(&hdm_ch->pending_list); 840 INIT_LIST_HEAD(&hdm_ch->started_list); 841 hdm_ch->is_initialized = false; 842 snprintf(hdm_ch->name, sizeof(hdm_ch->name), "ca%d", i * 2 + 2); 843 844 cap->name_suffix = hdm_ch->name; 845 cap->direction = MOST_CH_RX | MOST_CH_TX; 846 cap->data_type = MOST_CH_CONTROL | MOST_CH_ASYNC | 847 MOST_CH_ISOC | MOST_CH_SYNC; 848 cap->num_buffers_packet = MAX_BUFFERS_PACKET; 849 cap->buffer_size_packet = MAX_BUF_SIZE_PACKET; 850 cap->num_buffers_streaming = MAX_BUFFERS_STREAMING; 851 cap->buffer_size_streaming = MAX_BUF_SIZE_STREAMING; 852 } 853 854 { 855 const char *fmt; 856 857 if (sizeof(res->start) == sizeof(long long)) 858 fmt = "dim2-%016llx"; 859 else if (sizeof(res->start) == sizeof(long)) 860 fmt = "dim2-%016lx"; 861 else 862 fmt = "dim2-%016x"; 863 864 snprintf(dev->name, sizeof(dev->name), fmt, res->start); 865 } 866 867 dev->most_iface.interface = ITYPE_MEDIALB_DIM2; 868 dev->most_iface.description = dev->name; 869 dev->most_iface.num_channels = DMA_CHANNELS; 870 dev->most_iface.channel_vector = dev->capabilities; 871 dev->most_iface.configure = configure_channel; 872 dev->most_iface.enqueue = enqueue; 873 dev->most_iface.dma_alloc = dma_alloc; 874 dev->most_iface.dma_free = dma_free; 875 dev->most_iface.poison_channel = poison_channel; 876 dev->most_iface.request_netinfo = request_netinfo; 877 dev->most_iface.driver_dev = &pdev->dev; 878 dev->dev.init_name = "dim2_state"; 879 dev->dev.parent = &dev->most_iface.dev; 880 881 ret = most_register_interface(&dev->most_iface); 882 if (ret) { 883 dev_err(&pdev->dev, "failed to register MOST interface\n"); 884 goto err_stop_thread; 885 } 886 887 ret = dim2_sysfs_probe(&dev->dev); 888 if (ret) { 889 dev_err(&pdev->dev, "failed to create sysfs attribute\n"); 890 goto err_unreg_iface; 891 } 892 893 return 0; 894 895 err_unreg_iface: 896 most_deregister_interface(&dev->most_iface); 897 err_stop_thread: 898 kthread_stop(dev->netinfo_task); 899 err_shutdown_dim: 900 dim_shutdown(); 901 err_disable_platform: 902 if (dev->disable_platform) 903 dev->disable_platform(pdev); 904 905 return ret; 906 } 907 908 /** 909 * dim2_remove - dim2 remove handler 910 * @pdev: platform device structure 911 * 912 * Unregister the interface from mostcore 913 */ 914 static int dim2_remove(struct platform_device *pdev) 915 { 916 struct dim2_hdm *dev = platform_get_drvdata(pdev); 917 unsigned long flags; 918 919 dim2_sysfs_destroy(&dev->dev); 920 most_deregister_interface(&dev->most_iface); 921 kthread_stop(dev->netinfo_task); 922 923 spin_lock_irqsave(&dim_lock, flags); 924 dim_shutdown(); 925 spin_unlock_irqrestore(&dim_lock, flags); 926 927 if (dev->disable_platform) 928 dev->disable_platform(pdev); 929 930 return 0; 931 } 932 933 /* platform specific functions [[ */ 934 935 static int fsl_mx6_enable(struct platform_device *pdev) 936 { 937 struct dim2_hdm *dev = platform_get_drvdata(pdev); 938 int ret; 939 940 dev->clk = devm_clk_get(&pdev->dev, "mlb"); 941 if (IS_ERR_OR_NULL(dev->clk)) { 942 dev_err(&pdev->dev, "unable to get mlb clock\n"); 943 return -EFAULT; 944 } 945 946 ret = clk_prepare_enable(dev->clk); 947 if (ret) { 948 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed"); 949 return ret; 950 } 951 952 if (dev->clk_speed >= CLK_2048FS) { 953 /* enable pll */ 954 dev->clk_pll = devm_clk_get(&pdev->dev, "pll8_mlb"); 955 if (IS_ERR_OR_NULL(dev->clk_pll)) { 956 dev_err(&pdev->dev, "unable to get mlb pll clock\n"); 957 clk_disable_unprepare(dev->clk); 958 return -EFAULT; 959 } 960 961 writel(0x888, dev->io_base + 0x38); 962 clk_prepare_enable(dev->clk_pll); 963 } 964 965 return 0; 966 } 967 968 static void fsl_mx6_disable(struct platform_device *pdev) 969 { 970 struct dim2_hdm *dev = platform_get_drvdata(pdev); 971 972 if (dev->clk_speed >= CLK_2048FS) 973 clk_disable_unprepare(dev->clk_pll); 974 975 clk_disable_unprepare(dev->clk); 976 } 977 978 static int rcar_h2_enable(struct platform_device *pdev) 979 { 980 struct dim2_hdm *dev = platform_get_drvdata(pdev); 981 int ret; 982 983 dev->clk = devm_clk_get(&pdev->dev, NULL); 984 if (IS_ERR(dev->clk)) { 985 dev_err(&pdev->dev, "cannot get clock\n"); 986 return PTR_ERR(dev->clk); 987 } 988 989 ret = clk_prepare_enable(dev->clk); 990 if (ret) { 991 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed"); 992 return ret; 993 } 994 995 if (dev->clk_speed >= CLK_2048FS) { 996 /* enable MLP pll and LVDS drivers */ 997 writel(0x03, dev->io_base + 0x600); 998 /* set bias */ 999 writel(0x888, dev->io_base + 0x38); 1000 } else { 1001 /* PLL */ 1002 writel(0x04, dev->io_base + 0x600); 1003 } 1004 1005 1006 /* BBCR = 0b11 */ 1007 writel(0x03, dev->io_base + 0x500); 1008 writel(0x0002FF02, dev->io_base + 0x508); 1009 1010 return 0; 1011 } 1012 1013 static void rcar_h2_disable(struct platform_device *pdev) 1014 { 1015 struct dim2_hdm *dev = platform_get_drvdata(pdev); 1016 1017 clk_disable_unprepare(dev->clk); 1018 1019 /* disable PLLs and LVDS drivers */ 1020 writel(0x0, dev->io_base + 0x600); 1021 } 1022 1023 static int rcar_m3_enable(struct platform_device *pdev) 1024 { 1025 struct dim2_hdm *dev = platform_get_drvdata(pdev); 1026 u32 enable_512fs = dev->clk_speed == CLK_512FS; 1027 int ret; 1028 1029 dev->clk = devm_clk_get(&pdev->dev, NULL); 1030 if (IS_ERR(dev->clk)) { 1031 dev_err(&pdev->dev, "cannot get clock\n"); 1032 return PTR_ERR(dev->clk); 1033 } 1034 1035 ret = clk_prepare_enable(dev->clk); 1036 if (ret) { 1037 dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed"); 1038 return ret; 1039 } 1040 1041 /* PLL */ 1042 writel(0x04, dev->io_base + 0x600); 1043 1044 writel(enable_512fs, dev->io_base + 0x604); 1045 1046 /* BBCR = 0b11 */ 1047 writel(0x03, dev->io_base + 0x500); 1048 writel(0x0002FF02, dev->io_base + 0x508); 1049 1050 return 0; 1051 } 1052 1053 static void rcar_m3_disable(struct platform_device *pdev) 1054 { 1055 struct dim2_hdm *dev = platform_get_drvdata(pdev); 1056 1057 clk_disable_unprepare(dev->clk); 1058 1059 /* disable PLLs and LVDS drivers */ 1060 writel(0x0, dev->io_base + 0x600); 1061 } 1062 1063 /* ]] platform specific functions */ 1064 1065 enum dim2_platforms { FSL_MX6, RCAR_H2, RCAR_M3 }; 1066 1067 static struct dim2_platform_data plat_data[] = { 1068 [FSL_MX6] = { .enable = fsl_mx6_enable, .disable = fsl_mx6_disable }, 1069 [RCAR_H2] = { .enable = rcar_h2_enable, .disable = rcar_h2_disable }, 1070 [RCAR_M3] = { .enable = rcar_m3_enable, .disable = rcar_m3_disable }, 1071 }; 1072 1073 static const struct of_device_id dim2_of_match[] = { 1074 { 1075 .compatible = "fsl,imx6q-mlb150", 1076 .data = plat_data + FSL_MX6 1077 }, 1078 { 1079 .compatible = "renesas,mlp", 1080 .data = plat_data + RCAR_H2 1081 }, 1082 { 1083 .compatible = "rcar,medialb-dim2", 1084 .data = plat_data + RCAR_M3 1085 }, 1086 { 1087 .compatible = "xlnx,axi4-os62420_3pin-1.00.a", 1088 }, 1089 { 1090 .compatible = "xlnx,axi4-os62420_6pin-1.00.a", 1091 }, 1092 {}, 1093 }; 1094 1095 MODULE_DEVICE_TABLE(of, dim2_of_match); 1096 1097 static struct platform_driver dim2_driver = { 1098 .probe = dim2_probe, 1099 .remove = dim2_remove, 1100 .driver = { 1101 .name = "hdm_dim2", 1102 .of_match_table = dim2_of_match, 1103 }, 1104 }; 1105 1106 module_platform_driver(dim2_driver); 1107 1108 MODULE_AUTHOR("Andrey Shvetsov <andrey.shvetsov@k2l.de>"); 1109 MODULE_DESCRIPTION("MediaLB DIM2 Hardware Dependent Module"); 1110 MODULE_LICENSE("GPL"); 1111