1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk/tegra.h> 8 #include <linux/device.h> 9 #include <linux/host1x.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_graph.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 16 #include <media/v4l2-fwnode.h> 17 18 #include "csi.h" 19 #include "video.h" 20 21 #define MHZ 1000000 22 23 static inline struct tegra_csi * 24 host1x_client_to_csi(struct host1x_client *client) 25 { 26 return container_of(client, struct tegra_csi, client); 27 } 28 29 static inline struct tegra_csi_channel *to_csi_chan(struct v4l2_subdev *subdev) 30 { 31 return container_of(subdev, struct tegra_csi_channel, subdev); 32 } 33 34 /* 35 * CSI is a separate subdevice which has 6 source pads to generate 36 * test pattern. CSI subdevice pad ops are used only for TPG and 37 * allows below TPG formats. 38 */ 39 static const struct v4l2_mbus_framefmt tegra_csi_tpg_fmts[] = { 40 { 41 TEGRA_DEF_WIDTH, 42 TEGRA_DEF_HEIGHT, 43 MEDIA_BUS_FMT_SRGGB10_1X10, 44 V4L2_FIELD_NONE, 45 V4L2_COLORSPACE_SRGB 46 }, 47 { 48 TEGRA_DEF_WIDTH, 49 TEGRA_DEF_HEIGHT, 50 MEDIA_BUS_FMT_RGB888_1X32_PADHI, 51 V4L2_FIELD_NONE, 52 V4L2_COLORSPACE_SRGB 53 }, 54 }; 55 56 static const struct v4l2_frmsize_discrete tegra_csi_tpg_sizes[] = { 57 { 1280, 720 }, 58 { 1920, 1080 }, 59 { 3840, 2160 }, 60 }; 61 62 /* 63 * V4L2 Subdevice Pad Operations 64 */ 65 static int csi_enum_bus_code(struct v4l2_subdev *subdev, 66 struct v4l2_subdev_state *sd_state, 67 struct v4l2_subdev_mbus_code_enum *code) 68 { 69 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 70 return -ENOIOCTLCMD; 71 72 if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) 73 return -EINVAL; 74 75 code->code = tegra_csi_tpg_fmts[code->index].code; 76 77 return 0; 78 } 79 80 static int csi_get_format(struct v4l2_subdev *subdev, 81 struct v4l2_subdev_state *sd_state, 82 struct v4l2_subdev_format *fmt) 83 { 84 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 85 86 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 87 return -ENOIOCTLCMD; 88 89 fmt->format = csi_chan->format; 90 91 return 0; 92 } 93 94 static int csi_get_frmrate_table_index(struct tegra_csi *csi, u32 code, 95 u32 width, u32 height) 96 { 97 const struct tpg_framerate *frmrate; 98 unsigned int i; 99 100 frmrate = csi->soc->tpg_frmrate_table; 101 for (i = 0; i < csi->soc->tpg_frmrate_table_size; i++) { 102 if (frmrate[i].code == code && 103 frmrate[i].frmsize.width == width && 104 frmrate[i].frmsize.height == height) { 105 return i; 106 } 107 } 108 109 return -EINVAL; 110 } 111 112 static void csi_chan_update_blank_intervals(struct tegra_csi_channel *csi_chan, 113 u32 code, u32 width, u32 height) 114 { 115 struct tegra_csi *csi = csi_chan->csi; 116 const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table; 117 int index; 118 119 index = csi_get_frmrate_table_index(csi_chan->csi, code, 120 width, height); 121 if (index >= 0) { 122 csi_chan->h_blank = frmrate[index].h_blank; 123 csi_chan->v_blank = frmrate[index].v_blank; 124 csi_chan->framerate = frmrate[index].framerate; 125 } 126 } 127 128 static int csi_enum_framesizes(struct v4l2_subdev *subdev, 129 struct v4l2_subdev_state *sd_state, 130 struct v4l2_subdev_frame_size_enum *fse) 131 { 132 unsigned int i; 133 134 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 135 return -ENOIOCTLCMD; 136 137 if (fse->index >= ARRAY_SIZE(tegra_csi_tpg_sizes)) 138 return -EINVAL; 139 140 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++) 141 if (fse->code == tegra_csi_tpg_fmts[i].code) 142 break; 143 144 if (i == ARRAY_SIZE(tegra_csi_tpg_fmts)) 145 return -EINVAL; 146 147 fse->min_width = tegra_csi_tpg_sizes[fse->index].width; 148 fse->max_width = tegra_csi_tpg_sizes[fse->index].width; 149 fse->min_height = tegra_csi_tpg_sizes[fse->index].height; 150 fse->max_height = tegra_csi_tpg_sizes[fse->index].height; 151 152 return 0; 153 } 154 155 static int csi_enum_frameintervals(struct v4l2_subdev *subdev, 156 struct v4l2_subdev_state *sd_state, 157 struct v4l2_subdev_frame_interval_enum *fie) 158 { 159 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 160 struct tegra_csi *csi = csi_chan->csi; 161 const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table; 162 int index; 163 164 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 165 return -ENOIOCTLCMD; 166 167 /* one framerate per format and resolution */ 168 if (fie->index > 0) 169 return -EINVAL; 170 171 index = csi_get_frmrate_table_index(csi_chan->csi, fie->code, 172 fie->width, fie->height); 173 if (index < 0) 174 return -EINVAL; 175 176 fie->interval.numerator = 1; 177 fie->interval.denominator = frmrate[index].framerate; 178 179 return 0; 180 } 181 182 static int csi_set_format(struct v4l2_subdev *subdev, 183 struct v4l2_subdev_state *sd_state, 184 struct v4l2_subdev_format *fmt) 185 { 186 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 187 struct v4l2_mbus_framefmt *format = &fmt->format; 188 const struct v4l2_frmsize_discrete *sizes; 189 unsigned int i; 190 191 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 192 return -ENOIOCTLCMD; 193 194 sizes = v4l2_find_nearest_size(tegra_csi_tpg_sizes, 195 ARRAY_SIZE(tegra_csi_tpg_sizes), 196 width, height, 197 format->width, format->width); 198 format->width = sizes->width; 199 format->height = sizes->height; 200 201 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++) 202 if (format->code == tegra_csi_tpg_fmts[i].code) 203 break; 204 205 if (i == ARRAY_SIZE(tegra_csi_tpg_fmts)) 206 i = 0; 207 208 format->code = tegra_csi_tpg_fmts[i].code; 209 format->field = V4L2_FIELD_NONE; 210 211 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 212 return 0; 213 214 /* update blanking intervals from frame rate table and format */ 215 csi_chan_update_blank_intervals(csi_chan, format->code, 216 format->width, format->height); 217 csi_chan->format = *format; 218 219 return 0; 220 } 221 222 /* 223 * V4L2 Subdevice Video Operations 224 */ 225 static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, 226 struct v4l2_subdev_frame_interval *vfi) 227 { 228 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 229 230 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 231 return -ENOIOCTLCMD; 232 233 vfi->interval.numerator = 1; 234 vfi->interval.denominator = csi_chan->framerate; 235 236 return 0; 237 } 238 239 static unsigned int csi_get_pixel_rate(struct tegra_csi_channel *csi_chan) 240 { 241 struct tegra_vi_channel *chan; 242 struct v4l2_subdev *src_subdev; 243 struct v4l2_ctrl *ctrl; 244 245 chan = v4l2_get_subdev_hostdata(&csi_chan->subdev); 246 src_subdev = tegra_channel_get_remote_source_subdev(chan); 247 ctrl = v4l2_ctrl_find(src_subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); 248 if (ctrl) 249 return v4l2_ctrl_g_ctrl_int64(ctrl); 250 251 return 0; 252 } 253 254 void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, 255 u8 csi_port_num, 256 u8 *clk_settle_time, 257 u8 *ths_settle_time) 258 { 259 struct tegra_csi *csi = csi_chan->csi; 260 unsigned int cil_clk_mhz; 261 unsigned int pix_clk_mhz; 262 int clk_idx = (csi_port_num >> 1) + 1; 263 264 cil_clk_mhz = clk_get_rate(csi->clks[clk_idx].clk) / MHZ; 265 pix_clk_mhz = csi_get_pixel_rate(csi_chan) / MHZ; 266 267 /* 268 * CLK Settle time is the interval during which HS receiver should 269 * ignore any clock lane HS transitions, starting from the beginning 270 * of T-CLK-PREPARE. 271 * Per DPHY specification, T-CLK-SETTLE should be between 95ns ~ 300ns 272 * 273 * 95ns < (clk-settle-programmed + 7) * lp clk period < 300ns 274 * midpoint = 197.5 ns 275 */ 276 *clk_settle_time = ((95 + 300) * cil_clk_mhz - 14000) / 2000; 277 278 /* 279 * THS Settle time is the interval during which HS receiver should 280 * ignore any data lane HS transitions, starting from the beginning 281 * of THS-PREPARE. 282 * 283 * Per DPHY specification, T-HS-SETTLE should be between 85ns + 6UI 284 * and 145ns+10UI. 285 * 85ns + 6UI < (Ths-settle-prog + 5) * lp_clk_period < 145ns + 10UI 286 * midpoint = 115ns + 8UI 287 */ 288 if (pix_clk_mhz) 289 *ths_settle_time = (115 * cil_clk_mhz + 8000 * cil_clk_mhz 290 / (2 * pix_clk_mhz) - 5000) / 1000; 291 } 292 293 static int tegra_csi_enable_stream(struct v4l2_subdev *subdev) 294 { 295 struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); 296 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 297 struct tegra_csi *csi = csi_chan->csi; 298 int ret, err; 299 300 ret = pm_runtime_resume_and_get(csi->dev); 301 if (ret < 0) { 302 dev_err(csi->dev, "failed to get runtime PM: %d\n", ret); 303 return ret; 304 } 305 306 if (csi_chan->mipi) { 307 ret = tegra_mipi_enable(csi_chan->mipi); 308 if (ret < 0) { 309 dev_err(csi->dev, 310 "failed to enable MIPI pads: %d\n", ret); 311 goto rpm_put; 312 } 313 314 /* 315 * CSI MIPI pads PULLUP, PULLDN and TERM impedances need to 316 * be calibrated after power on. 317 * So, trigger the calibration start here and results will 318 * be latched and applied to the pads when link is in LP11 319 * state during start of sensor streaming. 320 */ 321 ret = tegra_mipi_start_calibration(csi_chan->mipi); 322 if (ret < 0) { 323 dev_err(csi->dev, 324 "failed to start MIPI calibration: %d\n", ret); 325 goto disable_mipi; 326 } 327 } 328 329 csi_chan->pg_mode = chan->pg_mode; 330 331 /* 332 * Tegra CSI receiver can detect the first LP to HS transition. 333 * So, start the CSI stream-on prior to sensor stream-on and 334 * vice-versa for stream-off. 335 */ 336 ret = csi->ops->csi_start_streaming(csi_chan); 337 if (ret < 0) 338 goto finish_calibration; 339 340 if (csi_chan->mipi) { 341 struct v4l2_subdev *src_subdev; 342 /* 343 * TRM has incorrectly documented to wait for done status from 344 * calibration logic after CSI interface power on. 345 * As per the design, calibration results are latched and applied 346 * to the pads only when the link is in LP11 state which will happen 347 * during the sensor stream-on. 348 * CSI subdev stream-on triggers start of MIPI pads calibration. 349 * Wait for calibration to finish here after sensor subdev stream-on. 350 */ 351 src_subdev = tegra_channel_get_remote_source_subdev(chan); 352 ret = v4l2_subdev_call(src_subdev, video, s_stream, true); 353 354 if (ret < 0 && ret != -ENOIOCTLCMD) 355 goto disable_csi_stream; 356 357 err = tegra_mipi_finish_calibration(csi_chan->mipi); 358 if (err < 0) 359 dev_warn(csi->dev, "MIPI calibration failed: %d\n", err); 360 } 361 362 return 0; 363 364 disable_csi_stream: 365 csi->ops->csi_stop_streaming(csi_chan); 366 finish_calibration: 367 if (csi_chan->mipi) 368 tegra_mipi_finish_calibration(csi_chan->mipi); 369 disable_mipi: 370 if (csi_chan->mipi) { 371 err = tegra_mipi_disable(csi_chan->mipi); 372 if (err < 0) 373 dev_err(csi->dev, 374 "failed to disable MIPI pads: %d\n", err); 375 } 376 377 rpm_put: 378 pm_runtime_put(csi->dev); 379 return ret; 380 } 381 382 static int tegra_csi_disable_stream(struct v4l2_subdev *subdev) 383 { 384 struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); 385 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 386 struct tegra_csi *csi = csi_chan->csi; 387 int err; 388 389 /* 390 * Stream-off subdevices in reverse order to stream-on. 391 * Remote source subdev in TPG mode is same as CSI subdev. 392 */ 393 if (csi_chan->mipi) { 394 struct v4l2_subdev *src_subdev; 395 396 src_subdev = tegra_channel_get_remote_source_subdev(chan); 397 err = v4l2_subdev_call(src_subdev, video, s_stream, false); 398 if (err < 0 && err != -ENOIOCTLCMD) 399 dev_err_probe(csi->dev, err, "source subdev stream off failed\n"); 400 } 401 402 csi->ops->csi_stop_streaming(csi_chan); 403 404 if (csi_chan->mipi) { 405 err = tegra_mipi_disable(csi_chan->mipi); 406 if (err < 0) 407 dev_err(csi->dev, 408 "failed to disable MIPI pads: %d\n", err); 409 } 410 411 pm_runtime_put(csi->dev); 412 413 return 0; 414 } 415 416 static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) 417 { 418 int ret; 419 420 if (enable) 421 ret = tegra_csi_enable_stream(subdev); 422 else 423 ret = tegra_csi_disable_stream(subdev); 424 425 return ret; 426 } 427 428 /* 429 * V4L2 Subdevice Operations 430 */ 431 static const struct v4l2_subdev_video_ops tegra_csi_video_ops = { 432 .s_stream = tegra_csi_s_stream, 433 .g_frame_interval = tegra_csi_g_frame_interval, 434 .s_frame_interval = tegra_csi_g_frame_interval, 435 }; 436 437 static const struct v4l2_subdev_pad_ops tegra_csi_pad_ops = { 438 .enum_mbus_code = csi_enum_bus_code, 439 .enum_frame_size = csi_enum_framesizes, 440 .enum_frame_interval = csi_enum_frameintervals, 441 .get_fmt = csi_get_format, 442 .set_fmt = csi_set_format, 443 }; 444 445 static const struct v4l2_subdev_ops tegra_csi_ops = { 446 .video = &tegra_csi_video_ops, 447 .pad = &tegra_csi_pad_ops, 448 }; 449 450 static int tegra_csi_channel_alloc(struct tegra_csi *csi, 451 struct device_node *node, 452 unsigned int port_num, unsigned int lanes, 453 unsigned int num_pads) 454 { 455 struct tegra_csi_channel *chan; 456 int ret = 0, i; 457 458 chan = kzalloc(sizeof(*chan), GFP_KERNEL); 459 if (!chan) 460 return -ENOMEM; 461 462 list_add_tail(&chan->list, &csi->csi_chans); 463 chan->csi = csi; 464 /* 465 * Each CSI brick has maximum of 4 lanes. 466 * For lanes more than 4, use multiple of immediate CSI bricks as gang. 467 */ 468 if (lanes <= CSI_LANES_PER_BRICK) { 469 chan->numlanes = lanes; 470 chan->numgangports = 1; 471 } else { 472 chan->numlanes = CSI_LANES_PER_BRICK; 473 chan->numgangports = lanes / CSI_LANES_PER_BRICK; 474 } 475 476 for (i = 0; i < chan->numgangports; i++) 477 chan->csi_port_nums[i] = port_num + i * CSI_PORTS_PER_BRICK; 478 479 chan->of_node = of_node_get(node); 480 chan->numpads = num_pads; 481 if (num_pads & 0x2) { 482 chan->pads[0].flags = MEDIA_PAD_FL_SINK; 483 chan->pads[1].flags = MEDIA_PAD_FL_SOURCE; 484 } else { 485 chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; 486 } 487 488 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 489 return 0; 490 491 chan->mipi = tegra_mipi_request(csi->dev, node); 492 if (IS_ERR(chan->mipi)) { 493 ret = PTR_ERR(chan->mipi); 494 chan->mipi = NULL; 495 dev_err(csi->dev, "failed to get mipi device: %d\n", ret); 496 } 497 498 return ret; 499 } 500 501 static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) 502 { 503 struct device_node *node = csi->dev->of_node; 504 unsigned int port_num; 505 unsigned int tpg_channels = csi->soc->csi_max_channels; 506 int ret; 507 508 /* allocate CSI channel for each CSI x2 ports */ 509 for (port_num = 0; port_num < tpg_channels; port_num++) { 510 ret = tegra_csi_channel_alloc(csi, node, port_num, 2, 1); 511 if (ret < 0) 512 return ret; 513 } 514 515 return 0; 516 } 517 518 static int tegra_csi_channels_alloc(struct tegra_csi *csi) 519 { 520 struct device_node *node = csi->dev->of_node; 521 struct v4l2_fwnode_endpoint v4l2_ep = { 522 .bus_type = V4L2_MBUS_CSI2_DPHY 523 }; 524 struct fwnode_handle *fwh; 525 struct device_node *channel; 526 struct device_node *ep; 527 unsigned int lanes, portno, num_pads; 528 int ret; 529 530 for_each_child_of_node(node, channel) { 531 if (!of_node_name_eq(channel, "channel")) 532 continue; 533 534 ret = of_property_read_u32(channel, "reg", &portno); 535 if (ret < 0) 536 continue; 537 538 if (portno >= csi->soc->csi_max_channels) { 539 dev_err(csi->dev, "invalid port num %d for %pOF\n", 540 portno, channel); 541 ret = -EINVAL; 542 goto err_node_put; 543 } 544 545 ep = of_graph_get_endpoint_by_regs(channel, 0, 0); 546 if (!ep) 547 continue; 548 549 fwh = of_fwnode_handle(ep); 550 ret = v4l2_fwnode_endpoint_parse(fwh, &v4l2_ep); 551 of_node_put(ep); 552 if (ret) { 553 dev_err(csi->dev, 554 "failed to parse v4l2 endpoint for %pOF: %d\n", 555 channel, ret); 556 goto err_node_put; 557 } 558 559 lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; 560 /* 561 * Each CSI brick has maximum 4 data lanes. 562 * For lanes more than 4, validate lanes to be multiple of 4 563 * so multiple of consecutive CSI bricks can be ganged up for 564 * streaming. 565 */ 566 if (!lanes || ((lanes & (lanes - 1)) != 0) || 567 (lanes > CSI_LANES_PER_BRICK && ((portno & 1) != 0))) { 568 dev_err(csi->dev, "invalid data-lanes %d for %pOF\n", 569 lanes, channel); 570 ret = -EINVAL; 571 goto err_node_put; 572 } 573 574 num_pads = of_graph_get_endpoint_count(channel); 575 if (num_pads == TEGRA_CSI_PADS_NUM) { 576 ret = tegra_csi_channel_alloc(csi, channel, portno, 577 lanes, num_pads); 578 if (ret < 0) 579 goto err_node_put; 580 } 581 } 582 583 return 0; 584 585 err_node_put: 586 of_node_put(channel); 587 return ret; 588 } 589 590 static int tegra_csi_channel_init(struct tegra_csi_channel *chan) 591 { 592 struct tegra_csi *csi = chan->csi; 593 struct v4l2_subdev *subdev; 594 int ret; 595 596 /* initialize the default format */ 597 chan->format.code = MEDIA_BUS_FMT_SRGGB10_1X10; 598 chan->format.field = V4L2_FIELD_NONE; 599 chan->format.colorspace = V4L2_COLORSPACE_SRGB; 600 chan->format.width = TEGRA_DEF_WIDTH; 601 chan->format.height = TEGRA_DEF_HEIGHT; 602 csi_chan_update_blank_intervals(chan, chan->format.code, 603 chan->format.width, 604 chan->format.height); 605 /* initialize V4L2 subdevice and media entity */ 606 subdev = &chan->subdev; 607 v4l2_subdev_init(subdev, &tegra_csi_ops); 608 subdev->dev = csi->dev; 609 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 610 snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg", 611 chan->csi_port_nums[0]); 612 else 613 snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s", 614 kbasename(chan->of_node->full_name)); 615 616 v4l2_set_subdevdata(subdev, chan); 617 subdev->fwnode = of_fwnode_handle(chan->of_node); 618 subdev->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 619 620 /* initialize media entity pads */ 621 ret = media_entity_pads_init(&subdev->entity, chan->numpads, 622 chan->pads); 623 if (ret < 0) { 624 dev_err(csi->dev, 625 "failed to initialize media entity: %d\n", ret); 626 subdev->dev = NULL; 627 return ret; 628 } 629 630 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { 631 ret = v4l2_async_register_subdev(subdev); 632 if (ret < 0) { 633 dev_err(csi->dev, 634 "failed to register subdev: %d\n", ret); 635 return ret; 636 } 637 } 638 639 return 0; 640 } 641 642 void tegra_csi_error_recover(struct v4l2_subdev *sd) 643 { 644 struct tegra_csi_channel *csi_chan = to_csi_chan(sd); 645 struct tegra_csi *csi = csi_chan->csi; 646 647 /* stop streaming during error recovery */ 648 csi->ops->csi_stop_streaming(csi_chan); 649 csi->ops->csi_err_recover(csi_chan); 650 csi->ops->csi_start_streaming(csi_chan); 651 } 652 653 static int tegra_csi_channels_init(struct tegra_csi *csi) 654 { 655 struct tegra_csi_channel *chan; 656 int ret; 657 658 list_for_each_entry(chan, &csi->csi_chans, list) { 659 ret = tegra_csi_channel_init(chan); 660 if (ret) { 661 dev_err(csi->dev, 662 "failed to initialize channel-%d: %d\n", 663 chan->csi_port_nums[0], ret); 664 return ret; 665 } 666 } 667 668 return 0; 669 } 670 671 static void tegra_csi_channels_cleanup(struct tegra_csi *csi) 672 { 673 struct v4l2_subdev *subdev; 674 struct tegra_csi_channel *chan, *tmp; 675 676 list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { 677 if (chan->mipi) 678 tegra_mipi_free(chan->mipi); 679 680 subdev = &chan->subdev; 681 if (subdev->dev) { 682 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 683 v4l2_async_unregister_subdev(subdev); 684 media_entity_cleanup(&subdev->entity); 685 } 686 687 of_node_put(chan->of_node); 688 list_del(&chan->list); 689 kfree(chan); 690 } 691 } 692 693 static int __maybe_unused csi_runtime_suspend(struct device *dev) 694 { 695 struct tegra_csi *csi = dev_get_drvdata(dev); 696 697 clk_bulk_disable_unprepare(csi->soc->num_clks, csi->clks); 698 699 return 0; 700 } 701 702 static int __maybe_unused csi_runtime_resume(struct device *dev) 703 { 704 struct tegra_csi *csi = dev_get_drvdata(dev); 705 int ret; 706 707 ret = clk_bulk_prepare_enable(csi->soc->num_clks, csi->clks); 708 if (ret < 0) { 709 dev_err(csi->dev, "failed to enable clocks: %d\n", ret); 710 return ret; 711 } 712 713 return 0; 714 } 715 716 static int tegra_csi_init(struct host1x_client *client) 717 { 718 struct tegra_csi *csi = host1x_client_to_csi(client); 719 struct tegra_video_device *vid = dev_get_drvdata(client->host); 720 int ret; 721 722 INIT_LIST_HEAD(&csi->csi_chans); 723 724 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 725 ret = tegra_csi_tpg_channels_alloc(csi); 726 else 727 ret = tegra_csi_channels_alloc(csi); 728 if (ret < 0) { 729 dev_err(csi->dev, 730 "failed to allocate channels: %d\n", ret); 731 goto cleanup; 732 } 733 734 ret = tegra_csi_channels_init(csi); 735 if (ret < 0) 736 goto cleanup; 737 738 vid->csi = csi; 739 740 return 0; 741 742 cleanup: 743 tegra_csi_channels_cleanup(csi); 744 return ret; 745 } 746 747 static int tegra_csi_exit(struct host1x_client *client) 748 { 749 struct tegra_csi *csi = host1x_client_to_csi(client); 750 751 tegra_csi_channels_cleanup(csi); 752 753 return 0; 754 } 755 756 static const struct host1x_client_ops csi_client_ops = { 757 .init = tegra_csi_init, 758 .exit = tegra_csi_exit, 759 }; 760 761 static int tegra_csi_probe(struct platform_device *pdev) 762 { 763 struct tegra_csi *csi; 764 unsigned int i; 765 int ret; 766 767 csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); 768 if (!csi) 769 return -ENOMEM; 770 771 csi->iomem = devm_platform_ioremap_resource(pdev, 0); 772 if (IS_ERR(csi->iomem)) 773 return PTR_ERR(csi->iomem); 774 775 csi->soc = of_device_get_match_data(&pdev->dev); 776 777 csi->clks = devm_kcalloc(&pdev->dev, csi->soc->num_clks, 778 sizeof(*csi->clks), GFP_KERNEL); 779 if (!csi->clks) 780 return -ENOMEM; 781 782 for (i = 0; i < csi->soc->num_clks; i++) 783 csi->clks[i].id = csi->soc->clk_names[i]; 784 785 ret = devm_clk_bulk_get(&pdev->dev, csi->soc->num_clks, csi->clks); 786 if (ret) { 787 dev_err(&pdev->dev, "failed to get the clocks: %d\n", ret); 788 return ret; 789 } 790 791 if (!pdev->dev.pm_domain) { 792 ret = -ENOENT; 793 dev_warn(&pdev->dev, "PM domain is not attached: %d\n", ret); 794 return ret; 795 } 796 797 csi->dev = &pdev->dev; 798 csi->ops = csi->soc->ops; 799 platform_set_drvdata(pdev, csi); 800 pm_runtime_enable(&pdev->dev); 801 802 /* initialize host1x interface */ 803 INIT_LIST_HEAD(&csi->client.list); 804 csi->client.ops = &csi_client_ops; 805 csi->client.dev = &pdev->dev; 806 807 ret = host1x_client_register(&csi->client); 808 if (ret < 0) { 809 dev_err(&pdev->dev, 810 "failed to register host1x client: %d\n", ret); 811 goto rpm_disable; 812 } 813 814 return 0; 815 816 rpm_disable: 817 pm_runtime_disable(&pdev->dev); 818 return ret; 819 } 820 821 static int tegra_csi_remove(struct platform_device *pdev) 822 { 823 struct tegra_csi *csi = platform_get_drvdata(pdev); 824 825 host1x_client_unregister(&csi->client); 826 827 pm_runtime_disable(&pdev->dev); 828 829 return 0; 830 } 831 832 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 833 extern const struct tegra_csi_soc tegra210_csi_soc; 834 #endif 835 836 static const struct of_device_id tegra_csi_of_id_table[] = { 837 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 838 { .compatible = "nvidia,tegra210-csi", .data = &tegra210_csi_soc }, 839 #endif 840 { } 841 }; 842 MODULE_DEVICE_TABLE(of, tegra_csi_of_id_table); 843 844 static const struct dev_pm_ops tegra_csi_pm_ops = { 845 SET_RUNTIME_PM_OPS(csi_runtime_suspend, csi_runtime_resume, NULL) 846 }; 847 848 struct platform_driver tegra_csi_driver = { 849 .driver = { 850 .name = "tegra-csi", 851 .of_match_table = tegra_csi_of_id_table, 852 .pm = &tegra_csi_pm_ops, 853 }, 854 .probe = tegra_csi_probe, 855 .remove = tegra_csi_remove, 856 }; 857