1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk/tegra.h> 8 #include <linux/device.h> 9 #include <linux/host1x.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_graph.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 17 #include <media/v4l2-fwnode.h> 18 19 #include "csi.h" 20 #include "video.h" 21 22 #define MHZ 1000000 23 24 static inline struct tegra_csi * 25 host1x_client_to_csi(struct host1x_client *client) 26 { 27 return container_of(client, struct tegra_csi, client); 28 } 29 30 static inline struct tegra_csi_channel *to_csi_chan(struct v4l2_subdev *subdev) 31 { 32 return container_of(subdev, struct tegra_csi_channel, subdev); 33 } 34 35 /* 36 * CSI is a separate subdevice which has 6 source pads to generate 37 * test pattern. CSI subdevice pad ops are used only for TPG and 38 * allows below TPG formats. 39 */ 40 static const struct v4l2_mbus_framefmt tegra_csi_tpg_fmts[] = { 41 { 42 TEGRA_DEF_WIDTH, 43 TEGRA_DEF_HEIGHT, 44 MEDIA_BUS_FMT_SRGGB10_1X10, 45 V4L2_FIELD_NONE, 46 V4L2_COLORSPACE_SRGB 47 }, 48 { 49 TEGRA_DEF_WIDTH, 50 TEGRA_DEF_HEIGHT, 51 MEDIA_BUS_FMT_RGB888_1X32_PADHI, 52 V4L2_FIELD_NONE, 53 V4L2_COLORSPACE_SRGB 54 }, 55 }; 56 57 static const struct v4l2_frmsize_discrete tegra_csi_tpg_sizes[] = { 58 { 1280, 720 }, 59 { 1920, 1080 }, 60 { 3840, 2160 }, 61 }; 62 63 /* 64 * V4L2 Subdevice Pad Operations 65 */ 66 static int csi_enum_bus_code(struct v4l2_subdev *subdev, 67 struct v4l2_subdev_pad_config *cfg, 68 struct v4l2_subdev_mbus_code_enum *code) 69 { 70 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 71 return -ENOIOCTLCMD; 72 73 if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) 74 return -EINVAL; 75 76 code->code = tegra_csi_tpg_fmts[code->index].code; 77 78 return 0; 79 } 80 81 static int csi_get_format(struct v4l2_subdev *subdev, 82 struct v4l2_subdev_pad_config *cfg, 83 struct v4l2_subdev_format *fmt) 84 { 85 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 86 87 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 88 return -ENOIOCTLCMD; 89 90 fmt->format = csi_chan->format; 91 92 return 0; 93 } 94 95 static int csi_get_frmrate_table_index(struct tegra_csi *csi, u32 code, 96 u32 width, u32 height) 97 { 98 const struct tpg_framerate *frmrate; 99 unsigned int i; 100 101 frmrate = csi->soc->tpg_frmrate_table; 102 for (i = 0; i < csi->soc->tpg_frmrate_table_size; i++) { 103 if (frmrate[i].code == code && 104 frmrate[i].frmsize.width == width && 105 frmrate[i].frmsize.height == height) { 106 return i; 107 } 108 } 109 110 return -EINVAL; 111 } 112 113 static void csi_chan_update_blank_intervals(struct tegra_csi_channel *csi_chan, 114 u32 code, u32 width, u32 height) 115 { 116 struct tegra_csi *csi = csi_chan->csi; 117 const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table; 118 int index; 119 120 index = csi_get_frmrate_table_index(csi_chan->csi, code, 121 width, height); 122 if (index >= 0) { 123 csi_chan->h_blank = frmrate[index].h_blank; 124 csi_chan->v_blank = frmrate[index].v_blank; 125 csi_chan->framerate = frmrate[index].framerate; 126 } 127 } 128 129 static int csi_enum_framesizes(struct v4l2_subdev *subdev, 130 struct v4l2_subdev_pad_config *cfg, 131 struct v4l2_subdev_frame_size_enum *fse) 132 { 133 unsigned int i; 134 135 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 136 return -ENOIOCTLCMD; 137 138 if (fse->index >= ARRAY_SIZE(tegra_csi_tpg_sizes)) 139 return -EINVAL; 140 141 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++) 142 if (fse->code == tegra_csi_tpg_fmts[i].code) 143 break; 144 145 if (i == ARRAY_SIZE(tegra_csi_tpg_fmts)) 146 return -EINVAL; 147 148 fse->min_width = tegra_csi_tpg_sizes[fse->index].width; 149 fse->max_width = tegra_csi_tpg_sizes[fse->index].width; 150 fse->min_height = tegra_csi_tpg_sizes[fse->index].height; 151 fse->max_height = tegra_csi_tpg_sizes[fse->index].height; 152 153 return 0; 154 } 155 156 static int csi_enum_frameintervals(struct v4l2_subdev *subdev, 157 struct v4l2_subdev_pad_config *cfg, 158 struct v4l2_subdev_frame_interval_enum *fie) 159 { 160 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 161 struct tegra_csi *csi = csi_chan->csi; 162 const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table; 163 int index; 164 165 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 166 return -ENOIOCTLCMD; 167 168 /* one framerate per format and resolution */ 169 if (fie->index > 0) 170 return -EINVAL; 171 172 index = csi_get_frmrate_table_index(csi_chan->csi, fie->code, 173 fie->width, fie->height); 174 if (index < 0) 175 return -EINVAL; 176 177 fie->interval.numerator = 1; 178 fie->interval.denominator = frmrate[index].framerate; 179 180 return 0; 181 } 182 183 static int csi_set_format(struct v4l2_subdev *subdev, 184 struct v4l2_subdev_pad_config *cfg, 185 struct v4l2_subdev_format *fmt) 186 { 187 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 188 struct v4l2_mbus_framefmt *format = &fmt->format; 189 const struct v4l2_frmsize_discrete *sizes; 190 unsigned int i; 191 192 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 193 return -ENOIOCTLCMD; 194 195 sizes = v4l2_find_nearest_size(tegra_csi_tpg_sizes, 196 ARRAY_SIZE(tegra_csi_tpg_sizes), 197 width, height, 198 format->width, format->width); 199 format->width = sizes->width; 200 format->height = sizes->height; 201 202 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++) 203 if (format->code == tegra_csi_tpg_fmts[i].code) 204 break; 205 206 if (i == ARRAY_SIZE(tegra_csi_tpg_fmts)) 207 i = 0; 208 209 format->code = tegra_csi_tpg_fmts[i].code; 210 format->field = V4L2_FIELD_NONE; 211 212 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 213 return 0; 214 215 /* update blanking intervals from frame rate table and format */ 216 csi_chan_update_blank_intervals(csi_chan, format->code, 217 format->width, format->height); 218 csi_chan->format = *format; 219 220 return 0; 221 } 222 223 /* 224 * V4L2 Subdevice Video Operations 225 */ 226 static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, 227 struct v4l2_subdev_frame_interval *vfi) 228 { 229 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 230 231 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 232 return -ENOIOCTLCMD; 233 234 vfi->interval.numerator = 1; 235 vfi->interval.denominator = csi_chan->framerate; 236 237 return 0; 238 } 239 240 static unsigned int csi_get_pixel_rate(struct tegra_csi_channel *csi_chan) 241 { 242 struct tegra_vi_channel *chan; 243 struct v4l2_subdev *src_subdev; 244 struct v4l2_ctrl *ctrl; 245 246 chan = v4l2_get_subdev_hostdata(&csi_chan->subdev); 247 src_subdev = tegra_channel_get_remote_source_subdev(chan); 248 ctrl = v4l2_ctrl_find(src_subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); 249 if (ctrl) 250 return v4l2_ctrl_g_ctrl_int64(ctrl); 251 252 return 0; 253 } 254 255 void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, 256 u8 csi_port_num, 257 u8 *clk_settle_time, 258 u8 *ths_settle_time) 259 { 260 struct tegra_csi *csi = csi_chan->csi; 261 unsigned int cil_clk_mhz; 262 unsigned int pix_clk_mhz; 263 int clk_idx = (csi_port_num >> 1) + 1; 264 265 cil_clk_mhz = clk_get_rate(csi->clks[clk_idx].clk) / MHZ; 266 pix_clk_mhz = csi_get_pixel_rate(csi_chan) / MHZ; 267 268 /* 269 * CLK Settle time is the interval during which HS receiver should 270 * ignore any clock lane HS transitions, starting from the beginning 271 * of T-CLK-PREPARE. 272 * Per DPHY specification, T-CLK-SETTLE should be between 95ns ~ 300ns 273 * 274 * 95ns < (clk-settle-programmed + 7) * lp clk period < 300ns 275 * midpoint = 197.5 ns 276 */ 277 *clk_settle_time = ((95 + 300) * cil_clk_mhz - 14000) / 2000; 278 279 /* 280 * THS Settle time is the interval during which HS receiver should 281 * ignore any data lane HS transitions, starting from the beginning 282 * of THS-PREPARE. 283 * 284 * Per DPHY specification, T-HS-SETTLE should be between 85ns + 6UI 285 * and 145ns+10UI. 286 * 85ns + 6UI < (Ths-settle-prog + 5) * lp_clk_period < 145ns + 10UI 287 * midpoint = 115ns + 8UI 288 */ 289 if (pix_clk_mhz) 290 *ths_settle_time = (115 * cil_clk_mhz + 8000 * cil_clk_mhz 291 / (2 * pix_clk_mhz) - 5000) / 1000; 292 } 293 294 static int tegra_csi_enable_stream(struct v4l2_subdev *subdev) 295 { 296 struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); 297 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 298 struct tegra_csi *csi = csi_chan->csi; 299 int ret, err; 300 301 ret = pm_runtime_get_sync(csi->dev); 302 if (ret < 0) { 303 dev_err(csi->dev, "failed to get runtime PM: %d\n", ret); 304 pm_runtime_put_noidle(csi->dev); 305 return ret; 306 } 307 308 if (csi_chan->mipi) { 309 ret = tegra_mipi_enable(csi_chan->mipi); 310 if (ret < 0) { 311 dev_err(csi->dev, 312 "failed to enable MIPI pads: %d\n", ret); 313 goto rpm_put; 314 } 315 316 /* 317 * CSI MIPI pads PULLUP, PULLDN and TERM impedances need to 318 * be calibrated after power on. 319 * So, trigger the calibration start here and results will 320 * be latched and applied to the pads when link is in LP11 321 * state during start of sensor streaming. 322 */ 323 ret = tegra_mipi_start_calibration(csi_chan->mipi); 324 if (ret < 0) { 325 dev_err(csi->dev, 326 "failed to start MIPI calibration: %d\n", ret); 327 goto disable_mipi; 328 } 329 } 330 331 csi_chan->pg_mode = chan->pg_mode; 332 ret = csi->ops->csi_start_streaming(csi_chan); 333 if (ret < 0) 334 goto finish_calibration; 335 336 return 0; 337 338 finish_calibration: 339 if (csi_chan->mipi) 340 tegra_mipi_finish_calibration(csi_chan->mipi); 341 disable_mipi: 342 if (csi_chan->mipi) { 343 err = tegra_mipi_disable(csi_chan->mipi); 344 if (err < 0) 345 dev_err(csi->dev, 346 "failed to disable MIPI pads: %d\n", err); 347 } 348 349 rpm_put: 350 pm_runtime_put(csi->dev); 351 return ret; 352 } 353 354 static int tegra_csi_disable_stream(struct v4l2_subdev *subdev) 355 { 356 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 357 struct tegra_csi *csi = csi_chan->csi; 358 int err; 359 360 csi->ops->csi_stop_streaming(csi_chan); 361 362 if (csi_chan->mipi) { 363 err = tegra_mipi_disable(csi_chan->mipi); 364 if (err < 0) 365 dev_err(csi->dev, 366 "failed to disable MIPI pads: %d\n", err); 367 } 368 369 pm_runtime_put(csi->dev); 370 371 return 0; 372 } 373 374 static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) 375 { 376 int ret; 377 378 if (enable) 379 ret = tegra_csi_enable_stream(subdev); 380 else 381 ret = tegra_csi_disable_stream(subdev); 382 383 return ret; 384 } 385 386 /* 387 * V4L2 Subdevice Operations 388 */ 389 static const struct v4l2_subdev_video_ops tegra_csi_video_ops = { 390 .s_stream = tegra_csi_s_stream, 391 .g_frame_interval = tegra_csi_g_frame_interval, 392 .s_frame_interval = tegra_csi_g_frame_interval, 393 }; 394 395 static const struct v4l2_subdev_pad_ops tegra_csi_pad_ops = { 396 .enum_mbus_code = csi_enum_bus_code, 397 .enum_frame_size = csi_enum_framesizes, 398 .enum_frame_interval = csi_enum_frameintervals, 399 .get_fmt = csi_get_format, 400 .set_fmt = csi_set_format, 401 }; 402 403 static const struct v4l2_subdev_ops tegra_csi_ops = { 404 .video = &tegra_csi_video_ops, 405 .pad = &tegra_csi_pad_ops, 406 }; 407 408 static int tegra_csi_channel_alloc(struct tegra_csi *csi, 409 struct device_node *node, 410 unsigned int port_num, unsigned int lanes, 411 unsigned int num_pads) 412 { 413 struct tegra_csi_channel *chan; 414 int ret = 0, i; 415 416 chan = kzalloc(sizeof(*chan), GFP_KERNEL); 417 if (!chan) 418 return -ENOMEM; 419 420 list_add_tail(&chan->list, &csi->csi_chans); 421 chan->csi = csi; 422 /* 423 * Each CSI brick has maximum of 4 lanes. 424 * For lanes more than 4, use multiple of immediate CSI bricks as gang. 425 */ 426 if (lanes <= CSI_LANES_PER_BRICK) { 427 chan->numlanes = lanes; 428 chan->numgangports = 1; 429 } else { 430 chan->numlanes = CSI_LANES_PER_BRICK; 431 chan->numgangports = lanes / CSI_LANES_PER_BRICK; 432 } 433 434 for (i = 0; i < chan->numgangports; i++) 435 chan->csi_port_nums[i] = port_num + i * CSI_PORTS_PER_BRICK; 436 437 chan->of_node = node; 438 chan->numpads = num_pads; 439 if (num_pads & 0x2) { 440 chan->pads[0].flags = MEDIA_PAD_FL_SINK; 441 chan->pads[1].flags = MEDIA_PAD_FL_SOURCE; 442 } else { 443 chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; 444 } 445 446 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 447 return 0; 448 449 chan->mipi = tegra_mipi_request(csi->dev, node); 450 if (IS_ERR(chan->mipi)) { 451 ret = PTR_ERR(chan->mipi); 452 dev_err(csi->dev, "failed to get mipi device: %d\n", ret); 453 } 454 455 return ret; 456 } 457 458 static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) 459 { 460 struct device_node *node = csi->dev->of_node; 461 unsigned int port_num; 462 unsigned int tpg_channels = csi->soc->csi_max_channels; 463 int ret; 464 465 /* allocate CSI channel for each CSI x2 ports */ 466 for (port_num = 0; port_num < tpg_channels; port_num++) { 467 ret = tegra_csi_channel_alloc(csi, node, port_num, 2, 1); 468 if (ret < 0) 469 return ret; 470 } 471 472 return 0; 473 } 474 475 static int tegra_csi_channels_alloc(struct tegra_csi *csi) 476 { 477 struct device_node *node = csi->dev->of_node; 478 struct v4l2_fwnode_endpoint v4l2_ep = { 479 .bus_type = V4L2_MBUS_CSI2_DPHY 480 }; 481 struct fwnode_handle *fwh; 482 struct device_node *channel; 483 struct device_node *ep; 484 unsigned int lanes, portno, num_pads; 485 int ret; 486 487 for_each_child_of_node(node, channel) { 488 if (!of_node_name_eq(channel, "channel")) 489 continue; 490 491 ret = of_property_read_u32(channel, "reg", &portno); 492 if (ret < 0) 493 continue; 494 495 if (portno >= csi->soc->csi_max_channels) { 496 dev_err(csi->dev, "invalid port num %d for %pOF\n", 497 portno, channel); 498 ret = -EINVAL; 499 goto err_node_put; 500 } 501 502 ep = of_graph_get_endpoint_by_regs(channel, 0, 0); 503 if (!ep) 504 continue; 505 506 fwh = of_fwnode_handle(ep); 507 ret = v4l2_fwnode_endpoint_parse(fwh, &v4l2_ep); 508 of_node_put(ep); 509 if (ret) { 510 dev_err(csi->dev, 511 "failed to parse v4l2 endpoint for %pOF: %d\n", 512 channel, ret); 513 goto err_node_put; 514 } 515 516 lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; 517 /* 518 * Each CSI brick has maximum 4 data lanes. 519 * For lanes more than 4, validate lanes to be multiple of 4 520 * so multiple of consecutive CSI bricks can be ganged up for 521 * streaming. 522 */ 523 if (!lanes || ((lanes & (lanes - 1)) != 0) || 524 (lanes > CSI_LANES_PER_BRICK && ((portno & 1) != 0))) { 525 dev_err(csi->dev, "invalid data-lanes %d for %pOF\n", 526 lanes, channel); 527 ret = -EINVAL; 528 goto err_node_put; 529 } 530 531 num_pads = of_graph_get_endpoint_count(channel); 532 if (num_pads == TEGRA_CSI_PADS_NUM) { 533 ret = tegra_csi_channel_alloc(csi, channel, portno, 534 lanes, num_pads); 535 if (ret < 0) 536 goto err_node_put; 537 } 538 } 539 540 return 0; 541 542 err_node_put: 543 of_node_put(channel); 544 return ret; 545 } 546 547 static int tegra_csi_channel_init(struct tegra_csi_channel *chan) 548 { 549 struct tegra_csi *csi = chan->csi; 550 struct v4l2_subdev *subdev; 551 int ret; 552 553 /* initialize the default format */ 554 chan->format.code = MEDIA_BUS_FMT_SRGGB10_1X10; 555 chan->format.field = V4L2_FIELD_NONE; 556 chan->format.colorspace = V4L2_COLORSPACE_SRGB; 557 chan->format.width = TEGRA_DEF_WIDTH; 558 chan->format.height = TEGRA_DEF_HEIGHT; 559 csi_chan_update_blank_intervals(chan, chan->format.code, 560 chan->format.width, 561 chan->format.height); 562 /* initialize V4L2 subdevice and media entity */ 563 subdev = &chan->subdev; 564 v4l2_subdev_init(subdev, &tegra_csi_ops); 565 subdev->dev = csi->dev; 566 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 567 snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg", 568 chan->csi_port_nums[0]); 569 else 570 snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s", 571 kbasename(chan->of_node->full_name)); 572 573 v4l2_set_subdevdata(subdev, chan); 574 subdev->fwnode = of_fwnode_handle(chan->of_node); 575 subdev->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 576 577 /* initialize media entity pads */ 578 ret = media_entity_pads_init(&subdev->entity, chan->numpads, 579 chan->pads); 580 if (ret < 0) { 581 dev_err(csi->dev, 582 "failed to initialize media entity: %d\n", ret); 583 subdev->dev = NULL; 584 return ret; 585 } 586 587 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { 588 ret = v4l2_async_register_subdev(subdev); 589 if (ret < 0) { 590 dev_err(csi->dev, 591 "failed to register subdev: %d\n", ret); 592 return ret; 593 } 594 } 595 596 return 0; 597 } 598 599 void tegra_csi_error_recover(struct v4l2_subdev *sd) 600 { 601 struct tegra_csi_channel *csi_chan = to_csi_chan(sd); 602 struct tegra_csi *csi = csi_chan->csi; 603 604 /* stop streaming during error recovery */ 605 csi->ops->csi_stop_streaming(csi_chan); 606 csi->ops->csi_err_recover(csi_chan); 607 csi->ops->csi_start_streaming(csi_chan); 608 } 609 610 static int tegra_csi_channels_init(struct tegra_csi *csi) 611 { 612 struct tegra_csi_channel *chan; 613 int ret; 614 615 list_for_each_entry(chan, &csi->csi_chans, list) { 616 ret = tegra_csi_channel_init(chan); 617 if (ret) { 618 dev_err(csi->dev, 619 "failed to initialize channel-%d: %d\n", 620 chan->csi_port_nums[0], ret); 621 return ret; 622 } 623 } 624 625 return 0; 626 } 627 628 static void tegra_csi_channels_cleanup(struct tegra_csi *csi) 629 { 630 struct v4l2_subdev *subdev; 631 struct tegra_csi_channel *chan, *tmp; 632 633 list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { 634 if (chan->mipi) 635 tegra_mipi_free(chan->mipi); 636 637 subdev = &chan->subdev; 638 if (subdev->dev) { 639 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 640 v4l2_async_unregister_subdev(subdev); 641 media_entity_cleanup(&subdev->entity); 642 } 643 644 list_del(&chan->list); 645 kfree(chan); 646 } 647 } 648 649 static int __maybe_unused csi_runtime_suspend(struct device *dev) 650 { 651 struct tegra_csi *csi = dev_get_drvdata(dev); 652 653 clk_bulk_disable_unprepare(csi->soc->num_clks, csi->clks); 654 655 return 0; 656 } 657 658 static int __maybe_unused csi_runtime_resume(struct device *dev) 659 { 660 struct tegra_csi *csi = dev_get_drvdata(dev); 661 int ret; 662 663 ret = clk_bulk_prepare_enable(csi->soc->num_clks, csi->clks); 664 if (ret < 0) { 665 dev_err(csi->dev, "failed to enable clocks: %d\n", ret); 666 return ret; 667 } 668 669 return 0; 670 } 671 672 static int tegra_csi_init(struct host1x_client *client) 673 { 674 struct tegra_csi *csi = host1x_client_to_csi(client); 675 struct tegra_video_device *vid = dev_get_drvdata(client->host); 676 int ret; 677 678 INIT_LIST_HEAD(&csi->csi_chans); 679 680 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 681 ret = tegra_csi_tpg_channels_alloc(csi); 682 else 683 ret = tegra_csi_channels_alloc(csi); 684 if (ret < 0) { 685 dev_err(csi->dev, 686 "failed to allocate channels: %d\n", ret); 687 goto cleanup; 688 } 689 690 ret = tegra_csi_channels_init(csi); 691 if (ret < 0) 692 goto cleanup; 693 694 vid->csi = csi; 695 696 return 0; 697 698 cleanup: 699 tegra_csi_channels_cleanup(csi); 700 return ret; 701 } 702 703 static int tegra_csi_exit(struct host1x_client *client) 704 { 705 struct tegra_csi *csi = host1x_client_to_csi(client); 706 707 tegra_csi_channels_cleanup(csi); 708 709 return 0; 710 } 711 712 static const struct host1x_client_ops csi_client_ops = { 713 .init = tegra_csi_init, 714 .exit = tegra_csi_exit, 715 }; 716 717 static int tegra_csi_probe(struct platform_device *pdev) 718 { 719 struct tegra_csi *csi; 720 unsigned int i; 721 int ret; 722 723 csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); 724 if (!csi) 725 return -ENOMEM; 726 727 csi->iomem = devm_platform_ioremap_resource(pdev, 0); 728 if (IS_ERR(csi->iomem)) 729 return PTR_ERR(csi->iomem); 730 731 csi->soc = of_device_get_match_data(&pdev->dev); 732 733 csi->clks = devm_kcalloc(&pdev->dev, csi->soc->num_clks, 734 sizeof(*csi->clks), GFP_KERNEL); 735 if (!csi->clks) 736 return -ENOMEM; 737 738 for (i = 0; i < csi->soc->num_clks; i++) 739 csi->clks[i].id = csi->soc->clk_names[i]; 740 741 ret = devm_clk_bulk_get(&pdev->dev, csi->soc->num_clks, csi->clks); 742 if (ret) { 743 dev_err(&pdev->dev, "failed to get the clocks: %d\n", ret); 744 return ret; 745 } 746 747 if (!pdev->dev.pm_domain) { 748 ret = -ENOENT; 749 dev_warn(&pdev->dev, "PM domain is not attached: %d\n", ret); 750 return ret; 751 } 752 753 csi->dev = &pdev->dev; 754 csi->ops = csi->soc->ops; 755 platform_set_drvdata(pdev, csi); 756 pm_runtime_enable(&pdev->dev); 757 758 /* initialize host1x interface */ 759 INIT_LIST_HEAD(&csi->client.list); 760 csi->client.ops = &csi_client_ops; 761 csi->client.dev = &pdev->dev; 762 763 ret = host1x_client_register(&csi->client); 764 if (ret < 0) { 765 dev_err(&pdev->dev, 766 "failed to register host1x client: %d\n", ret); 767 goto rpm_disable; 768 } 769 770 return 0; 771 772 rpm_disable: 773 pm_runtime_disable(&pdev->dev); 774 return ret; 775 } 776 777 static int tegra_csi_remove(struct platform_device *pdev) 778 { 779 struct tegra_csi *csi = platform_get_drvdata(pdev); 780 int err; 781 782 err = host1x_client_unregister(&csi->client); 783 if (err < 0) { 784 dev_err(&pdev->dev, 785 "failed to unregister host1x client: %d\n", err); 786 return err; 787 } 788 789 pm_runtime_disable(&pdev->dev); 790 791 return 0; 792 } 793 794 static const struct of_device_id tegra_csi_of_id_table[] = { 795 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 796 { .compatible = "nvidia,tegra210-csi", .data = &tegra210_csi_soc }, 797 #endif 798 { } 799 }; 800 MODULE_DEVICE_TABLE(of, tegra_csi_of_id_table); 801 802 static const struct dev_pm_ops tegra_csi_pm_ops = { 803 SET_RUNTIME_PM_OPS(csi_runtime_suspend, csi_runtime_resume, NULL) 804 }; 805 806 struct platform_driver tegra_csi_driver = { 807 .driver = { 808 .name = "tegra-csi", 809 .of_match_table = tegra_csi_of_id_table, 810 .pm = &tegra_csi_pm_ops, 811 }, 812 .probe = tegra_csi_probe, 813 .remove = tegra_csi_remove, 814 }; 815