1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk/tegra.h> 8 #include <linux/device.h> 9 #include <linux/host1x.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_graph.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 17 #include <media/v4l2-fwnode.h> 18 19 #include "csi.h" 20 #include "video.h" 21 22 #define MHZ 1000000 23 24 static inline struct tegra_csi * 25 host1x_client_to_csi(struct host1x_client *client) 26 { 27 return container_of(client, struct tegra_csi, client); 28 } 29 30 static inline struct tegra_csi_channel *to_csi_chan(struct v4l2_subdev *subdev) 31 { 32 return container_of(subdev, struct tegra_csi_channel, subdev); 33 } 34 35 /* 36 * CSI is a separate subdevice which has 6 source pads to generate 37 * test pattern. CSI subdevice pad ops are used only for TPG and 38 * allows below TPG formats. 39 */ 40 static const struct v4l2_mbus_framefmt tegra_csi_tpg_fmts[] = { 41 { 42 TEGRA_DEF_WIDTH, 43 TEGRA_DEF_HEIGHT, 44 MEDIA_BUS_FMT_SRGGB10_1X10, 45 V4L2_FIELD_NONE, 46 V4L2_COLORSPACE_SRGB 47 }, 48 { 49 TEGRA_DEF_WIDTH, 50 TEGRA_DEF_HEIGHT, 51 MEDIA_BUS_FMT_RGB888_1X32_PADHI, 52 V4L2_FIELD_NONE, 53 V4L2_COLORSPACE_SRGB 54 }, 55 }; 56 57 static const struct v4l2_frmsize_discrete tegra_csi_tpg_sizes[] = { 58 { 1280, 720 }, 59 { 1920, 1080 }, 60 { 3840, 2160 }, 61 }; 62 63 /* 64 * V4L2 Subdevice Pad Operations 65 */ 66 static int csi_enum_bus_code(struct v4l2_subdev *subdev, 67 struct v4l2_subdev_state *sd_state, 68 struct v4l2_subdev_mbus_code_enum *code) 69 { 70 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 71 return -ENOIOCTLCMD; 72 73 if (code->index >= ARRAY_SIZE(tegra_csi_tpg_fmts)) 74 return -EINVAL; 75 76 code->code = tegra_csi_tpg_fmts[code->index].code; 77 78 return 0; 79 } 80 81 static int csi_get_format(struct v4l2_subdev *subdev, 82 struct v4l2_subdev_state *sd_state, 83 struct v4l2_subdev_format *fmt) 84 { 85 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 86 87 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 88 return -ENOIOCTLCMD; 89 90 fmt->format = csi_chan->format; 91 92 return 0; 93 } 94 95 static int csi_get_frmrate_table_index(struct tegra_csi *csi, u32 code, 96 u32 width, u32 height) 97 { 98 const struct tpg_framerate *frmrate; 99 unsigned int i; 100 101 frmrate = csi->soc->tpg_frmrate_table; 102 for (i = 0; i < csi->soc->tpg_frmrate_table_size; i++) { 103 if (frmrate[i].code == code && 104 frmrate[i].frmsize.width == width && 105 frmrate[i].frmsize.height == height) { 106 return i; 107 } 108 } 109 110 return -EINVAL; 111 } 112 113 static void csi_chan_update_blank_intervals(struct tegra_csi_channel *csi_chan, 114 u32 code, u32 width, u32 height) 115 { 116 struct tegra_csi *csi = csi_chan->csi; 117 const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table; 118 int index; 119 120 index = csi_get_frmrate_table_index(csi_chan->csi, code, 121 width, height); 122 if (index >= 0) { 123 csi_chan->h_blank = frmrate[index].h_blank; 124 csi_chan->v_blank = frmrate[index].v_blank; 125 csi_chan->framerate = frmrate[index].framerate; 126 } 127 } 128 129 static int csi_enum_framesizes(struct v4l2_subdev *subdev, 130 struct v4l2_subdev_state *sd_state, 131 struct v4l2_subdev_frame_size_enum *fse) 132 { 133 unsigned int i; 134 135 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 136 return -ENOIOCTLCMD; 137 138 if (fse->index >= ARRAY_SIZE(tegra_csi_tpg_sizes)) 139 return -EINVAL; 140 141 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++) 142 if (fse->code == tegra_csi_tpg_fmts[i].code) 143 break; 144 145 if (i == ARRAY_SIZE(tegra_csi_tpg_fmts)) 146 return -EINVAL; 147 148 fse->min_width = tegra_csi_tpg_sizes[fse->index].width; 149 fse->max_width = tegra_csi_tpg_sizes[fse->index].width; 150 fse->min_height = tegra_csi_tpg_sizes[fse->index].height; 151 fse->max_height = tegra_csi_tpg_sizes[fse->index].height; 152 153 return 0; 154 } 155 156 static int csi_enum_frameintervals(struct v4l2_subdev *subdev, 157 struct v4l2_subdev_state *sd_state, 158 struct v4l2_subdev_frame_interval_enum *fie) 159 { 160 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 161 struct tegra_csi *csi = csi_chan->csi; 162 const struct tpg_framerate *frmrate = csi->soc->tpg_frmrate_table; 163 int index; 164 165 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 166 return -ENOIOCTLCMD; 167 168 /* one framerate per format and resolution */ 169 if (fie->index > 0) 170 return -EINVAL; 171 172 index = csi_get_frmrate_table_index(csi_chan->csi, fie->code, 173 fie->width, fie->height); 174 if (index < 0) 175 return -EINVAL; 176 177 fie->interval.numerator = 1; 178 fie->interval.denominator = frmrate[index].framerate; 179 180 return 0; 181 } 182 183 static int csi_set_format(struct v4l2_subdev *subdev, 184 struct v4l2_subdev_state *sd_state, 185 struct v4l2_subdev_format *fmt) 186 { 187 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 188 struct v4l2_mbus_framefmt *format = &fmt->format; 189 const struct v4l2_frmsize_discrete *sizes; 190 unsigned int i; 191 192 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 193 return -ENOIOCTLCMD; 194 195 sizes = v4l2_find_nearest_size(tegra_csi_tpg_sizes, 196 ARRAY_SIZE(tegra_csi_tpg_sizes), 197 width, height, 198 format->width, format->width); 199 format->width = sizes->width; 200 format->height = sizes->height; 201 202 for (i = 0; i < ARRAY_SIZE(tegra_csi_tpg_fmts); i++) 203 if (format->code == tegra_csi_tpg_fmts[i].code) 204 break; 205 206 if (i == ARRAY_SIZE(tegra_csi_tpg_fmts)) 207 i = 0; 208 209 format->code = tegra_csi_tpg_fmts[i].code; 210 format->field = V4L2_FIELD_NONE; 211 212 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) 213 return 0; 214 215 /* update blanking intervals from frame rate table and format */ 216 csi_chan_update_blank_intervals(csi_chan, format->code, 217 format->width, format->height); 218 csi_chan->format = *format; 219 220 return 0; 221 } 222 223 /* 224 * V4L2 Subdevice Video Operations 225 */ 226 static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, 227 struct v4l2_subdev_frame_interval *vfi) 228 { 229 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 230 231 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 232 return -ENOIOCTLCMD; 233 234 vfi->interval.numerator = 1; 235 vfi->interval.denominator = csi_chan->framerate; 236 237 return 0; 238 } 239 240 static unsigned int csi_get_pixel_rate(struct tegra_csi_channel *csi_chan) 241 { 242 struct tegra_vi_channel *chan; 243 struct v4l2_subdev *src_subdev; 244 struct v4l2_ctrl *ctrl; 245 246 chan = v4l2_get_subdev_hostdata(&csi_chan->subdev); 247 src_subdev = tegra_channel_get_remote_source_subdev(chan); 248 ctrl = v4l2_ctrl_find(src_subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); 249 if (ctrl) 250 return v4l2_ctrl_g_ctrl_int64(ctrl); 251 252 return 0; 253 } 254 255 void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, 256 u8 csi_port_num, 257 u8 *clk_settle_time, 258 u8 *ths_settle_time) 259 { 260 struct tegra_csi *csi = csi_chan->csi; 261 unsigned int cil_clk_mhz; 262 unsigned int pix_clk_mhz; 263 int clk_idx = (csi_port_num >> 1) + 1; 264 265 cil_clk_mhz = clk_get_rate(csi->clks[clk_idx].clk) / MHZ; 266 pix_clk_mhz = csi_get_pixel_rate(csi_chan) / MHZ; 267 268 /* 269 * CLK Settle time is the interval during which HS receiver should 270 * ignore any clock lane HS transitions, starting from the beginning 271 * of T-CLK-PREPARE. 272 * Per DPHY specification, T-CLK-SETTLE should be between 95ns ~ 300ns 273 * 274 * 95ns < (clk-settle-programmed + 7) * lp clk period < 300ns 275 * midpoint = 197.5 ns 276 */ 277 *clk_settle_time = ((95 + 300) * cil_clk_mhz - 14000) / 2000; 278 279 /* 280 * THS Settle time is the interval during which HS receiver should 281 * ignore any data lane HS transitions, starting from the beginning 282 * of THS-PREPARE. 283 * 284 * Per DPHY specification, T-HS-SETTLE should be between 85ns + 6UI 285 * and 145ns+10UI. 286 * 85ns + 6UI < (Ths-settle-prog + 5) * lp_clk_period < 145ns + 10UI 287 * midpoint = 115ns + 8UI 288 */ 289 if (pix_clk_mhz) 290 *ths_settle_time = (115 * cil_clk_mhz + 8000 * cil_clk_mhz 291 / (2 * pix_clk_mhz) - 5000) / 1000; 292 } 293 294 static int tegra_csi_enable_stream(struct v4l2_subdev *subdev) 295 { 296 struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); 297 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 298 struct tegra_csi *csi = csi_chan->csi; 299 int ret, err; 300 301 ret = pm_runtime_resume_and_get(csi->dev); 302 if (ret < 0) { 303 dev_err(csi->dev, "failed to get runtime PM: %d\n", ret); 304 return ret; 305 } 306 307 if (csi_chan->mipi) { 308 ret = tegra_mipi_enable(csi_chan->mipi); 309 if (ret < 0) { 310 dev_err(csi->dev, 311 "failed to enable MIPI pads: %d\n", ret); 312 goto rpm_put; 313 } 314 315 /* 316 * CSI MIPI pads PULLUP, PULLDN and TERM impedances need to 317 * be calibrated after power on. 318 * So, trigger the calibration start here and results will 319 * be latched and applied to the pads when link is in LP11 320 * state during start of sensor streaming. 321 */ 322 ret = tegra_mipi_start_calibration(csi_chan->mipi); 323 if (ret < 0) { 324 dev_err(csi->dev, 325 "failed to start MIPI calibration: %d\n", ret); 326 goto disable_mipi; 327 } 328 } 329 330 csi_chan->pg_mode = chan->pg_mode; 331 332 /* 333 * Tegra CSI receiver can detect the first LP to HS transition. 334 * So, start the CSI stream-on prior to sensor stream-on and 335 * vice-versa for stream-off. 336 */ 337 ret = csi->ops->csi_start_streaming(csi_chan); 338 if (ret < 0) 339 goto finish_calibration; 340 341 if (csi_chan->mipi) { 342 struct v4l2_subdev *src_subdev; 343 /* 344 * TRM has incorrectly documented to wait for done status from 345 * calibration logic after CSI interface power on. 346 * As per the design, calibration results are latched and applied 347 * to the pads only when the link is in LP11 state which will happen 348 * during the sensor stream-on. 349 * CSI subdev stream-on triggers start of MIPI pads calibration. 350 * Wait for calibration to finish here after sensor subdev stream-on. 351 */ 352 src_subdev = tegra_channel_get_remote_source_subdev(chan); 353 ret = v4l2_subdev_call(src_subdev, video, s_stream, true); 354 355 if (ret < 0 && ret != -ENOIOCTLCMD) 356 goto disable_csi_stream; 357 358 err = tegra_mipi_finish_calibration(csi_chan->mipi); 359 if (err < 0) 360 dev_warn(csi->dev, "MIPI calibration failed: %d\n", err); 361 } 362 363 return 0; 364 365 disable_csi_stream: 366 csi->ops->csi_stop_streaming(csi_chan); 367 finish_calibration: 368 if (csi_chan->mipi) 369 tegra_mipi_finish_calibration(csi_chan->mipi); 370 disable_mipi: 371 if (csi_chan->mipi) { 372 err = tegra_mipi_disable(csi_chan->mipi); 373 if (err < 0) 374 dev_err(csi->dev, 375 "failed to disable MIPI pads: %d\n", err); 376 } 377 378 rpm_put: 379 pm_runtime_put(csi->dev); 380 return ret; 381 } 382 383 static int tegra_csi_disable_stream(struct v4l2_subdev *subdev) 384 { 385 struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); 386 struct tegra_csi_channel *csi_chan = to_csi_chan(subdev); 387 struct tegra_csi *csi = csi_chan->csi; 388 int err; 389 390 /* 391 * Stream-off subdevices in reverse order to stream-on. 392 * Remote source subdev in TPG mode is same as CSI subdev. 393 */ 394 if (csi_chan->mipi) { 395 struct v4l2_subdev *src_subdev; 396 397 src_subdev = tegra_channel_get_remote_source_subdev(chan); 398 err = v4l2_subdev_call(src_subdev, video, s_stream, false); 399 if (err < 0 && err != -ENOIOCTLCMD) 400 dev_err_probe(csi->dev, err, "source subdev stream off failed\n"); 401 } 402 403 csi->ops->csi_stop_streaming(csi_chan); 404 405 if (csi_chan->mipi) { 406 err = tegra_mipi_disable(csi_chan->mipi); 407 if (err < 0) 408 dev_err(csi->dev, 409 "failed to disable MIPI pads: %d\n", err); 410 } 411 412 pm_runtime_put(csi->dev); 413 414 return 0; 415 } 416 417 static int tegra_csi_s_stream(struct v4l2_subdev *subdev, int enable) 418 { 419 int ret; 420 421 if (enable) 422 ret = tegra_csi_enable_stream(subdev); 423 else 424 ret = tegra_csi_disable_stream(subdev); 425 426 return ret; 427 } 428 429 /* 430 * V4L2 Subdevice Operations 431 */ 432 static const struct v4l2_subdev_video_ops tegra_csi_video_ops = { 433 .s_stream = tegra_csi_s_stream, 434 .g_frame_interval = tegra_csi_g_frame_interval, 435 .s_frame_interval = tegra_csi_g_frame_interval, 436 }; 437 438 static const struct v4l2_subdev_pad_ops tegra_csi_pad_ops = { 439 .enum_mbus_code = csi_enum_bus_code, 440 .enum_frame_size = csi_enum_framesizes, 441 .enum_frame_interval = csi_enum_frameintervals, 442 .get_fmt = csi_get_format, 443 .set_fmt = csi_set_format, 444 }; 445 446 static const struct v4l2_subdev_ops tegra_csi_ops = { 447 .video = &tegra_csi_video_ops, 448 .pad = &tegra_csi_pad_ops, 449 }; 450 451 static int tegra_csi_channel_alloc(struct tegra_csi *csi, 452 struct device_node *node, 453 unsigned int port_num, unsigned int lanes, 454 unsigned int num_pads) 455 { 456 struct tegra_csi_channel *chan; 457 int ret = 0, i; 458 459 chan = kzalloc(sizeof(*chan), GFP_KERNEL); 460 if (!chan) 461 return -ENOMEM; 462 463 list_add_tail(&chan->list, &csi->csi_chans); 464 chan->csi = csi; 465 /* 466 * Each CSI brick has maximum of 4 lanes. 467 * For lanes more than 4, use multiple of immediate CSI bricks as gang. 468 */ 469 if (lanes <= CSI_LANES_PER_BRICK) { 470 chan->numlanes = lanes; 471 chan->numgangports = 1; 472 } else { 473 chan->numlanes = CSI_LANES_PER_BRICK; 474 chan->numgangports = lanes / CSI_LANES_PER_BRICK; 475 } 476 477 for (i = 0; i < chan->numgangports; i++) 478 chan->csi_port_nums[i] = port_num + i * CSI_PORTS_PER_BRICK; 479 480 chan->of_node = of_node_get(node); 481 chan->numpads = num_pads; 482 if (num_pads & 0x2) { 483 chan->pads[0].flags = MEDIA_PAD_FL_SINK; 484 chan->pads[1].flags = MEDIA_PAD_FL_SOURCE; 485 } else { 486 chan->pads[0].flags = MEDIA_PAD_FL_SOURCE; 487 } 488 489 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 490 return 0; 491 492 chan->mipi = tegra_mipi_request(csi->dev, node); 493 if (IS_ERR(chan->mipi)) { 494 ret = PTR_ERR(chan->mipi); 495 chan->mipi = NULL; 496 dev_err(csi->dev, "failed to get mipi device: %d\n", ret); 497 } 498 499 return ret; 500 } 501 502 static int tegra_csi_tpg_channels_alloc(struct tegra_csi *csi) 503 { 504 struct device_node *node = csi->dev->of_node; 505 unsigned int port_num; 506 unsigned int tpg_channels = csi->soc->csi_max_channels; 507 int ret; 508 509 /* allocate CSI channel for each CSI x2 ports */ 510 for (port_num = 0; port_num < tpg_channels; port_num++) { 511 ret = tegra_csi_channel_alloc(csi, node, port_num, 2, 1); 512 if (ret < 0) 513 return ret; 514 } 515 516 return 0; 517 } 518 519 static int tegra_csi_channels_alloc(struct tegra_csi *csi) 520 { 521 struct device_node *node = csi->dev->of_node; 522 struct v4l2_fwnode_endpoint v4l2_ep = { 523 .bus_type = V4L2_MBUS_CSI2_DPHY 524 }; 525 struct fwnode_handle *fwh; 526 struct device_node *channel; 527 struct device_node *ep; 528 unsigned int lanes, portno, num_pads; 529 int ret; 530 531 for_each_child_of_node(node, channel) { 532 if (!of_node_name_eq(channel, "channel")) 533 continue; 534 535 ret = of_property_read_u32(channel, "reg", &portno); 536 if (ret < 0) 537 continue; 538 539 if (portno >= csi->soc->csi_max_channels) { 540 dev_err(csi->dev, "invalid port num %d for %pOF\n", 541 portno, channel); 542 ret = -EINVAL; 543 goto err_node_put; 544 } 545 546 ep = of_graph_get_endpoint_by_regs(channel, 0, 0); 547 if (!ep) 548 continue; 549 550 fwh = of_fwnode_handle(ep); 551 ret = v4l2_fwnode_endpoint_parse(fwh, &v4l2_ep); 552 of_node_put(ep); 553 if (ret) { 554 dev_err(csi->dev, 555 "failed to parse v4l2 endpoint for %pOF: %d\n", 556 channel, ret); 557 goto err_node_put; 558 } 559 560 lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; 561 /* 562 * Each CSI brick has maximum 4 data lanes. 563 * For lanes more than 4, validate lanes to be multiple of 4 564 * so multiple of consecutive CSI bricks can be ganged up for 565 * streaming. 566 */ 567 if (!lanes || ((lanes & (lanes - 1)) != 0) || 568 (lanes > CSI_LANES_PER_BRICK && ((portno & 1) != 0))) { 569 dev_err(csi->dev, "invalid data-lanes %d for %pOF\n", 570 lanes, channel); 571 ret = -EINVAL; 572 goto err_node_put; 573 } 574 575 num_pads = of_graph_get_endpoint_count(channel); 576 if (num_pads == TEGRA_CSI_PADS_NUM) { 577 ret = tegra_csi_channel_alloc(csi, channel, portno, 578 lanes, num_pads); 579 if (ret < 0) 580 goto err_node_put; 581 } 582 } 583 584 return 0; 585 586 err_node_put: 587 of_node_put(channel); 588 return ret; 589 } 590 591 static int tegra_csi_channel_init(struct tegra_csi_channel *chan) 592 { 593 struct tegra_csi *csi = chan->csi; 594 struct v4l2_subdev *subdev; 595 int ret; 596 597 /* initialize the default format */ 598 chan->format.code = MEDIA_BUS_FMT_SRGGB10_1X10; 599 chan->format.field = V4L2_FIELD_NONE; 600 chan->format.colorspace = V4L2_COLORSPACE_SRGB; 601 chan->format.width = TEGRA_DEF_WIDTH; 602 chan->format.height = TEGRA_DEF_HEIGHT; 603 csi_chan_update_blank_intervals(chan, chan->format.code, 604 chan->format.width, 605 chan->format.height); 606 /* initialize V4L2 subdevice and media entity */ 607 subdev = &chan->subdev; 608 v4l2_subdev_init(subdev, &tegra_csi_ops); 609 subdev->dev = csi->dev; 610 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 611 snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s-%d", "tpg", 612 chan->csi_port_nums[0]); 613 else 614 snprintf(subdev->name, V4L2_SUBDEV_NAME_SIZE, "%s", 615 kbasename(chan->of_node->full_name)); 616 617 v4l2_set_subdevdata(subdev, chan); 618 subdev->fwnode = of_fwnode_handle(chan->of_node); 619 subdev->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 620 621 /* initialize media entity pads */ 622 ret = media_entity_pads_init(&subdev->entity, chan->numpads, 623 chan->pads); 624 if (ret < 0) { 625 dev_err(csi->dev, 626 "failed to initialize media entity: %d\n", ret); 627 subdev->dev = NULL; 628 return ret; 629 } 630 631 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) { 632 ret = v4l2_async_register_subdev(subdev); 633 if (ret < 0) { 634 dev_err(csi->dev, 635 "failed to register subdev: %d\n", ret); 636 return ret; 637 } 638 } 639 640 return 0; 641 } 642 643 void tegra_csi_error_recover(struct v4l2_subdev *sd) 644 { 645 struct tegra_csi_channel *csi_chan = to_csi_chan(sd); 646 struct tegra_csi *csi = csi_chan->csi; 647 648 /* stop streaming during error recovery */ 649 csi->ops->csi_stop_streaming(csi_chan); 650 csi->ops->csi_err_recover(csi_chan); 651 csi->ops->csi_start_streaming(csi_chan); 652 } 653 654 static int tegra_csi_channels_init(struct tegra_csi *csi) 655 { 656 struct tegra_csi_channel *chan; 657 int ret; 658 659 list_for_each_entry(chan, &csi->csi_chans, list) { 660 ret = tegra_csi_channel_init(chan); 661 if (ret) { 662 dev_err(csi->dev, 663 "failed to initialize channel-%d: %d\n", 664 chan->csi_port_nums[0], ret); 665 return ret; 666 } 667 } 668 669 return 0; 670 } 671 672 static void tegra_csi_channels_cleanup(struct tegra_csi *csi) 673 { 674 struct v4l2_subdev *subdev; 675 struct tegra_csi_channel *chan, *tmp; 676 677 list_for_each_entry_safe(chan, tmp, &csi->csi_chans, list) { 678 if (chan->mipi) 679 tegra_mipi_free(chan->mipi); 680 681 subdev = &chan->subdev; 682 if (subdev->dev) { 683 if (!IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 684 v4l2_async_unregister_subdev(subdev); 685 media_entity_cleanup(&subdev->entity); 686 } 687 688 of_node_put(chan->of_node); 689 list_del(&chan->list); 690 kfree(chan); 691 } 692 } 693 694 static int __maybe_unused csi_runtime_suspend(struct device *dev) 695 { 696 struct tegra_csi *csi = dev_get_drvdata(dev); 697 698 clk_bulk_disable_unprepare(csi->soc->num_clks, csi->clks); 699 700 return 0; 701 } 702 703 static int __maybe_unused csi_runtime_resume(struct device *dev) 704 { 705 struct tegra_csi *csi = dev_get_drvdata(dev); 706 int ret; 707 708 ret = clk_bulk_prepare_enable(csi->soc->num_clks, csi->clks); 709 if (ret < 0) { 710 dev_err(csi->dev, "failed to enable clocks: %d\n", ret); 711 return ret; 712 } 713 714 return 0; 715 } 716 717 static int tegra_csi_init(struct host1x_client *client) 718 { 719 struct tegra_csi *csi = host1x_client_to_csi(client); 720 struct tegra_video_device *vid = dev_get_drvdata(client->host); 721 int ret; 722 723 INIT_LIST_HEAD(&csi->csi_chans); 724 725 if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) 726 ret = tegra_csi_tpg_channels_alloc(csi); 727 else 728 ret = tegra_csi_channels_alloc(csi); 729 if (ret < 0) { 730 dev_err(csi->dev, 731 "failed to allocate channels: %d\n", ret); 732 goto cleanup; 733 } 734 735 ret = tegra_csi_channels_init(csi); 736 if (ret < 0) 737 goto cleanup; 738 739 vid->csi = csi; 740 741 return 0; 742 743 cleanup: 744 tegra_csi_channels_cleanup(csi); 745 return ret; 746 } 747 748 static int tegra_csi_exit(struct host1x_client *client) 749 { 750 struct tegra_csi *csi = host1x_client_to_csi(client); 751 752 tegra_csi_channels_cleanup(csi); 753 754 return 0; 755 } 756 757 static const struct host1x_client_ops csi_client_ops = { 758 .init = tegra_csi_init, 759 .exit = tegra_csi_exit, 760 }; 761 762 static int tegra_csi_probe(struct platform_device *pdev) 763 { 764 struct tegra_csi *csi; 765 unsigned int i; 766 int ret; 767 768 csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); 769 if (!csi) 770 return -ENOMEM; 771 772 csi->iomem = devm_platform_ioremap_resource(pdev, 0); 773 if (IS_ERR(csi->iomem)) 774 return PTR_ERR(csi->iomem); 775 776 csi->soc = of_device_get_match_data(&pdev->dev); 777 778 csi->clks = devm_kcalloc(&pdev->dev, csi->soc->num_clks, 779 sizeof(*csi->clks), GFP_KERNEL); 780 if (!csi->clks) 781 return -ENOMEM; 782 783 for (i = 0; i < csi->soc->num_clks; i++) 784 csi->clks[i].id = csi->soc->clk_names[i]; 785 786 ret = devm_clk_bulk_get(&pdev->dev, csi->soc->num_clks, csi->clks); 787 if (ret) { 788 dev_err(&pdev->dev, "failed to get the clocks: %d\n", ret); 789 return ret; 790 } 791 792 if (!pdev->dev.pm_domain) { 793 ret = -ENOENT; 794 dev_warn(&pdev->dev, "PM domain is not attached: %d\n", ret); 795 return ret; 796 } 797 798 csi->dev = &pdev->dev; 799 csi->ops = csi->soc->ops; 800 platform_set_drvdata(pdev, csi); 801 pm_runtime_enable(&pdev->dev); 802 803 /* initialize host1x interface */ 804 INIT_LIST_HEAD(&csi->client.list); 805 csi->client.ops = &csi_client_ops; 806 csi->client.dev = &pdev->dev; 807 808 ret = host1x_client_register(&csi->client); 809 if (ret < 0) { 810 dev_err(&pdev->dev, 811 "failed to register host1x client: %d\n", ret); 812 goto rpm_disable; 813 } 814 815 return 0; 816 817 rpm_disable: 818 pm_runtime_disable(&pdev->dev); 819 return ret; 820 } 821 822 static int tegra_csi_remove(struct platform_device *pdev) 823 { 824 struct tegra_csi *csi = platform_get_drvdata(pdev); 825 826 host1x_client_unregister(&csi->client); 827 828 pm_runtime_disable(&pdev->dev); 829 830 return 0; 831 } 832 833 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 834 extern const struct tegra_csi_soc tegra210_csi_soc; 835 #endif 836 837 static const struct of_device_id tegra_csi_of_id_table[] = { 838 #if defined(CONFIG_ARCH_TEGRA_210_SOC) 839 { .compatible = "nvidia,tegra210-csi", .data = &tegra210_csi_soc }, 840 #endif 841 { } 842 }; 843 MODULE_DEVICE_TABLE(of, tegra_csi_of_id_table); 844 845 static const struct dev_pm_ops tegra_csi_pm_ops = { 846 SET_RUNTIME_PM_OPS(csi_runtime_suspend, csi_runtime_resume, NULL) 847 }; 848 849 struct platform_driver tegra_csi_driver = { 850 .driver = { 851 .name = "tegra-csi", 852 .of_match_table = tegra_csi_of_id_table, 853 .pm = &tegra_csi_pm_ops, 854 }, 855 .probe = tegra_csi_probe, 856 .remove = tegra_csi_remove, 857 }; 858