1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cedrus VPU driver 4 * 5 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com> 6 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com> 7 * Copyright (C) 2018 Bootlin 8 * 9 * Based on the vim2m driver, that is: 10 * 11 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 12 * Pawel Osciak, <pawel@osciak.com> 13 * Marek Szyprowski, <m.szyprowski@samsung.com> 14 */ 15 16 #include <linux/platform_device.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/of_device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/interrupt.h> 21 #include <linux/clk.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 #include <linux/soc/sunxi/sunxi_sram.h> 25 26 #include <media/videobuf2-core.h> 27 #include <media/v4l2-mem2mem.h> 28 29 #include "cedrus.h" 30 #include "cedrus_hw.h" 31 #include "cedrus_regs.h" 32 33 int cedrus_engine_enable(struct cedrus_dev *dev, enum cedrus_codec codec) 34 { 35 u32 reg = 0; 36 37 /* 38 * FIXME: This is only valid on 32-bits DDR's, we should test 39 * it on the A13/A33. 40 */ 41 reg |= VE_MODE_REC_WR_MODE_2MB; 42 reg |= VE_MODE_DDR_MODE_BW_128; 43 44 switch (codec) { 45 case CEDRUS_CODEC_MPEG2: 46 reg |= VE_MODE_DEC_MPEG; 47 break; 48 49 default: 50 return -EINVAL; 51 } 52 53 cedrus_write(dev, VE_MODE, reg); 54 55 return 0; 56 } 57 58 void cedrus_engine_disable(struct cedrus_dev *dev) 59 { 60 cedrus_write(dev, VE_MODE, VE_MODE_DISABLED); 61 } 62 63 void cedrus_dst_format_set(struct cedrus_dev *dev, 64 struct v4l2_pix_format *fmt) 65 { 66 unsigned int width = fmt->width; 67 unsigned int height = fmt->height; 68 u32 chroma_size; 69 u32 reg; 70 71 switch (fmt->pixelformat) { 72 case V4L2_PIX_FMT_NV12: 73 chroma_size = ALIGN(width, 16) * ALIGN(height, 16) / 2; 74 75 reg = VE_PRIMARY_OUT_FMT_NV12; 76 cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg); 77 78 reg = VE_CHROMA_BUF_LEN_SDRT(chroma_size / 2); 79 cedrus_write(dev, VE_CHROMA_BUF_LEN, reg); 80 81 reg = chroma_size / 2; 82 cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg); 83 84 reg = VE_PRIMARY_FB_LINE_STRIDE_LUMA(ALIGN(width, 16)) | 85 VE_PRIMARY_FB_LINE_STRIDE_CHROMA(ALIGN(width, 16) / 2); 86 cedrus_write(dev, VE_PRIMARY_FB_LINE_STRIDE, reg); 87 88 break; 89 case V4L2_PIX_FMT_SUNXI_TILED_NV12: 90 default: 91 reg = VE_PRIMARY_OUT_FMT_TILED_32_NV12; 92 cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg); 93 94 reg = VE_SECONDARY_OUT_FMT_TILED_32_NV12; 95 cedrus_write(dev, VE_CHROMA_BUF_LEN, reg); 96 97 break; 98 } 99 } 100 101 static irqreturn_t cedrus_irq(int irq, void *data) 102 { 103 struct cedrus_dev *dev = data; 104 struct cedrus_ctx *ctx; 105 struct vb2_v4l2_buffer *src_buf, *dst_buf; 106 enum vb2_buffer_state state; 107 enum cedrus_irq_status status; 108 109 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev); 110 if (!ctx) { 111 v4l2_err(&dev->v4l2_dev, 112 "Instance released before the end of transaction\n"); 113 return IRQ_NONE; 114 } 115 116 status = dev->dec_ops[ctx->current_codec]->irq_status(ctx); 117 if (status == CEDRUS_IRQ_NONE) 118 return IRQ_NONE; 119 120 dev->dec_ops[ctx->current_codec]->irq_disable(ctx); 121 dev->dec_ops[ctx->current_codec]->irq_clear(ctx); 122 123 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 124 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 125 126 if (!src_buf || !dst_buf) { 127 v4l2_err(&dev->v4l2_dev, 128 "Missing source and/or destination buffers\n"); 129 return IRQ_HANDLED; 130 } 131 132 if (status == CEDRUS_IRQ_ERROR) 133 state = VB2_BUF_STATE_ERROR; 134 else 135 state = VB2_BUF_STATE_DONE; 136 137 v4l2_m2m_buf_done(src_buf, state); 138 v4l2_m2m_buf_done(dst_buf, state); 139 140 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx); 141 142 return IRQ_HANDLED; 143 } 144 145 int cedrus_hw_probe(struct cedrus_dev *dev) 146 { 147 const struct cedrus_variant *variant; 148 struct resource *res; 149 int irq_dec; 150 int ret; 151 152 variant = of_device_get_match_data(dev->dev); 153 if (!variant) 154 return -EINVAL; 155 156 dev->capabilities = variant->capabilities; 157 158 irq_dec = platform_get_irq(dev->pdev, 0); 159 if (irq_dec <= 0) { 160 dev_err(dev->dev, "Failed to get IRQ\n"); 161 162 return irq_dec; 163 } 164 ret = devm_request_irq(dev->dev, irq_dec, cedrus_irq, 165 0, dev_name(dev->dev), dev); 166 if (ret) { 167 dev_err(dev->dev, "Failed to request IRQ\n"); 168 169 return ret; 170 } 171 172 /* 173 * The VPU is only able to handle bus addresses so we have to subtract 174 * the RAM offset to the physcal addresses. 175 * 176 * This information will eventually be obtained from device-tree. 177 */ 178 179 #ifdef PHYS_PFN_OFFSET 180 if (!(variant->quirks & CEDRUS_QUIRK_NO_DMA_OFFSET)) 181 dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET; 182 #endif 183 184 ret = of_reserved_mem_device_init(dev->dev); 185 if (ret && ret != -ENODEV) { 186 dev_err(dev->dev, "Failed to reserve memory\n"); 187 188 return ret; 189 } 190 191 ret = sunxi_sram_claim(dev->dev); 192 if (ret) { 193 dev_err(dev->dev, "Failed to claim SRAM\n"); 194 195 goto err_mem; 196 } 197 198 dev->ahb_clk = devm_clk_get(dev->dev, "ahb"); 199 if (IS_ERR(dev->ahb_clk)) { 200 dev_err(dev->dev, "Failed to get AHB clock\n"); 201 202 ret = PTR_ERR(dev->ahb_clk); 203 goto err_sram; 204 } 205 206 dev->mod_clk = devm_clk_get(dev->dev, "mod"); 207 if (IS_ERR(dev->mod_clk)) { 208 dev_err(dev->dev, "Failed to get MOD clock\n"); 209 210 ret = PTR_ERR(dev->mod_clk); 211 goto err_sram; 212 } 213 214 dev->ram_clk = devm_clk_get(dev->dev, "ram"); 215 if (IS_ERR(dev->ram_clk)) { 216 dev_err(dev->dev, "Failed to get RAM clock\n"); 217 218 ret = PTR_ERR(dev->ram_clk); 219 goto err_sram; 220 } 221 222 dev->rstc = devm_reset_control_get(dev->dev, NULL); 223 if (IS_ERR(dev->rstc)) { 224 dev_err(dev->dev, "Failed to get reset control\n"); 225 226 ret = PTR_ERR(dev->rstc); 227 goto err_sram; 228 } 229 230 res = platform_get_resource(dev->pdev, IORESOURCE_MEM, 0); 231 dev->base = devm_ioremap_resource(dev->dev, res); 232 if (IS_ERR(dev->base)) { 233 dev_err(dev->dev, "Failed to map registers\n"); 234 235 ret = PTR_ERR(dev->base); 236 goto err_sram; 237 } 238 239 ret = clk_set_rate(dev->mod_clk, CEDRUS_CLOCK_RATE_DEFAULT); 240 if (ret) { 241 dev_err(dev->dev, "Failed to set clock rate\n"); 242 243 goto err_sram; 244 } 245 246 ret = clk_prepare_enable(dev->ahb_clk); 247 if (ret) { 248 dev_err(dev->dev, "Failed to enable AHB clock\n"); 249 250 goto err_sram; 251 } 252 253 ret = clk_prepare_enable(dev->mod_clk); 254 if (ret) { 255 dev_err(dev->dev, "Failed to enable MOD clock\n"); 256 257 goto err_ahb_clk; 258 } 259 260 ret = clk_prepare_enable(dev->ram_clk); 261 if (ret) { 262 dev_err(dev->dev, "Failed to enable RAM clock\n"); 263 264 goto err_mod_clk; 265 } 266 267 ret = reset_control_reset(dev->rstc); 268 if (ret) { 269 dev_err(dev->dev, "Failed to apply reset\n"); 270 271 goto err_ram_clk; 272 } 273 274 return 0; 275 276 err_ram_clk: 277 clk_disable_unprepare(dev->ram_clk); 278 err_mod_clk: 279 clk_disable_unprepare(dev->mod_clk); 280 err_ahb_clk: 281 clk_disable_unprepare(dev->ahb_clk); 282 err_sram: 283 sunxi_sram_release(dev->dev); 284 err_mem: 285 of_reserved_mem_device_release(dev->dev); 286 287 return ret; 288 } 289 290 void cedrus_hw_remove(struct cedrus_dev *dev) 291 { 292 reset_control_assert(dev->rstc); 293 294 clk_disable_unprepare(dev->ram_clk); 295 clk_disable_unprepare(dev->mod_clk); 296 clk_disable_unprepare(dev->ahb_clk); 297 298 sunxi_sram_release(dev->dev); 299 300 of_reserved_mem_device_release(dev->dev); 301 } 302