1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Cedrus VPU driver 4 * 5 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com> 6 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com> 7 * Copyright (C) 2018 Bootlin 8 * 9 * Based on the vim2m driver, that is: 10 * 11 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 12 * Pawel Osciak, <pawel@osciak.com> 13 * Marek Szyprowski, <m.szyprowski@samsung.com> 14 */ 15 16 #include <linux/platform_device.h> 17 #include <linux/of_reserved_mem.h> 18 #include <linux/of_device.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/interrupt.h> 21 #include <linux/clk.h> 22 #include <linux/regmap.h> 23 #include <linux/reset.h> 24 #include <linux/soc/sunxi/sunxi_sram.h> 25 26 #include <media/videobuf2-core.h> 27 #include <media/v4l2-mem2mem.h> 28 29 #include "cedrus.h" 30 #include "cedrus_hw.h" 31 #include "cedrus_regs.h" 32 33 int cedrus_engine_enable(struct cedrus_ctx *ctx, enum cedrus_codec codec) 34 { 35 u32 reg = 0; 36 37 /* 38 * FIXME: This is only valid on 32-bits DDR's, we should test 39 * it on the A13/A33. 40 */ 41 reg |= VE_MODE_REC_WR_MODE_2MB; 42 reg |= VE_MODE_DDR_MODE_BW_128; 43 44 switch (codec) { 45 case CEDRUS_CODEC_MPEG2: 46 reg |= VE_MODE_DEC_MPEG; 47 break; 48 49 case CEDRUS_CODEC_H264: 50 reg |= VE_MODE_DEC_H264; 51 break; 52 53 case CEDRUS_CODEC_H265: 54 reg |= VE_MODE_DEC_H265; 55 break; 56 57 default: 58 return -EINVAL; 59 } 60 61 if (ctx->src_fmt.width == 4096) 62 reg |= VE_MODE_PIC_WIDTH_IS_4096; 63 if (ctx->src_fmt.width > 2048) 64 reg |= VE_MODE_PIC_WIDTH_MORE_2048; 65 66 cedrus_write(ctx->dev, VE_MODE, reg); 67 68 return 0; 69 } 70 71 void cedrus_engine_disable(struct cedrus_dev *dev) 72 { 73 cedrus_write(dev, VE_MODE, VE_MODE_DISABLED); 74 } 75 76 void cedrus_dst_format_set(struct cedrus_dev *dev, 77 struct v4l2_pix_format *fmt) 78 { 79 unsigned int width = fmt->width; 80 unsigned int height = fmt->height; 81 u32 chroma_size; 82 u32 reg; 83 84 switch (fmt->pixelformat) { 85 case V4L2_PIX_FMT_NV12: 86 chroma_size = ALIGN(width, 16) * ALIGN(height, 16) / 2; 87 88 reg = VE_PRIMARY_OUT_FMT_NV12; 89 cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg); 90 91 reg = chroma_size / 2; 92 cedrus_write(dev, VE_PRIMARY_CHROMA_BUF_LEN, reg); 93 94 reg = VE_PRIMARY_FB_LINE_STRIDE_LUMA(ALIGN(width, 16)) | 95 VE_PRIMARY_FB_LINE_STRIDE_CHROMA(ALIGN(width, 16) / 2); 96 cedrus_write(dev, VE_PRIMARY_FB_LINE_STRIDE, reg); 97 98 break; 99 case V4L2_PIX_FMT_SUNXI_TILED_NV12: 100 default: 101 reg = VE_PRIMARY_OUT_FMT_TILED_32_NV12; 102 cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg); 103 104 reg = VE_SECONDARY_OUT_FMT_TILED_32_NV12; 105 cedrus_write(dev, VE_CHROMA_BUF_LEN, reg); 106 107 break; 108 } 109 } 110 111 static irqreturn_t cedrus_irq(int irq, void *data) 112 { 113 struct cedrus_dev *dev = data; 114 struct cedrus_ctx *ctx; 115 enum vb2_buffer_state state; 116 enum cedrus_irq_status status; 117 118 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev); 119 if (!ctx) { 120 v4l2_err(&dev->v4l2_dev, 121 "Instance released before the end of transaction\n"); 122 return IRQ_NONE; 123 } 124 125 status = dev->dec_ops[ctx->current_codec]->irq_status(ctx); 126 if (status == CEDRUS_IRQ_NONE) 127 return IRQ_NONE; 128 129 dev->dec_ops[ctx->current_codec]->irq_disable(ctx); 130 dev->dec_ops[ctx->current_codec]->irq_clear(ctx); 131 132 if (status == CEDRUS_IRQ_ERROR) 133 state = VB2_BUF_STATE_ERROR; 134 else 135 state = VB2_BUF_STATE_DONE; 136 137 v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx, 138 state); 139 140 return IRQ_HANDLED; 141 } 142 143 int cedrus_hw_probe(struct cedrus_dev *dev) 144 { 145 const struct cedrus_variant *variant; 146 int irq_dec; 147 int ret; 148 149 variant = of_device_get_match_data(dev->dev); 150 if (!variant) 151 return -EINVAL; 152 153 dev->capabilities = variant->capabilities; 154 155 irq_dec = platform_get_irq(dev->pdev, 0); 156 if (irq_dec <= 0) 157 return irq_dec; 158 ret = devm_request_irq(dev->dev, irq_dec, cedrus_irq, 159 0, dev_name(dev->dev), dev); 160 if (ret) { 161 dev_err(dev->dev, "Failed to request IRQ\n"); 162 163 return ret; 164 } 165 166 /* 167 * The VPU is only able to handle bus addresses so we have to subtract 168 * the RAM offset to the physcal addresses. 169 * 170 * This information will eventually be obtained from device-tree. 171 */ 172 173 #ifdef PHYS_PFN_OFFSET 174 if (!(variant->quirks & CEDRUS_QUIRK_NO_DMA_OFFSET)) 175 dev->dev->dma_pfn_offset = PHYS_PFN_OFFSET; 176 #endif 177 178 ret = of_reserved_mem_device_init(dev->dev); 179 if (ret && ret != -ENODEV) { 180 dev_err(dev->dev, "Failed to reserve memory\n"); 181 182 return ret; 183 } 184 185 ret = sunxi_sram_claim(dev->dev); 186 if (ret) { 187 dev_err(dev->dev, "Failed to claim SRAM\n"); 188 189 goto err_mem; 190 } 191 192 dev->ahb_clk = devm_clk_get(dev->dev, "ahb"); 193 if (IS_ERR(dev->ahb_clk)) { 194 dev_err(dev->dev, "Failed to get AHB clock\n"); 195 196 ret = PTR_ERR(dev->ahb_clk); 197 goto err_sram; 198 } 199 200 dev->mod_clk = devm_clk_get(dev->dev, "mod"); 201 if (IS_ERR(dev->mod_clk)) { 202 dev_err(dev->dev, "Failed to get MOD clock\n"); 203 204 ret = PTR_ERR(dev->mod_clk); 205 goto err_sram; 206 } 207 208 dev->ram_clk = devm_clk_get(dev->dev, "ram"); 209 if (IS_ERR(dev->ram_clk)) { 210 dev_err(dev->dev, "Failed to get RAM clock\n"); 211 212 ret = PTR_ERR(dev->ram_clk); 213 goto err_sram; 214 } 215 216 dev->rstc = devm_reset_control_get(dev->dev, NULL); 217 if (IS_ERR(dev->rstc)) { 218 dev_err(dev->dev, "Failed to get reset control\n"); 219 220 ret = PTR_ERR(dev->rstc); 221 goto err_sram; 222 } 223 224 dev->base = devm_platform_ioremap_resource(dev->pdev, 0); 225 if (IS_ERR(dev->base)) { 226 dev_err(dev->dev, "Failed to map registers\n"); 227 228 ret = PTR_ERR(dev->base); 229 goto err_sram; 230 } 231 232 ret = clk_set_rate(dev->mod_clk, variant->mod_rate); 233 if (ret) { 234 dev_err(dev->dev, "Failed to set clock rate\n"); 235 236 goto err_sram; 237 } 238 239 ret = clk_prepare_enable(dev->ahb_clk); 240 if (ret) { 241 dev_err(dev->dev, "Failed to enable AHB clock\n"); 242 243 goto err_sram; 244 } 245 246 ret = clk_prepare_enable(dev->mod_clk); 247 if (ret) { 248 dev_err(dev->dev, "Failed to enable MOD clock\n"); 249 250 goto err_ahb_clk; 251 } 252 253 ret = clk_prepare_enable(dev->ram_clk); 254 if (ret) { 255 dev_err(dev->dev, "Failed to enable RAM clock\n"); 256 257 goto err_mod_clk; 258 } 259 260 ret = reset_control_reset(dev->rstc); 261 if (ret) { 262 dev_err(dev->dev, "Failed to apply reset\n"); 263 264 goto err_ram_clk; 265 } 266 267 return 0; 268 269 err_ram_clk: 270 clk_disable_unprepare(dev->ram_clk); 271 err_mod_clk: 272 clk_disable_unprepare(dev->mod_clk); 273 err_ahb_clk: 274 clk_disable_unprepare(dev->ahb_clk); 275 err_sram: 276 sunxi_sram_release(dev->dev); 277 err_mem: 278 of_reserved_mem_device_release(dev->dev); 279 280 return ret; 281 } 282 283 void cedrus_hw_remove(struct cedrus_dev *dev) 284 { 285 reset_control_assert(dev->rstc); 286 287 clk_disable_unprepare(dev->ram_clk); 288 clk_disable_unprepare(dev->mod_clk); 289 clk_disable_unprepare(dev->ahb_clk); 290 291 sunxi_sram_release(dev->dev); 292 293 of_reserved_mem_device_release(dev->dev); 294 } 295