1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Cedrus VPU driver 4 * 5 * Copyright (C) 2013 Jens Kuske <jenskuske@gmail.com> 6 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com> 7 * Copyright (C) 2018 Bootlin 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/types.h> 12 13 #include <media/videobuf2-dma-contig.h> 14 15 #include "cedrus.h" 16 #include "cedrus_hw.h" 17 #include "cedrus_regs.h" 18 19 /* 20 * These are the sizes for side buffers required by the hardware for storing 21 * internal decoding metadata. They match the values used by the early BSP 22 * implementations, that were initially exposed in libvdpau-sunxi. 23 * Subsequent BSP implementations seem to double the neighbor info buffer size 24 * for the H6 SoC, which may be related to 10 bit H265 support. 25 */ 26 #define CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE (794 * SZ_1K) 27 #define CEDRUS_H265_ENTRY_POINTS_BUF_SIZE (4 * SZ_1K) 28 #define CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE 160 29 30 struct cedrus_h265_sram_frame_info { 31 __le32 top_pic_order_cnt; 32 __le32 bottom_pic_order_cnt; 33 __le32 top_mv_col_buf_addr; 34 __le32 bottom_mv_col_buf_addr; 35 __le32 luma_addr; 36 __le32 chroma_addr; 37 } __packed; 38 39 struct cedrus_h265_sram_pred_weight { 40 __s8 delta_weight; 41 __s8 offset; 42 } __packed; 43 44 static enum cedrus_irq_status cedrus_h265_irq_status(struct cedrus_ctx *ctx) 45 { 46 struct cedrus_dev *dev = ctx->dev; 47 u32 reg; 48 49 reg = cedrus_read(dev, VE_DEC_H265_STATUS); 50 reg &= VE_DEC_H265_STATUS_CHECK_MASK; 51 52 if (reg & VE_DEC_H265_STATUS_CHECK_ERROR || 53 !(reg & VE_DEC_H265_STATUS_SUCCESS)) 54 return CEDRUS_IRQ_ERROR; 55 56 return CEDRUS_IRQ_OK; 57 } 58 59 static void cedrus_h265_irq_clear(struct cedrus_ctx *ctx) 60 { 61 struct cedrus_dev *dev = ctx->dev; 62 63 cedrus_write(dev, VE_DEC_H265_STATUS, VE_DEC_H265_STATUS_CHECK_MASK); 64 } 65 66 static void cedrus_h265_irq_disable(struct cedrus_ctx *ctx) 67 { 68 struct cedrus_dev *dev = ctx->dev; 69 u32 reg = cedrus_read(dev, VE_DEC_H265_CTRL); 70 71 reg &= ~VE_DEC_H265_CTRL_IRQ_MASK; 72 73 cedrus_write(dev, VE_DEC_H265_CTRL, reg); 74 } 75 76 static void cedrus_h265_sram_write_offset(struct cedrus_dev *dev, u32 offset) 77 { 78 cedrus_write(dev, VE_DEC_H265_SRAM_OFFSET, offset); 79 } 80 81 static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data, 82 unsigned int size) 83 { 84 u32 *word = data; 85 86 while (size >= sizeof(u32)) { 87 cedrus_write(dev, VE_DEC_H265_SRAM_DATA, *word++); 88 size -= sizeof(u32); 89 } 90 } 91 92 static inline dma_addr_t 93 cedrus_h265_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx, 94 unsigned int index, unsigned int field) 95 { 96 return ctx->codec.h265.mv_col_buf_addr + index * 97 ctx->codec.h265.mv_col_buf_unit_size + 98 field * ctx->codec.h265.mv_col_buf_unit_size / 2; 99 } 100 101 static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx, 102 unsigned int index, 103 bool field_pic, 104 u32 pic_order_cnt[], 105 int buffer_index) 106 { 107 struct cedrus_dev *dev = ctx->dev; 108 dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 0); 109 dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 1); 110 dma_addr_t mv_col_buf_addr[2] = { 111 cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, 0), 112 cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, 113 field_pic ? 1 : 0) 114 }; 115 u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO + 116 VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index; 117 struct cedrus_h265_sram_frame_info frame_info = { 118 .top_pic_order_cnt = cpu_to_le32(pic_order_cnt[0]), 119 .bottom_pic_order_cnt = cpu_to_le32(field_pic ? 120 pic_order_cnt[1] : 121 pic_order_cnt[0]), 122 .top_mv_col_buf_addr = 123 cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])), 124 .bottom_mv_col_buf_addr = cpu_to_le32(field_pic ? 125 VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[1]) : 126 VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])), 127 .luma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_luma_addr)), 128 .chroma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_chroma_addr)), 129 }; 130 131 cedrus_h265_sram_write_offset(dev, offset); 132 cedrus_h265_sram_write_data(dev, &frame_info, sizeof(frame_info)); 133 } 134 135 static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx, 136 const struct v4l2_hevc_dpb_entry *dpb, 137 u8 num_active_dpb_entries) 138 { 139 struct vb2_queue *vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, 140 V4L2_BUF_TYPE_VIDEO_CAPTURE); 141 unsigned int i; 142 143 for (i = 0; i < num_active_dpb_entries; i++) { 144 int buffer_index = vb2_find_timestamp(vq, dpb[i].timestamp, 0); 145 u32 pic_order_cnt[2] = { 146 dpb[i].pic_order_cnt[0], 147 dpb[i].pic_order_cnt[1] 148 }; 149 150 if (buffer_index < 0) 151 continue; 152 153 cedrus_h265_frame_info_write_single(ctx, i, dpb[i].field_pic, 154 pic_order_cnt, 155 buffer_index); 156 } 157 } 158 159 static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev, 160 const struct v4l2_hevc_dpb_entry *dpb, 161 const u8 list[], 162 u8 num_ref_idx_active, 163 u32 sram_offset) 164 { 165 unsigned int i; 166 u32 word = 0; 167 168 cedrus_h265_sram_write_offset(dev, sram_offset); 169 170 for (i = 0; i < num_ref_idx_active; i++) { 171 unsigned int shift = (i % 4) * 8; 172 unsigned int index = list[i]; 173 u8 value = list[i]; 174 175 if (dpb[index].rps == V4L2_HEVC_DPB_ENTRY_RPS_LT_CURR) 176 value |= VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF; 177 178 /* Each SRAM word gathers up to 4 references. */ 179 word |= value << shift; 180 181 /* Write the word to SRAM and clear it for the next batch. */ 182 if ((i % 4) == 3 || i == (num_ref_idx_active - 1)) { 183 cedrus_h265_sram_write_data(dev, &word, sizeof(word)); 184 word = 0; 185 } 186 } 187 } 188 189 static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev, 190 const s8 delta_luma_weight[], 191 const s8 luma_offset[], 192 const s8 delta_chroma_weight[][2], 193 const s8 chroma_offset[][2], 194 u8 num_ref_idx_active, 195 u32 sram_luma_offset, 196 u32 sram_chroma_offset) 197 { 198 struct cedrus_h265_sram_pred_weight pred_weight[2] = { { 0 } }; 199 unsigned int i, j; 200 201 cedrus_h265_sram_write_offset(dev, sram_luma_offset); 202 203 for (i = 0; i < num_ref_idx_active; i++) { 204 unsigned int index = i % 2; 205 206 pred_weight[index].delta_weight = delta_luma_weight[i]; 207 pred_weight[index].offset = luma_offset[i]; 208 209 if (index == 1 || i == (num_ref_idx_active - 1)) 210 cedrus_h265_sram_write_data(dev, (u32 *)&pred_weight, 211 sizeof(pred_weight)); 212 } 213 214 cedrus_h265_sram_write_offset(dev, sram_chroma_offset); 215 216 for (i = 0; i < num_ref_idx_active; i++) { 217 for (j = 0; j < 2; j++) { 218 pred_weight[j].delta_weight = delta_chroma_weight[i][j]; 219 pred_weight[j].offset = chroma_offset[i][j]; 220 } 221 222 cedrus_h265_sram_write_data(dev, &pred_weight, 223 sizeof(pred_weight)); 224 } 225 } 226 227 static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num) 228 { 229 int count = 0; 230 231 while (count < num) { 232 int tmp = min(num - count, 32); 233 234 cedrus_write(dev, VE_DEC_H265_TRIGGER, 235 VE_DEC_H265_TRIGGER_FLUSH_BITS | 236 VE_DEC_H265_TRIGGER_TYPE_N_BITS(tmp)); 237 while (cedrus_read(dev, VE_DEC_H265_STATUS) & VE_DEC_H265_STATUS_VLD_BUSY) 238 udelay(1); 239 240 count += tmp; 241 } 242 } 243 244 static void cedrus_h265_setup(struct cedrus_ctx *ctx, 245 struct cedrus_run *run) 246 { 247 struct cedrus_dev *dev = ctx->dev; 248 const struct v4l2_ctrl_hevc_sps *sps; 249 const struct v4l2_ctrl_hevc_pps *pps; 250 const struct v4l2_ctrl_hevc_slice_params *slice_params; 251 const struct v4l2_ctrl_hevc_decode_params *decode_params; 252 const struct v4l2_hevc_pred_weight_table *pred_weight_table; 253 unsigned int width_in_ctb_luma, ctb_size_luma; 254 unsigned int log2_max_luma_coding_block_size; 255 dma_addr_t src_buf_addr; 256 dma_addr_t src_buf_end_addr; 257 u32 chroma_log2_weight_denom; 258 u32 output_pic_list_index; 259 u32 pic_order_cnt[2]; 260 u32 reg; 261 262 sps = run->h265.sps; 263 pps = run->h265.pps; 264 slice_params = run->h265.slice_params; 265 decode_params = run->h265.decode_params; 266 pred_weight_table = &slice_params->pred_weight_table; 267 268 log2_max_luma_coding_block_size = 269 sps->log2_min_luma_coding_block_size_minus3 + 3 + 270 sps->log2_diff_max_min_luma_coding_block_size; 271 ctb_size_luma = 1UL << log2_max_luma_coding_block_size; 272 width_in_ctb_luma = 273 DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma); 274 275 /* MV column buffer size and allocation. */ 276 if (!ctx->codec.h265.mv_col_buf_size) { 277 unsigned int num_buffers = 278 run->dst->vb2_buf.vb2_queue->num_buffers; 279 280 /* 281 * Each CTB requires a MV col buffer with a specific unit size. 282 * Since the address is given with missing lsb bits, 1 KiB is 283 * added to each buffer to ensure proper alignment. 284 */ 285 ctx->codec.h265.mv_col_buf_unit_size = 286 DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) * 287 DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) * 288 CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K; 289 290 ctx->codec.h265.mv_col_buf_size = num_buffers * 291 ctx->codec.h265.mv_col_buf_unit_size; 292 293 ctx->codec.h265.mv_col_buf = 294 dma_alloc_coherent(dev->dev, 295 ctx->codec.h265.mv_col_buf_size, 296 &ctx->codec.h265.mv_col_buf_addr, 297 GFP_KERNEL); 298 if (!ctx->codec.h265.mv_col_buf) { 299 ctx->codec.h265.mv_col_buf_size = 0; 300 // TODO: Abort the process here. 301 return; 302 } 303 } 304 305 /* Activate H265 engine. */ 306 cedrus_engine_enable(ctx, CEDRUS_CODEC_H265); 307 308 /* Source offset and length in bits. */ 309 310 cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, 0); 311 312 reg = slice_params->bit_size; 313 cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg); 314 315 /* Source beginning and end addresses. */ 316 317 src_buf_addr = vb2_dma_contig_plane_dma_addr(&run->src->vb2_buf, 0); 318 319 reg = VE_DEC_H265_BITS_ADDR_BASE(src_buf_addr); 320 reg |= VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA; 321 reg |= VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA; 322 reg |= VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA; 323 324 cedrus_write(dev, VE_DEC_H265_BITS_ADDR, reg); 325 326 src_buf_end_addr = src_buf_addr + 327 DIV_ROUND_UP(slice_params->bit_size, 8); 328 329 reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr); 330 cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg); 331 332 /* Coding tree block address */ 333 reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma); 334 reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma); 335 cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg); 336 337 cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0); 338 cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0); 339 340 /* Clear the number of correctly-decoded coding tree blocks. */ 341 if (ctx->fh.m2m_ctx->new_frame) 342 cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0); 343 344 /* Initialize bitstream access. */ 345 cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC); 346 347 cedrus_h265_skip_bits(dev, slice_params->data_bit_offset); 348 349 /* Bitstream parameters. */ 350 351 reg = VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(slice_params->nal_unit_type) | 352 VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(slice_params->nuh_temporal_id_plus1); 353 354 cedrus_write(dev, VE_DEC_H265_DEC_NAL_HDR, reg); 355 356 /* SPS. */ 357 358 reg = VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(sps->max_transform_hierarchy_depth_intra) | 359 VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(sps->max_transform_hierarchy_depth_inter) | 360 VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(sps->log2_diff_max_min_luma_transform_block_size) | 361 VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(sps->log2_min_luma_transform_block_size_minus2) | 362 VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) | 363 VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) | 364 VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) | 365 VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(sps->bit_depth_luma_minus8) | 366 VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc); 367 368 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE, 369 V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED, 370 sps->flags); 371 372 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED, 373 V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED, 374 sps->flags); 375 376 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED, 377 V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET, 378 sps->flags); 379 380 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_AMP_ENABLED, 381 V4L2_HEVC_SPS_FLAG_AMP_ENABLED, sps->flags); 382 383 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE, 384 V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE, 385 sps->flags); 386 387 cedrus_write(dev, VE_DEC_H265_DEC_SPS_HDR, reg); 388 389 reg = VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_pcm_luma_coding_block_size) | 390 VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_pcm_luma_coding_block_size_minus3) | 391 VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(sps->pcm_sample_bit_depth_chroma_minus1) | 392 VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(sps->pcm_sample_bit_depth_luma_minus1); 393 394 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_ENABLED, 395 V4L2_HEVC_SPS_FLAG_PCM_ENABLED, sps->flags); 396 397 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED, 398 V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED, 399 sps->flags); 400 401 cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg); 402 403 /* PPS. */ 404 405 reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) | 406 VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) | 407 VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) | 408 VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(pps->diff_cu_qp_delta_depth); 409 410 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED, 411 V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED, 412 pps->flags); 413 414 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED, 415 V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED, 416 pps->flags); 417 418 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED, 419 V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED, 420 pps->flags); 421 422 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED, 423 V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED, 424 pps->flags); 425 426 cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL0, reg); 427 428 reg = VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(pps->log2_parallel_merge_level_minus2); 429 430 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED, 431 V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED, 432 pps->flags); 433 434 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED, 435 V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED, 436 pps->flags); 437 438 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED, 439 V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED, 440 pps->flags); 441 442 /* TODO: VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */ 443 444 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED, 445 V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED, 446 pps->flags); 447 448 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED, 449 V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED, pps->flags); 450 451 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED, 452 V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED, pps->flags); 453 454 cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL1, reg); 455 456 /* Slice Parameters. */ 457 458 reg = VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(slice_params->pic_struct) | 459 VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(slice_params->five_minus_max_num_merge_cand) | 460 VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(slice_params->num_ref_idx_l1_active_minus1) | 461 VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(slice_params->num_ref_idx_l0_active_minus1) | 462 VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(slice_params->collocated_ref_idx) | 463 VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) | 464 VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type); 465 466 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0, 467 V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0, 468 slice_params->flags); 469 470 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT, 471 V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT, 472 slice_params->flags); 473 474 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO, 475 V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO, 476 slice_params->flags); 477 478 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA, 479 V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA, 480 slice_params->flags); 481 482 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA, 483 V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA, 484 slice_params->flags); 485 486 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE, 487 V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED, 488 slice_params->flags); 489 490 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT, 491 V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT, 492 slice_params->flags); 493 494 if (ctx->fh.m2m_ctx->new_frame) 495 reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC; 496 497 cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg); 498 499 reg = VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) | 500 VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) | 501 VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) | 502 VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) | 503 VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta); 504 505 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED, 506 V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED, 507 slice_params->flags); 508 509 reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED, 510 V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED, 511 slice_params->flags); 512 513 if (decode_params->num_poc_st_curr_after == 0) 514 reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_NOT_LOW_DELAY; 515 516 cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO1, reg); 517 518 chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom + 519 pred_weight_table->delta_chroma_log2_weight_denom; 520 reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) | 521 VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) | 522 VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom); 523 524 cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg); 525 526 /* Decoded picture size. */ 527 528 reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) | 529 VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(ctx->src_fmt.height); 530 531 cedrus_write(dev, VE_DEC_H265_DEC_PIC_SIZE, reg); 532 533 /* Scaling list. */ 534 535 reg = VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT; 536 cedrus_write(dev, VE_DEC_H265_SCALING_LIST_CTRL0, reg); 537 538 /* Neightbor information address. */ 539 reg = VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(ctx->codec.h265.neighbor_info_buf_addr); 540 cedrus_write(dev, VE_DEC_H265_NEIGHBOR_INFO_ADDR, reg); 541 542 /* Write decoded picture buffer in pic list. */ 543 cedrus_h265_frame_info_write_dpb(ctx, decode_params->dpb, 544 decode_params->num_active_dpb_entries); 545 546 /* Output frame. */ 547 548 output_pic_list_index = V4L2_HEVC_DPB_ENTRIES_NUM_MAX; 549 pic_order_cnt[0] = slice_params->slice_pic_order_cnt; 550 pic_order_cnt[1] = slice_params->slice_pic_order_cnt; 551 552 cedrus_h265_frame_info_write_single(ctx, output_pic_list_index, 553 slice_params->pic_struct != 0, 554 pic_order_cnt, 555 run->dst->vb2_buf.index); 556 557 cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index); 558 559 /* Reference picture list 0 (for P/B frames). */ 560 if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) { 561 cedrus_h265_ref_pic_list_write(dev, decode_params->dpb, 562 slice_params->ref_idx_l0, 563 slice_params->num_ref_idx_l0_active_minus1 + 1, 564 VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0); 565 566 if ((pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED) || 567 (pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED)) 568 cedrus_h265_pred_weight_write(dev, 569 pred_weight_table->delta_luma_weight_l0, 570 pred_weight_table->luma_offset_l0, 571 pred_weight_table->delta_chroma_weight_l0, 572 pred_weight_table->chroma_offset_l0, 573 slice_params->num_ref_idx_l0_active_minus1 + 1, 574 VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0, 575 VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0); 576 } 577 578 /* Reference picture list 1 (for B frames). */ 579 if (slice_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) { 580 cedrus_h265_ref_pic_list_write(dev, decode_params->dpb, 581 slice_params->ref_idx_l1, 582 slice_params->num_ref_idx_l1_active_minus1 + 1, 583 VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1); 584 585 if (pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED) 586 cedrus_h265_pred_weight_write(dev, 587 pred_weight_table->delta_luma_weight_l1, 588 pred_weight_table->luma_offset_l1, 589 pred_weight_table->delta_chroma_weight_l1, 590 pred_weight_table->chroma_offset_l1, 591 slice_params->num_ref_idx_l1_active_minus1 + 1, 592 VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1, 593 VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1); 594 } 595 596 /* Enable appropriate interruptions. */ 597 cedrus_write(dev, VE_DEC_H265_CTRL, VE_DEC_H265_CTRL_IRQ_MASK); 598 } 599 600 static int cedrus_h265_start(struct cedrus_ctx *ctx) 601 { 602 struct cedrus_dev *dev = ctx->dev; 603 604 /* The buffer size is calculated at setup time. */ 605 ctx->codec.h265.mv_col_buf_size = 0; 606 607 ctx->codec.h265.neighbor_info_buf = 608 dma_alloc_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, 609 &ctx->codec.h265.neighbor_info_buf_addr, 610 GFP_KERNEL); 611 if (!ctx->codec.h265.neighbor_info_buf) 612 return -ENOMEM; 613 614 return 0; 615 } 616 617 static void cedrus_h265_stop(struct cedrus_ctx *ctx) 618 { 619 struct cedrus_dev *dev = ctx->dev; 620 621 if (ctx->codec.h265.mv_col_buf_size > 0) { 622 dma_free_coherent(dev->dev, ctx->codec.h265.mv_col_buf_size, 623 ctx->codec.h265.mv_col_buf, 624 ctx->codec.h265.mv_col_buf_addr); 625 626 ctx->codec.h265.mv_col_buf_size = 0; 627 } 628 629 dma_free_coherent(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE, 630 ctx->codec.h265.neighbor_info_buf, 631 ctx->codec.h265.neighbor_info_buf_addr); 632 } 633 634 static void cedrus_h265_trigger(struct cedrus_ctx *ctx) 635 { 636 struct cedrus_dev *dev = ctx->dev; 637 638 cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_DEC_SLICE); 639 } 640 641 struct cedrus_dec_ops cedrus_dec_ops_h265 = { 642 .irq_clear = cedrus_h265_irq_clear, 643 .irq_disable = cedrus_h265_irq_disable, 644 .irq_status = cedrus_h265_irq_status, 645 .setup = cedrus_h265_setup, 646 .start = cedrus_h265_start, 647 .stop = cedrus_h265_stop, 648 .trigger = cedrus_h265_trigger, 649 }; 650