1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Cedrus VPU driver 4 * 5 * Copyright (c) 2013 Jens Kuske <jenskuske@gmail.com> 6 * Copyright (c) 2018 Bootlin 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/types.h> 11 12 #include <media/videobuf2-dma-contig.h> 13 14 #include "cedrus.h" 15 #include "cedrus_hw.h" 16 #include "cedrus_regs.h" 17 18 enum cedrus_h264_sram_off { 19 CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE = 0x000, 20 CEDRUS_SRAM_H264_FRAMEBUFFER_LIST = 0x100, 21 CEDRUS_SRAM_H264_REF_LIST_0 = 0x190, 22 CEDRUS_SRAM_H264_REF_LIST_1 = 0x199, 23 CEDRUS_SRAM_H264_SCALING_LIST_8x8_0 = 0x200, 24 CEDRUS_SRAM_H264_SCALING_LIST_8x8_1 = 0x210, 25 CEDRUS_SRAM_H264_SCALING_LIST_4x4 = 0x220, 26 }; 27 28 struct cedrus_h264_sram_ref_pic { 29 __le32 top_field_order_cnt; 30 __le32 bottom_field_order_cnt; 31 __le32 frame_info; 32 __le32 luma_ptr; 33 __le32 chroma_ptr; 34 __le32 mv_col_top_ptr; 35 __le32 mv_col_bot_ptr; 36 __le32 reserved; 37 } __packed; 38 39 #define CEDRUS_H264_FRAME_NUM 18 40 41 #define CEDRUS_NEIGHBOR_INFO_BUF_SIZE (16 * SZ_1K) 42 #define CEDRUS_MIN_PIC_INFO_BUF_SIZE (130 * SZ_1K) 43 44 static void cedrus_h264_write_sram(struct cedrus_dev *dev, 45 enum cedrus_h264_sram_off off, 46 const void *data, size_t len) 47 { 48 const u32 *buffer = data; 49 size_t count = DIV_ROUND_UP(len, 4); 50 51 cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, off << 2); 52 53 while (count--) 54 cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, *buffer++); 55 } 56 57 static dma_addr_t cedrus_h264_mv_col_buf_addr(struct cedrus_ctx *ctx, 58 unsigned int position, 59 unsigned int field) 60 { 61 dma_addr_t addr = ctx->codec.h264.mv_col_buf_dma; 62 63 /* Adjust for the position */ 64 addr += position * ctx->codec.h264.mv_col_buf_field_size * 2; 65 66 /* Adjust for the field */ 67 addr += field * ctx->codec.h264.mv_col_buf_field_size; 68 69 return addr; 70 } 71 72 static void cedrus_fill_ref_pic(struct cedrus_ctx *ctx, 73 struct cedrus_buffer *buf, 74 unsigned int top_field_order_cnt, 75 unsigned int bottom_field_order_cnt, 76 struct cedrus_h264_sram_ref_pic *pic) 77 { 78 struct vb2_buffer *vbuf = &buf->m2m_buf.vb.vb2_buf; 79 unsigned int position = buf->codec.h264.position; 80 81 pic->top_field_order_cnt = cpu_to_le32(top_field_order_cnt); 82 pic->bottom_field_order_cnt = cpu_to_le32(bottom_field_order_cnt); 83 pic->frame_info = cpu_to_le32(buf->codec.h264.pic_type << 8); 84 85 pic->luma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 0)); 86 pic->chroma_ptr = cpu_to_le32(cedrus_buf_addr(vbuf, &ctx->dst_fmt, 1)); 87 pic->mv_col_top_ptr = 88 cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 0)); 89 pic->mv_col_bot_ptr = 90 cpu_to_le32(cedrus_h264_mv_col_buf_addr(ctx, position, 1)); 91 } 92 93 static void cedrus_write_frame_list(struct cedrus_ctx *ctx, 94 struct cedrus_run *run) 95 { 96 struct cedrus_h264_sram_ref_pic pic_list[CEDRUS_H264_FRAME_NUM]; 97 const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; 98 const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; 99 struct vb2_queue *cap_q; 100 struct cedrus_buffer *output_buf; 101 struct cedrus_dev *dev = ctx->dev; 102 unsigned long used_dpbs = 0; 103 unsigned int position; 104 unsigned int output = 0; 105 unsigned int i; 106 107 cap_q = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); 108 109 memset(pic_list, 0, sizeof(pic_list)); 110 111 for (i = 0; i < ARRAY_SIZE(decode->dpb); i++) { 112 const struct v4l2_h264_dpb_entry *dpb = &decode->dpb[i]; 113 struct cedrus_buffer *cedrus_buf; 114 int buf_idx; 115 116 if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_VALID)) 117 continue; 118 119 buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); 120 if (buf_idx < 0) 121 continue; 122 123 cedrus_buf = vb2_to_cedrus_buffer(cap_q->bufs[buf_idx]); 124 position = cedrus_buf->codec.h264.position; 125 used_dpbs |= BIT(position); 126 127 if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) 128 continue; 129 130 cedrus_fill_ref_pic(ctx, cedrus_buf, 131 dpb->top_field_order_cnt, 132 dpb->bottom_field_order_cnt, 133 &pic_list[position]); 134 135 output = max(position, output); 136 } 137 138 position = find_next_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM, 139 output); 140 if (position >= CEDRUS_H264_FRAME_NUM) 141 position = find_first_zero_bit(&used_dpbs, CEDRUS_H264_FRAME_NUM); 142 143 output_buf = vb2_to_cedrus_buffer(&run->dst->vb2_buf); 144 output_buf->codec.h264.position = position; 145 146 if (decode->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) 147 output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FIELD; 148 else if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) 149 output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_MBAFF; 150 else 151 output_buf->codec.h264.pic_type = CEDRUS_H264_PIC_TYPE_FRAME; 152 153 cedrus_fill_ref_pic(ctx, output_buf, 154 decode->top_field_order_cnt, 155 decode->bottom_field_order_cnt, 156 &pic_list[position]); 157 158 cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_FRAMEBUFFER_LIST, 159 pic_list, sizeof(pic_list)); 160 161 cedrus_write(dev, VE_H264_OUTPUT_FRAME_IDX, position); 162 } 163 164 #define CEDRUS_MAX_REF_IDX 32 165 166 static void _cedrus_write_ref_list(struct cedrus_ctx *ctx, 167 struct cedrus_run *run, 168 const struct v4l2_h264_reference *ref_list, 169 u8 num_ref, enum cedrus_h264_sram_off sram) 170 { 171 const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; 172 struct vb2_queue *cap_q; 173 struct cedrus_dev *dev = ctx->dev; 174 u8 sram_array[CEDRUS_MAX_REF_IDX]; 175 unsigned int i; 176 size_t size; 177 178 cap_q = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); 179 180 memset(sram_array, 0, sizeof(sram_array)); 181 182 for (i = 0; i < num_ref; i++) { 183 const struct v4l2_h264_dpb_entry *dpb; 184 const struct cedrus_buffer *cedrus_buf; 185 const struct vb2_v4l2_buffer *ref_buf; 186 unsigned int position; 187 int buf_idx; 188 u8 dpb_idx; 189 190 dpb_idx = ref_list[i].index; 191 dpb = &decode->dpb[dpb_idx]; 192 193 if (!(dpb->flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) 194 continue; 195 196 buf_idx = vb2_find_timestamp(cap_q, dpb->reference_ts, 0); 197 if (buf_idx < 0) 198 continue; 199 200 ref_buf = to_vb2_v4l2_buffer(cap_q->bufs[buf_idx]); 201 cedrus_buf = vb2_v4l2_to_cedrus_buffer(ref_buf); 202 position = cedrus_buf->codec.h264.position; 203 204 sram_array[i] |= position << 1; 205 if (ref_buf->field == V4L2_FIELD_BOTTOM) 206 sram_array[i] |= BIT(0); 207 } 208 209 size = min_t(size_t, ALIGN(num_ref, 4), sizeof(sram_array)); 210 cedrus_h264_write_sram(dev, sram, &sram_array, size); 211 } 212 213 static void cedrus_write_ref_list0(struct cedrus_ctx *ctx, 214 struct cedrus_run *run) 215 { 216 const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; 217 218 _cedrus_write_ref_list(ctx, run, 219 slice->ref_pic_list0, 220 slice->num_ref_idx_l0_active_minus1 + 1, 221 CEDRUS_SRAM_H264_REF_LIST_0); 222 } 223 224 static void cedrus_write_ref_list1(struct cedrus_ctx *ctx, 225 struct cedrus_run *run) 226 { 227 const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; 228 229 _cedrus_write_ref_list(ctx, run, 230 slice->ref_pic_list1, 231 slice->num_ref_idx_l1_active_minus1 + 1, 232 CEDRUS_SRAM_H264_REF_LIST_1); 233 } 234 235 static void cedrus_write_scaling_lists(struct cedrus_ctx *ctx, 236 struct cedrus_run *run) 237 { 238 const struct v4l2_ctrl_h264_scaling_matrix *scaling = 239 run->h264.scaling_matrix; 240 struct cedrus_dev *dev = ctx->dev; 241 242 cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_0, 243 scaling->scaling_list_8x8[0], 244 sizeof(scaling->scaling_list_8x8[0])); 245 246 cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_8x8_1, 247 scaling->scaling_list_8x8[1], 248 sizeof(scaling->scaling_list_8x8[1])); 249 250 cedrus_h264_write_sram(dev, CEDRUS_SRAM_H264_SCALING_LIST_4x4, 251 scaling->scaling_list_4x4, 252 sizeof(scaling->scaling_list_4x4)); 253 } 254 255 static void cedrus_write_pred_weight_table(struct cedrus_ctx *ctx, 256 struct cedrus_run *run) 257 { 258 const struct v4l2_ctrl_h264_pred_weights *pred_weight = 259 run->h264.pred_weights; 260 struct cedrus_dev *dev = ctx->dev; 261 int i, j, k; 262 263 cedrus_write(dev, VE_H264_SHS_WP, 264 ((pred_weight->chroma_log2_weight_denom & 0x7) << 4) | 265 ((pred_weight->luma_log2_weight_denom & 0x7) << 0)); 266 267 cedrus_write(dev, VE_AVC_SRAM_PORT_OFFSET, 268 CEDRUS_SRAM_H264_PRED_WEIGHT_TABLE << 2); 269 270 for (i = 0; i < ARRAY_SIZE(pred_weight->weight_factors); i++) { 271 const struct v4l2_h264_weight_factors *factors = 272 &pred_weight->weight_factors[i]; 273 274 for (j = 0; j < ARRAY_SIZE(factors->luma_weight); j++) { 275 u32 val; 276 277 val = (((u32)factors->luma_offset[j] & 0x1ff) << 16) | 278 (factors->luma_weight[j] & 0x1ff); 279 cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); 280 } 281 282 for (j = 0; j < ARRAY_SIZE(factors->chroma_weight); j++) { 283 for (k = 0; k < ARRAY_SIZE(factors->chroma_weight[0]); k++) { 284 u32 val; 285 286 val = (((u32)factors->chroma_offset[j][k] & 0x1ff) << 16) | 287 (factors->chroma_weight[j][k] & 0x1ff); 288 cedrus_write(dev, VE_AVC_SRAM_PORT_DATA, val); 289 } 290 } 291 } 292 } 293 294 /* 295 * It turns out that using VE_H264_VLD_OFFSET to skip bits is not reliable. In 296 * rare cases frame is not decoded correctly. However, setting offset to 0 and 297 * skipping appropriate amount of bits with flush bits trigger always works. 298 */ 299 static void cedrus_skip_bits(struct cedrus_dev *dev, int num) 300 { 301 int count = 0; 302 303 while (count < num) { 304 int tmp = min(num - count, 32); 305 306 cedrus_write(dev, VE_H264_TRIGGER_TYPE, 307 VE_H264_TRIGGER_TYPE_FLUSH_BITS | 308 VE_H264_TRIGGER_TYPE_N_BITS(tmp)); 309 while (cedrus_read(dev, VE_H264_STATUS) & VE_H264_STATUS_VLD_BUSY) 310 udelay(1); 311 312 count += tmp; 313 } 314 } 315 316 static void cedrus_set_params(struct cedrus_ctx *ctx, 317 struct cedrus_run *run) 318 { 319 const struct v4l2_ctrl_h264_decode_params *decode = run->h264.decode_params; 320 const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; 321 const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; 322 const struct v4l2_ctrl_h264_sps *sps = run->h264.sps; 323 struct vb2_buffer *src_buf = &run->src->vb2_buf; 324 struct cedrus_dev *dev = ctx->dev; 325 dma_addr_t src_buf_addr; 326 size_t slice_bytes = vb2_get_plane_payload(src_buf, 0); 327 unsigned int pic_width_in_mbs; 328 bool mbaff_pic; 329 u32 reg; 330 331 cedrus_write(dev, VE_H264_VLD_LEN, slice_bytes * 8); 332 cedrus_write(dev, VE_H264_VLD_OFFSET, 0); 333 334 src_buf_addr = vb2_dma_contig_plane_dma_addr(src_buf, 0); 335 cedrus_write(dev, VE_H264_VLD_END, src_buf_addr + slice_bytes); 336 cedrus_write(dev, VE_H264_VLD_ADDR, 337 VE_H264_VLD_ADDR_VAL(src_buf_addr) | 338 VE_H264_VLD_ADDR_FIRST | VE_H264_VLD_ADDR_VALID | 339 VE_H264_VLD_ADDR_LAST); 340 341 if (ctx->src_fmt.width > 2048) { 342 cedrus_write(dev, VE_BUF_CTRL, 343 VE_BUF_CTRL_INTRAPRED_MIXED_RAM | 344 VE_BUF_CTRL_DBLK_MIXED_RAM); 345 cedrus_write(dev, VE_DBLK_DRAM_BUF_ADDR, 346 ctx->codec.h264.deblk_buf_dma); 347 cedrus_write(dev, VE_INTRAPRED_DRAM_BUF_ADDR, 348 ctx->codec.h264.intra_pred_buf_dma); 349 } else { 350 cedrus_write(dev, VE_BUF_CTRL, 351 VE_BUF_CTRL_INTRAPRED_INT_SRAM | 352 VE_BUF_CTRL_DBLK_INT_SRAM); 353 } 354 355 /* 356 * FIXME: Since the bitstream parsing is done in software, and 357 * in userspace, this shouldn't be needed anymore. But it 358 * turns out that removing it breaks the decoding process, 359 * without any clear indication why. 360 */ 361 cedrus_write(dev, VE_H264_TRIGGER_TYPE, 362 VE_H264_TRIGGER_TYPE_INIT_SWDEC); 363 364 cedrus_skip_bits(dev, slice->header_bit_size); 365 366 if (V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice)) 367 cedrus_write_pred_weight_table(ctx, run); 368 369 if ((slice->slice_type == V4L2_H264_SLICE_TYPE_P) || 370 (slice->slice_type == V4L2_H264_SLICE_TYPE_SP) || 371 (slice->slice_type == V4L2_H264_SLICE_TYPE_B)) 372 cedrus_write_ref_list0(ctx, run); 373 374 if (slice->slice_type == V4L2_H264_SLICE_TYPE_B) 375 cedrus_write_ref_list1(ctx, run); 376 377 // picture parameters 378 reg = 0; 379 /* 380 * FIXME: the kernel headers are allowing the default value to 381 * be passed, but the libva doesn't give us that. 382 */ 383 reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 10; 384 reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 5; 385 reg |= (pps->weighted_bipred_idc & 0x3) << 2; 386 if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) 387 reg |= VE_H264_PPS_ENTROPY_CODING_MODE; 388 if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) 389 reg |= VE_H264_PPS_WEIGHTED_PRED; 390 if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) 391 reg |= VE_H264_PPS_CONSTRAINED_INTRA_PRED; 392 if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) 393 reg |= VE_H264_PPS_TRANSFORM_8X8_MODE; 394 cedrus_write(dev, VE_H264_PPS, reg); 395 396 // sequence parameters 397 reg = 0; 398 reg |= (sps->chroma_format_idc & 0x7) << 19; 399 reg |= (sps->pic_width_in_mbs_minus1 & 0xff) << 8; 400 reg |= sps->pic_height_in_map_units_minus1 & 0xff; 401 if (sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) 402 reg |= VE_H264_SPS_MBS_ONLY; 403 if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) 404 reg |= VE_H264_SPS_MB_ADAPTIVE_FRAME_FIELD; 405 if (sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) 406 reg |= VE_H264_SPS_DIRECT_8X8_INFERENCE; 407 cedrus_write(dev, VE_H264_SPS, reg); 408 409 mbaff_pic = !(decode->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) && 410 (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD); 411 pic_width_in_mbs = sps->pic_width_in_mbs_minus1 + 1; 412 413 // slice parameters 414 reg = 0; 415 reg |= ((slice->first_mb_in_slice % pic_width_in_mbs) & 0xff) << 24; 416 reg |= (((slice->first_mb_in_slice / pic_width_in_mbs) * 417 (mbaff_pic + 1)) & 0xff) << 16; 418 reg |= decode->nal_ref_idc ? BIT(12) : 0; 419 reg |= (slice->slice_type & 0xf) << 8; 420 reg |= slice->cabac_init_idc & 0x3; 421 if (ctx->fh.m2m_ctx->new_frame) 422 reg |= VE_H264_SHS_FIRST_SLICE_IN_PIC; 423 if (decode->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC) 424 reg |= VE_H264_SHS_FIELD_PIC; 425 if (decode->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD) 426 reg |= VE_H264_SHS_BOTTOM_FIELD; 427 if (slice->flags & V4L2_H264_SLICE_FLAG_DIRECT_SPATIAL_MV_PRED) 428 reg |= VE_H264_SHS_DIRECT_SPATIAL_MV_PRED; 429 cedrus_write(dev, VE_H264_SHS, reg); 430 431 reg = 0; 432 reg |= VE_H264_SHS2_NUM_REF_IDX_ACTIVE_OVRD; 433 reg |= (slice->num_ref_idx_l0_active_minus1 & 0x1f) << 24; 434 reg |= (slice->num_ref_idx_l1_active_minus1 & 0x1f) << 16; 435 reg |= (slice->disable_deblocking_filter_idc & 0x3) << 8; 436 reg |= (slice->slice_alpha_c0_offset_div2 & 0xf) << 4; 437 reg |= slice->slice_beta_offset_div2 & 0xf; 438 cedrus_write(dev, VE_H264_SHS2, reg); 439 440 reg = 0; 441 reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; 442 reg |= (pps->chroma_qp_index_offset & 0x3f) << 8; 443 reg |= (pps->pic_init_qp_minus26 + 26 + slice->slice_qp_delta) & 0x3f; 444 cedrus_write(dev, VE_H264_SHS_QP, reg); 445 446 // clear status flags 447 cedrus_write(dev, VE_H264_STATUS, cedrus_read(dev, VE_H264_STATUS)); 448 449 // enable int 450 cedrus_write(dev, VE_H264_CTRL, 451 VE_H264_CTRL_SLICE_DECODE_INT | 452 VE_H264_CTRL_DECODE_ERR_INT | 453 VE_H264_CTRL_VLD_DATA_REQ_INT); 454 } 455 456 static enum cedrus_irq_status 457 cedrus_h264_irq_status(struct cedrus_ctx *ctx) 458 { 459 struct cedrus_dev *dev = ctx->dev; 460 u32 reg = cedrus_read(dev, VE_H264_STATUS); 461 462 if (reg & (VE_H264_STATUS_DECODE_ERR_INT | 463 VE_H264_STATUS_VLD_DATA_REQ_INT)) 464 return CEDRUS_IRQ_ERROR; 465 466 if (reg & VE_H264_CTRL_SLICE_DECODE_INT) 467 return CEDRUS_IRQ_OK; 468 469 return CEDRUS_IRQ_NONE; 470 } 471 472 static void cedrus_h264_irq_clear(struct cedrus_ctx *ctx) 473 { 474 struct cedrus_dev *dev = ctx->dev; 475 476 cedrus_write(dev, VE_H264_STATUS, 477 VE_H264_STATUS_INT_MASK); 478 } 479 480 static void cedrus_h264_irq_disable(struct cedrus_ctx *ctx) 481 { 482 struct cedrus_dev *dev = ctx->dev; 483 u32 reg = cedrus_read(dev, VE_H264_CTRL); 484 485 cedrus_write(dev, VE_H264_CTRL, 486 reg & ~VE_H264_CTRL_INT_MASK); 487 } 488 489 static void cedrus_h264_setup(struct cedrus_ctx *ctx, 490 struct cedrus_run *run) 491 { 492 struct cedrus_dev *dev = ctx->dev; 493 494 cedrus_engine_enable(ctx, CEDRUS_CODEC_H264); 495 496 cedrus_write(dev, VE_H264_SDROT_CTRL, 0); 497 cedrus_write(dev, VE_H264_EXTRA_BUFFER1, 498 ctx->codec.h264.pic_info_buf_dma); 499 cedrus_write(dev, VE_H264_EXTRA_BUFFER2, 500 ctx->codec.h264.neighbor_info_buf_dma); 501 502 cedrus_write_scaling_lists(ctx, run); 503 cedrus_write_frame_list(ctx, run); 504 505 cedrus_set_params(ctx, run); 506 } 507 508 static int cedrus_h264_start(struct cedrus_ctx *ctx) 509 { 510 struct cedrus_dev *dev = ctx->dev; 511 unsigned int pic_info_size; 512 unsigned int field_size; 513 unsigned int mv_col_size; 514 int ret; 515 516 /* Formula for picture buffer size is taken from CedarX source. */ 517 518 if (ctx->src_fmt.width > 2048) 519 pic_info_size = CEDRUS_H264_FRAME_NUM * 0x4000; 520 else 521 pic_info_size = CEDRUS_H264_FRAME_NUM * 0x1000; 522 523 /* 524 * FIXME: If V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY is set, 525 * there is no need to multiply by 2. 526 */ 527 pic_info_size += ctx->src_fmt.height * 2 * 64; 528 529 if (pic_info_size < CEDRUS_MIN_PIC_INFO_BUF_SIZE) 530 pic_info_size = CEDRUS_MIN_PIC_INFO_BUF_SIZE; 531 532 ctx->codec.h264.pic_info_buf_size = pic_info_size; 533 ctx->codec.h264.pic_info_buf = 534 dma_alloc_coherent(dev->dev, ctx->codec.h264.pic_info_buf_size, 535 &ctx->codec.h264.pic_info_buf_dma, 536 GFP_KERNEL); 537 if (!ctx->codec.h264.pic_info_buf) 538 return -ENOMEM; 539 540 /* 541 * That buffer is supposed to be 16kiB in size, and be aligned 542 * on 16kiB as well. However, dma_alloc_coherent provides the 543 * guarantee that we'll have a CPU and DMA address aligned on 544 * the smallest page order that is greater to the requested 545 * size, so we don't have to overallocate. 546 */ 547 ctx->codec.h264.neighbor_info_buf = 548 dma_alloc_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, 549 &ctx->codec.h264.neighbor_info_buf_dma, 550 GFP_KERNEL); 551 if (!ctx->codec.h264.neighbor_info_buf) { 552 ret = -ENOMEM; 553 goto err_pic_buf; 554 } 555 556 field_size = DIV_ROUND_UP(ctx->src_fmt.width, 16) * 557 DIV_ROUND_UP(ctx->src_fmt.height, 16) * 16; 558 559 /* 560 * FIXME: This is actually conditional to 561 * V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE not being set, we 562 * might have to rework this if memory efficiency ever is 563 * something we need to work on. 564 */ 565 field_size = field_size * 2; 566 567 /* 568 * FIXME: This is actually conditional to 569 * V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY not being set, we might 570 * have to rework this if memory efficiency ever is something 571 * we need to work on. 572 */ 573 field_size = field_size * 2; 574 ctx->codec.h264.mv_col_buf_field_size = field_size; 575 576 mv_col_size = field_size * 2 * CEDRUS_H264_FRAME_NUM; 577 ctx->codec.h264.mv_col_buf_size = mv_col_size; 578 ctx->codec.h264.mv_col_buf = dma_alloc_coherent(dev->dev, 579 ctx->codec.h264.mv_col_buf_size, 580 &ctx->codec.h264.mv_col_buf_dma, 581 GFP_KERNEL); 582 if (!ctx->codec.h264.mv_col_buf) { 583 ret = -ENOMEM; 584 goto err_neighbor_buf; 585 } 586 587 if (ctx->src_fmt.width > 2048) { 588 /* 589 * Formulas for deblock and intra prediction buffer sizes 590 * are taken from CedarX source. 591 */ 592 593 ctx->codec.h264.deblk_buf_size = 594 ALIGN(ctx->src_fmt.width, 32) * 12; 595 ctx->codec.h264.deblk_buf = 596 dma_alloc_coherent(dev->dev, 597 ctx->codec.h264.deblk_buf_size, 598 &ctx->codec.h264.deblk_buf_dma, 599 GFP_KERNEL); 600 if (!ctx->codec.h264.deblk_buf) { 601 ret = -ENOMEM; 602 goto err_mv_col_buf; 603 } 604 605 /* 606 * NOTE: Multiplying by two deviates from CedarX logic, but it 607 * is for some unknown reason needed for H264 4K decoding on H6. 608 */ 609 ctx->codec.h264.intra_pred_buf_size = 610 ALIGN(ctx->src_fmt.width, 64) * 5 * 2; 611 ctx->codec.h264.intra_pred_buf = 612 dma_alloc_coherent(dev->dev, 613 ctx->codec.h264.intra_pred_buf_size, 614 &ctx->codec.h264.intra_pred_buf_dma, 615 GFP_KERNEL); 616 if (!ctx->codec.h264.intra_pred_buf) { 617 ret = -ENOMEM; 618 goto err_deblk_buf; 619 } 620 } 621 622 return 0; 623 624 err_deblk_buf: 625 dma_free_coherent(dev->dev, ctx->codec.h264.deblk_buf_size, 626 ctx->codec.h264.deblk_buf, 627 ctx->codec.h264.deblk_buf_dma); 628 629 err_mv_col_buf: 630 dma_free_coherent(dev->dev, ctx->codec.h264.mv_col_buf_size, 631 ctx->codec.h264.mv_col_buf, 632 ctx->codec.h264.mv_col_buf_dma); 633 634 err_neighbor_buf: 635 dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, 636 ctx->codec.h264.neighbor_info_buf, 637 ctx->codec.h264.neighbor_info_buf_dma); 638 639 err_pic_buf: 640 dma_free_coherent(dev->dev, ctx->codec.h264.pic_info_buf_size, 641 ctx->codec.h264.pic_info_buf, 642 ctx->codec.h264.pic_info_buf_dma); 643 return ret; 644 } 645 646 static void cedrus_h264_stop(struct cedrus_ctx *ctx) 647 { 648 struct cedrus_dev *dev = ctx->dev; 649 650 dma_free_coherent(dev->dev, ctx->codec.h264.mv_col_buf_size, 651 ctx->codec.h264.mv_col_buf, 652 ctx->codec.h264.mv_col_buf_dma); 653 dma_free_coherent(dev->dev, CEDRUS_NEIGHBOR_INFO_BUF_SIZE, 654 ctx->codec.h264.neighbor_info_buf, 655 ctx->codec.h264.neighbor_info_buf_dma); 656 dma_free_coherent(dev->dev, ctx->codec.h264.pic_info_buf_size, 657 ctx->codec.h264.pic_info_buf, 658 ctx->codec.h264.pic_info_buf_dma); 659 if (ctx->codec.h264.deblk_buf_size) 660 dma_free_coherent(dev->dev, ctx->codec.h264.deblk_buf_size, 661 ctx->codec.h264.deblk_buf, 662 ctx->codec.h264.deblk_buf_dma); 663 if (ctx->codec.h264.intra_pred_buf_size) 664 dma_free_coherent(dev->dev, ctx->codec.h264.intra_pred_buf_size, 665 ctx->codec.h264.intra_pred_buf, 666 ctx->codec.h264.intra_pred_buf_dma); 667 } 668 669 static void cedrus_h264_trigger(struct cedrus_ctx *ctx) 670 { 671 struct cedrus_dev *dev = ctx->dev; 672 673 cedrus_write(dev, VE_H264_TRIGGER_TYPE, 674 VE_H264_TRIGGER_TYPE_AVC_SLICE_DECODE); 675 } 676 677 struct cedrus_dec_ops cedrus_dec_ops_h264 = { 678 .irq_clear = cedrus_h264_irq_clear, 679 .irq_disable = cedrus_h264_irq_disable, 680 .irq_status = cedrus_h264_irq_status, 681 .setup = cedrus_h264_setup, 682 .start = cedrus_h264_start, 683 .stop = cedrus_h264_stop, 684 .trigger = cedrus_h264_trigger, 685 }; 686