1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Cedrus VPU driver 4 * 5 * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com> 6 * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com> 7 * Copyright (C) 2018 Bootlin 8 * 9 * Based on the vim2m driver, that is: 10 * 11 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. 12 * Pawel Osciak, <pawel@osciak.com> 13 * Marek Szyprowski, <m.szyprowski@samsung.com> 14 */ 15 16 #ifndef _CEDRUS_H_ 17 #define _CEDRUS_H_ 18 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-mem2mem.h> 22 #include <media/videobuf2-v4l2.h> 23 #include <media/videobuf2-dma-contig.h> 24 25 #include <linux/platform_device.h> 26 27 #define CEDRUS_NAME "cedrus" 28 29 #define CEDRUS_CAPABILITY_UNTILED BIT(0) 30 #define CEDRUS_CAPABILITY_H265_DEC BIT(1) 31 32 #define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0) 33 34 enum cedrus_codec { 35 CEDRUS_CODEC_MPEG2, 36 CEDRUS_CODEC_H264, 37 CEDRUS_CODEC_H265, 38 CEDRUS_CODEC_LAST, 39 }; 40 41 enum cedrus_irq_status { 42 CEDRUS_IRQ_NONE, 43 CEDRUS_IRQ_ERROR, 44 CEDRUS_IRQ_OK, 45 }; 46 47 enum cedrus_h264_pic_type { 48 CEDRUS_H264_PIC_TYPE_FRAME = 0, 49 CEDRUS_H264_PIC_TYPE_FIELD, 50 CEDRUS_H264_PIC_TYPE_MBAFF, 51 }; 52 53 struct cedrus_control { 54 struct v4l2_ctrl_config cfg; 55 enum cedrus_codec codec; 56 unsigned char required:1; 57 }; 58 59 struct cedrus_h264_run { 60 const struct v4l2_ctrl_h264_decode_params *decode_params; 61 const struct v4l2_ctrl_h264_pps *pps; 62 const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix; 63 const struct v4l2_ctrl_h264_slice_params *slice_params; 64 const struct v4l2_ctrl_h264_sps *sps; 65 }; 66 67 struct cedrus_mpeg2_run { 68 const struct v4l2_ctrl_mpeg2_slice_params *slice_params; 69 const struct v4l2_ctrl_mpeg2_quantization *quantization; 70 }; 71 72 struct cedrus_h265_run { 73 const struct v4l2_ctrl_hevc_sps *sps; 74 const struct v4l2_ctrl_hevc_pps *pps; 75 const struct v4l2_ctrl_hevc_slice_params *slice_params; 76 }; 77 78 struct cedrus_run { 79 struct vb2_v4l2_buffer *src; 80 struct vb2_v4l2_buffer *dst; 81 82 union { 83 struct cedrus_h264_run h264; 84 struct cedrus_mpeg2_run mpeg2; 85 struct cedrus_h265_run h265; 86 }; 87 }; 88 89 struct cedrus_buffer { 90 struct v4l2_m2m_buffer m2m_buf; 91 92 union { 93 struct { 94 unsigned int position; 95 enum cedrus_h264_pic_type pic_type; 96 } h264; 97 } codec; 98 }; 99 100 struct cedrus_ctx { 101 struct v4l2_fh fh; 102 struct cedrus_dev *dev; 103 104 struct v4l2_pix_format src_fmt; 105 struct v4l2_pix_format dst_fmt; 106 enum cedrus_codec current_codec; 107 108 struct v4l2_ctrl_handler hdl; 109 struct v4l2_ctrl **ctrls; 110 111 union { 112 struct { 113 void *mv_col_buf; 114 dma_addr_t mv_col_buf_dma; 115 ssize_t mv_col_buf_field_size; 116 ssize_t mv_col_buf_size; 117 void *pic_info_buf; 118 dma_addr_t pic_info_buf_dma; 119 ssize_t pic_info_buf_size; 120 void *neighbor_info_buf; 121 dma_addr_t neighbor_info_buf_dma; 122 void *deblk_buf; 123 dma_addr_t deblk_buf_dma; 124 ssize_t deblk_buf_size; 125 void *intra_pred_buf; 126 dma_addr_t intra_pred_buf_dma; 127 ssize_t intra_pred_buf_size; 128 } h264; 129 struct { 130 void *mv_col_buf; 131 dma_addr_t mv_col_buf_addr; 132 ssize_t mv_col_buf_size; 133 ssize_t mv_col_buf_unit_size; 134 void *neighbor_info_buf; 135 dma_addr_t neighbor_info_buf_addr; 136 } h265; 137 } codec; 138 }; 139 140 struct cedrus_dec_ops { 141 void (*irq_clear)(struct cedrus_ctx *ctx); 142 void (*irq_disable)(struct cedrus_ctx *ctx); 143 enum cedrus_irq_status (*irq_status)(struct cedrus_ctx *ctx); 144 void (*setup)(struct cedrus_ctx *ctx, struct cedrus_run *run); 145 int (*start)(struct cedrus_ctx *ctx); 146 void (*stop)(struct cedrus_ctx *ctx); 147 void (*trigger)(struct cedrus_ctx *ctx); 148 }; 149 150 struct cedrus_variant { 151 unsigned int capabilities; 152 unsigned int quirks; 153 unsigned int mod_rate; 154 }; 155 156 struct cedrus_dev { 157 struct v4l2_device v4l2_dev; 158 struct video_device vfd; 159 struct media_device mdev; 160 struct media_pad pad[2]; 161 struct platform_device *pdev; 162 struct device *dev; 163 struct v4l2_m2m_dev *m2m_dev; 164 struct cedrus_dec_ops *dec_ops[CEDRUS_CODEC_LAST]; 165 166 /* Device file mutex */ 167 struct mutex dev_mutex; 168 169 void __iomem *base; 170 171 struct clk *mod_clk; 172 struct clk *ahb_clk; 173 struct clk *ram_clk; 174 175 struct reset_control *rstc; 176 177 unsigned int capabilities; 178 }; 179 180 extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2; 181 extern struct cedrus_dec_ops cedrus_dec_ops_h264; 182 extern struct cedrus_dec_ops cedrus_dec_ops_h265; 183 184 static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val) 185 { 186 writel(val, dev->base + reg); 187 } 188 189 static inline u32 cedrus_read(struct cedrus_dev *dev, u32 reg) 190 { 191 return readl(dev->base + reg); 192 } 193 194 static inline dma_addr_t cedrus_buf_addr(struct vb2_buffer *buf, 195 struct v4l2_pix_format *pix_fmt, 196 unsigned int plane) 197 { 198 dma_addr_t addr = vb2_dma_contig_plane_dma_addr(buf, 0); 199 200 return addr + (pix_fmt ? (dma_addr_t)pix_fmt->bytesperline * 201 pix_fmt->height * plane : 0); 202 } 203 204 static inline dma_addr_t cedrus_dst_buf_addr(struct cedrus_ctx *ctx, 205 int index, unsigned int plane) 206 { 207 struct vb2_buffer *buf = NULL; 208 struct vb2_queue *vq; 209 210 if (index < 0) 211 return 0; 212 213 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE); 214 if (vq) 215 buf = vb2_get_buffer(vq, index); 216 217 return buf ? cedrus_buf_addr(buf, &ctx->dst_fmt, plane) : 0; 218 } 219 220 static inline struct cedrus_buffer * 221 vb2_v4l2_to_cedrus_buffer(const struct vb2_v4l2_buffer *p) 222 { 223 return container_of(p, struct cedrus_buffer, m2m_buf.vb); 224 } 225 226 static inline struct cedrus_buffer * 227 vb2_to_cedrus_buffer(const struct vb2_buffer *p) 228 { 229 return vb2_v4l2_to_cedrus_buffer(to_vb2_v4l2_buffer(p)); 230 } 231 232 void *cedrus_find_control_data(struct cedrus_ctx *ctx, u32 id); 233 234 #endif 235