159f0ad80SSergio Aguirre /* 259f0ad80SSergio Aguirre * TI OMAP4 ISS V4L2 Driver 359f0ad80SSergio Aguirre * 459f0ad80SSergio Aguirre * Copyright (C) 2012 Texas Instruments. 559f0ad80SSergio Aguirre * 659f0ad80SSergio Aguirre * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com> 759f0ad80SSergio Aguirre * 859f0ad80SSergio Aguirre * This program is free software; you can redistribute it and/or modify 959f0ad80SSergio Aguirre * it under the terms of the GNU General Public License as published by 1059f0ad80SSergio Aguirre * the Free Software Foundation; either version 2 of the License, or 1159f0ad80SSergio Aguirre * (at your option) any later version. 1259f0ad80SSergio Aguirre */ 1359f0ad80SSergio Aguirre 1459f0ad80SSergio Aguirre #ifndef _OMAP4_ISS_H_ 1559f0ad80SSergio Aguirre #define _OMAP4_ISS_H_ 1659f0ad80SSergio Aguirre 1759f0ad80SSergio Aguirre #include <media/v4l2-device.h> 1859f0ad80SSergio Aguirre #include <linux/device.h> 1959f0ad80SSergio Aguirre #include <linux/io.h> 2059f0ad80SSergio Aguirre #include <linux/platform_device.h> 2159f0ad80SSergio Aguirre #include <linux/wait.h> 2259f0ad80SSergio Aguirre 2359f0ad80SSergio Aguirre #include <media/omap4iss.h> 2459f0ad80SSergio Aguirre 2559f0ad80SSergio Aguirre #include "iss_regs.h" 2659f0ad80SSergio Aguirre #include "iss_csiphy.h" 2759f0ad80SSergio Aguirre #include "iss_csi2.h" 2859f0ad80SSergio Aguirre #include "iss_ipipeif.h" 2959f0ad80SSergio Aguirre #include "iss_ipipe.h" 3059f0ad80SSergio Aguirre #include "iss_resizer.h" 3159f0ad80SSergio Aguirre 32fefad2d5SLaurent Pinchart struct regmap; 33fefad2d5SLaurent Pinchart 3459f0ad80SSergio Aguirre #define to_iss_device(ptr_module) \ 3559f0ad80SSergio Aguirre container_of(ptr_module, struct iss_device, ptr_module) 3659f0ad80SSergio Aguirre #define to_device(ptr_module) \ 3759f0ad80SSergio Aguirre (to_iss_device(ptr_module)->dev) 3859f0ad80SSergio Aguirre 3959f0ad80SSergio Aguirre enum iss_mem_resources { 4059f0ad80SSergio Aguirre OMAP4_ISS_MEM_TOP, 4159f0ad80SSergio Aguirre OMAP4_ISS_MEM_CSI2_A_REGS1, 4259f0ad80SSergio Aguirre OMAP4_ISS_MEM_CAMERARX_CORE1, 4359f0ad80SSergio Aguirre OMAP4_ISS_MEM_CSI2_B_REGS1, 4459f0ad80SSergio Aguirre OMAP4_ISS_MEM_CAMERARX_CORE2, 4559f0ad80SSergio Aguirre OMAP4_ISS_MEM_BTE, 4659f0ad80SSergio Aguirre OMAP4_ISS_MEM_ISP_SYS1, 4759f0ad80SSergio Aguirre OMAP4_ISS_MEM_ISP_RESIZER, 4859f0ad80SSergio Aguirre OMAP4_ISS_MEM_ISP_IPIPE, 4959f0ad80SSergio Aguirre OMAP4_ISS_MEM_ISP_ISIF, 5059f0ad80SSergio Aguirre OMAP4_ISS_MEM_ISP_IPIPEIF, 5159f0ad80SSergio Aguirre OMAP4_ISS_MEM_LAST, 5259f0ad80SSergio Aguirre }; 5359f0ad80SSergio Aguirre 5459f0ad80SSergio Aguirre enum iss_subclk_resource { 5559f0ad80SSergio Aguirre OMAP4_ISS_SUBCLK_SIMCOP = (1 << 0), 5659f0ad80SSergio Aguirre OMAP4_ISS_SUBCLK_ISP = (1 << 1), 5759f0ad80SSergio Aguirre OMAP4_ISS_SUBCLK_CSI2_A = (1 << 2), 5859f0ad80SSergio Aguirre OMAP4_ISS_SUBCLK_CSI2_B = (1 << 3), 5959f0ad80SSergio Aguirre OMAP4_ISS_SUBCLK_CCP2 = (1 << 4), 6059f0ad80SSergio Aguirre }; 6159f0ad80SSergio Aguirre 6259f0ad80SSergio Aguirre enum iss_isp_subclk_resource { 6359f0ad80SSergio Aguirre OMAP4_ISS_ISP_SUBCLK_BL = (1 << 0), 6459f0ad80SSergio Aguirre OMAP4_ISS_ISP_SUBCLK_ISIF = (1 << 1), 6559f0ad80SSergio Aguirre OMAP4_ISS_ISP_SUBCLK_H3A = (1 << 2), 6659f0ad80SSergio Aguirre OMAP4_ISS_ISP_SUBCLK_RSZ = (1 << 3), 6759f0ad80SSergio Aguirre OMAP4_ISS_ISP_SUBCLK_IPIPE = (1 << 4), 6859f0ad80SSergio Aguirre OMAP4_ISS_ISP_SUBCLK_IPIPEIF = (1 << 5), 6959f0ad80SSergio Aguirre }; 7059f0ad80SSergio Aguirre 7159f0ad80SSergio Aguirre /* 7259f0ad80SSergio Aguirre * struct iss_reg - Structure for ISS register values. 7359f0ad80SSergio Aguirre * @reg: 32-bit Register address. 7459f0ad80SSergio Aguirre * @val: 32-bit Register value. 7559f0ad80SSergio Aguirre */ 7659f0ad80SSergio Aguirre struct iss_reg { 7759f0ad80SSergio Aguirre enum iss_mem_resources mmio_range; 7859f0ad80SSergio Aguirre u32 reg; 7959f0ad80SSergio Aguirre u32 val; 8059f0ad80SSergio Aguirre }; 8159f0ad80SSergio Aguirre 82f3632ba8SLaurent Pinchart /* 83f3632ba8SLaurent Pinchart * struct iss_device - ISS device structure. 84fefad2d5SLaurent Pinchart * @syscon: Regmap for the syscon register space 85f3632ba8SLaurent Pinchart * @crashed: Bitmask of crashed entities (indexed by entity ID) 86f3632ba8SLaurent Pinchart */ 8759f0ad80SSergio Aguirre struct iss_device { 8859f0ad80SSergio Aguirre struct v4l2_device v4l2_dev; 8959f0ad80SSergio Aguirre struct media_device media_dev; 9059f0ad80SSergio Aguirre struct device *dev; 9159f0ad80SSergio Aguirre u32 revision; 9259f0ad80SSergio Aguirre 9359f0ad80SSergio Aguirre /* platform HW resources */ 9459f0ad80SSergio Aguirre struct iss_platform_data *pdata; 9559f0ad80SSergio Aguirre unsigned int irq_num; 9659f0ad80SSergio Aguirre 9759f0ad80SSergio Aguirre struct resource *res[OMAP4_ISS_MEM_LAST]; 9859f0ad80SSergio Aguirre void __iomem *regs[OMAP4_ISS_MEM_LAST]; 99fefad2d5SLaurent Pinchart struct regmap *syscon; 10059f0ad80SSergio Aguirre 10159f0ad80SSergio Aguirre u64 raw_dmamask; 10259f0ad80SSergio Aguirre 10359f0ad80SSergio Aguirre struct mutex iss_mutex; /* For handling ref_count field */ 104c6e58110SRasmus Villemoes unsigned int crashed; 10559f0ad80SSergio Aguirre int has_context; 10659f0ad80SSergio Aguirre int ref_count; 10759f0ad80SSergio Aguirre 10859f0ad80SSergio Aguirre struct clk *iss_fck; 10959f0ad80SSergio Aguirre struct clk *iss_ctrlclk; 11059f0ad80SSergio Aguirre 11159f0ad80SSergio Aguirre /* ISS modules */ 11259f0ad80SSergio Aguirre struct iss_csi2_device csi2a; 11359f0ad80SSergio Aguirre struct iss_csi2_device csi2b; 11459f0ad80SSergio Aguirre struct iss_csiphy csiphy1; 11559f0ad80SSergio Aguirre struct iss_csiphy csiphy2; 11659f0ad80SSergio Aguirre struct iss_ipipeif_device ipipeif; 11759f0ad80SSergio Aguirre struct iss_ipipe_device ipipe; 11859f0ad80SSergio Aguirre struct iss_resizer_device resizer; 11959f0ad80SSergio Aguirre 12059f0ad80SSergio Aguirre unsigned int subclk_resources; 12159f0ad80SSergio Aguirre unsigned int isp_subclk_resources; 12259f0ad80SSergio Aguirre }; 12359f0ad80SSergio Aguirre 12459f0ad80SSergio Aguirre #define v4l2_dev_to_iss_device(dev) \ 12559f0ad80SSergio Aguirre container_of(dev, struct iss_device, v4l2_dev) 12659f0ad80SSergio Aguirre 12759f0ad80SSergio Aguirre int omap4iss_get_external_info(struct iss_pipeline *pipe, 12859f0ad80SSergio Aguirre struct media_link *link); 12959f0ad80SSergio Aguirre 13059f0ad80SSergio Aguirre int omap4iss_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait, 13159f0ad80SSergio Aguirre atomic_t *stopping); 13259f0ad80SSergio Aguirre 13359f0ad80SSergio Aguirre int omap4iss_module_sync_is_stopping(wait_queue_head_t *wait, 13459f0ad80SSergio Aguirre atomic_t *stopping); 13559f0ad80SSergio Aguirre 13659f0ad80SSergio Aguirre int omap4iss_pipeline_set_stream(struct iss_pipeline *pipe, 13759f0ad80SSergio Aguirre enum iss_pipeline_stream_state state); 138112da085SLaurent Pinchart void omap4iss_pipeline_cancel_stream(struct iss_pipeline *pipe); 13959f0ad80SSergio Aguirre 14059f0ad80SSergio Aguirre void omap4iss_configure_bridge(struct iss_device *iss, 14159f0ad80SSergio Aguirre enum ipipeif_input_entity input); 14259f0ad80SSergio Aguirre 14359f0ad80SSergio Aguirre struct iss_device *omap4iss_get(struct iss_device *iss); 14459f0ad80SSergio Aguirre void omap4iss_put(struct iss_device *iss); 14559f0ad80SSergio Aguirre int omap4iss_subclk_enable(struct iss_device *iss, 14659f0ad80SSergio Aguirre enum iss_subclk_resource res); 14759f0ad80SSergio Aguirre int omap4iss_subclk_disable(struct iss_device *iss, 14859f0ad80SSergio Aguirre enum iss_subclk_resource res); 14968c03a66SLaurent Pinchart void omap4iss_isp_subclk_enable(struct iss_device *iss, 15059f0ad80SSergio Aguirre enum iss_isp_subclk_resource res); 15168c03a66SLaurent Pinchart void omap4iss_isp_subclk_disable(struct iss_device *iss, 15259f0ad80SSergio Aguirre enum iss_isp_subclk_resource res); 15359f0ad80SSergio Aguirre 15459f0ad80SSergio Aguirre int omap4iss_pipeline_pm_use(struct media_entity *entity, int use); 15559f0ad80SSergio Aguirre 15659f0ad80SSergio Aguirre int omap4iss_register_entities(struct platform_device *pdev, 15759f0ad80SSergio Aguirre struct v4l2_device *v4l2_dev); 15859f0ad80SSergio Aguirre void omap4iss_unregister_entities(struct platform_device *pdev); 15959f0ad80SSergio Aguirre 16011abbfd3SLaurent Pinchart /* 16111abbfd3SLaurent Pinchart * iss_reg_read - Read the value of an OMAP4 ISS register 16211abbfd3SLaurent Pinchart * @iss: the ISS device 16311abbfd3SLaurent Pinchart * @res: memory resource in which the register is located 16411abbfd3SLaurent Pinchart * @offset: register offset in the memory resource 16511abbfd3SLaurent Pinchart * 16611abbfd3SLaurent Pinchart * Return the register value. 16711abbfd3SLaurent Pinchart */ 16811abbfd3SLaurent Pinchart static inline 16911abbfd3SLaurent Pinchart u32 iss_reg_read(struct iss_device *iss, enum iss_mem_resources res, 17011abbfd3SLaurent Pinchart u32 offset) 17111abbfd3SLaurent Pinchart { 17211abbfd3SLaurent Pinchart return readl(iss->regs[res] + offset); 17311abbfd3SLaurent Pinchart } 17411abbfd3SLaurent Pinchart 17511abbfd3SLaurent Pinchart /* 17611abbfd3SLaurent Pinchart * iss_reg_write - Write a value to an OMAP4 ISS register 17711abbfd3SLaurent Pinchart * @iss: the ISS device 17811abbfd3SLaurent Pinchart * @res: memory resource in which the register is located 17911abbfd3SLaurent Pinchart * @offset: register offset in the memory resource 18011abbfd3SLaurent Pinchart * @value: value to be written 18111abbfd3SLaurent Pinchart */ 18211abbfd3SLaurent Pinchart static inline 18311abbfd3SLaurent Pinchart void iss_reg_write(struct iss_device *iss, enum iss_mem_resources res, 18411abbfd3SLaurent Pinchart u32 offset, u32 value) 18511abbfd3SLaurent Pinchart { 18611abbfd3SLaurent Pinchart writel(value, iss->regs[res] + offset); 18711abbfd3SLaurent Pinchart } 18811abbfd3SLaurent Pinchart 18911abbfd3SLaurent Pinchart /* 19011abbfd3SLaurent Pinchart * iss_reg_clr - Clear bits in an OMAP4 ISS register 19111abbfd3SLaurent Pinchart * @iss: the ISS device 19211abbfd3SLaurent Pinchart * @res: memory resource in which the register is located 19311abbfd3SLaurent Pinchart * @offset: register offset in the memory resource 19411abbfd3SLaurent Pinchart * @clr: bit mask to be cleared 19511abbfd3SLaurent Pinchart */ 19611abbfd3SLaurent Pinchart static inline 19711abbfd3SLaurent Pinchart void iss_reg_clr(struct iss_device *iss, enum iss_mem_resources res, 19811abbfd3SLaurent Pinchart u32 offset, u32 clr) 19911abbfd3SLaurent Pinchart { 20011abbfd3SLaurent Pinchart u32 v = iss_reg_read(iss, res, offset); 20111abbfd3SLaurent Pinchart 20211abbfd3SLaurent Pinchart iss_reg_write(iss, res, offset, v & ~clr); 20311abbfd3SLaurent Pinchart } 20411abbfd3SLaurent Pinchart 20511abbfd3SLaurent Pinchart /* 20611abbfd3SLaurent Pinchart * iss_reg_set - Set bits in an OMAP4 ISS register 20711abbfd3SLaurent Pinchart * @iss: the ISS device 20811abbfd3SLaurent Pinchart * @res: memory resource in which the register is located 20911abbfd3SLaurent Pinchart * @offset: register offset in the memory resource 21011abbfd3SLaurent Pinchart * @set: bit mask to be set 21111abbfd3SLaurent Pinchart */ 21211abbfd3SLaurent Pinchart static inline 21311abbfd3SLaurent Pinchart void iss_reg_set(struct iss_device *iss, enum iss_mem_resources res, 21411abbfd3SLaurent Pinchart u32 offset, u32 set) 21511abbfd3SLaurent Pinchart { 21611abbfd3SLaurent Pinchart u32 v = iss_reg_read(iss, res, offset); 21711abbfd3SLaurent Pinchart 21811abbfd3SLaurent Pinchart iss_reg_write(iss, res, offset, v | set); 21911abbfd3SLaurent Pinchart } 22011abbfd3SLaurent Pinchart 22111abbfd3SLaurent Pinchart /* 22211abbfd3SLaurent Pinchart * iss_reg_update - Clear and set bits in an OMAP4 ISS register 22311abbfd3SLaurent Pinchart * @iss: the ISS device 22411abbfd3SLaurent Pinchart * @res: memory resource in which the register is located 22511abbfd3SLaurent Pinchart * @offset: register offset in the memory resource 22611abbfd3SLaurent Pinchart * @clr: bit mask to be cleared 22711abbfd3SLaurent Pinchart * @set: bit mask to be set 22811abbfd3SLaurent Pinchart * 22911abbfd3SLaurent Pinchart * Clear the clr mask first and then set the set mask. 23011abbfd3SLaurent Pinchart */ 23111abbfd3SLaurent Pinchart static inline 23211abbfd3SLaurent Pinchart void iss_reg_update(struct iss_device *iss, enum iss_mem_resources res, 23311abbfd3SLaurent Pinchart u32 offset, u32 clr, u32 set) 23411abbfd3SLaurent Pinchart { 23511abbfd3SLaurent Pinchart u32 v = iss_reg_read(iss, res, offset); 23611abbfd3SLaurent Pinchart 23711abbfd3SLaurent Pinchart iss_reg_write(iss, res, offset, (v & ~clr) | set); 23811abbfd3SLaurent Pinchart } 23911abbfd3SLaurent Pinchart 24005b1b986SLaurent Pinchart #define iss_poll_condition_timeout(cond, timeout, min_ival, max_ival) \ 24105b1b986SLaurent Pinchart ({ \ 24205b1b986SLaurent Pinchart unsigned long __timeout = jiffies + usecs_to_jiffies(timeout); \ 24305b1b986SLaurent Pinchart unsigned int __min_ival = (min_ival); \ 24405b1b986SLaurent Pinchart unsigned int __max_ival = (max_ival); \ 24505b1b986SLaurent Pinchart bool __cond; \ 24605b1b986SLaurent Pinchart while (!(__cond = (cond))) { \ 24705b1b986SLaurent Pinchart if (time_after(jiffies, __timeout)) \ 24805b1b986SLaurent Pinchart break; \ 24905b1b986SLaurent Pinchart usleep_range(__min_ival, __max_ival); \ 25005b1b986SLaurent Pinchart } \ 25105b1b986SLaurent Pinchart !__cond; \ 25205b1b986SLaurent Pinchart }) 25305b1b986SLaurent Pinchart 25459f0ad80SSergio Aguirre #endif /* _OMAP4_ISS_H_ */ 255