115e2f1baSYong Zhi /* SPDX-License-Identifier: GPL-2.0 */ 215e2f1baSYong Zhi /* Copyright (C) 2018 Intel Corporation */ 315e2f1baSYong Zhi 415e2f1baSYong Zhi #ifndef __IPU3_TABLES_H 515e2f1baSYong Zhi #define __IPU3_TABLES_H 615e2f1baSYong Zhi 715e2f1baSYong Zhi #include "ipu3-abi.h" 815e2f1baSYong Zhi 915e2f1baSYong Zhi #define IMGU_BDS_GRANULARITY 32 /* Downscaling granularity */ 1015e2f1baSYong Zhi #define IMGU_BDS_MIN_SF_INV IMGU_BDS_GRANULARITY 1115e2f1baSYong Zhi #define IMGU_BDS_CONFIG_LEN 97 1215e2f1baSYong Zhi 1315e2f1baSYong Zhi #define IMGU_SCALER_DOWNSCALE_4TAPS_LEN 128 1415e2f1baSYong Zhi #define IMGU_SCALER_DOWNSCALE_2TAPS_LEN 64 1515e2f1baSYong Zhi #define IMGU_SCALER_FP ((u32)1 << 31) /* 1.0 in fixed point */ 1615e2f1baSYong Zhi 1715e2f1baSYong Zhi #define IMGU_XNR3_VMEM_LUT_LEN 16 1815e2f1baSYong Zhi 1915e2f1baSYong Zhi #define IMGU_GDC_LUT_UNIT 4 2015e2f1baSYong Zhi #define IMGU_GDC_LUT_LEN 256 2115e2f1baSYong Zhi 2215e2f1baSYong Zhi struct ipu3_css_bds_config { 2315e2f1baSYong Zhi struct imgu_abi_bds_phase_arr hor_phase_arr; 2415e2f1baSYong Zhi struct imgu_abi_bds_phase_arr ver_phase_arr; 2515e2f1baSYong Zhi struct imgu_abi_bds_ptrn_arr ptrn_arr; 2615e2f1baSYong Zhi u16 sample_patrn_length; 2715e2f1baSYong Zhi u8 hor_ds_en; 2815e2f1baSYong Zhi u8 ver_ds_en; 2915e2f1baSYong Zhi }; 3015e2f1baSYong Zhi 3115e2f1baSYong Zhi struct ipu3_css_xnr3_vmem_defaults { 3215e2f1baSYong Zhi s16 x[IMGU_XNR3_VMEM_LUT_LEN]; 3315e2f1baSYong Zhi s16 a[IMGU_XNR3_VMEM_LUT_LEN]; 3415e2f1baSYong Zhi s16 b[IMGU_XNR3_VMEM_LUT_LEN]; 3515e2f1baSYong Zhi s16 c[IMGU_XNR3_VMEM_LUT_LEN]; 3615e2f1baSYong Zhi }; 3715e2f1baSYong Zhi 3815e2f1baSYong Zhi extern const struct ipu3_css_bds_config 3915e2f1baSYong Zhi ipu3_css_bds_configs[IMGU_BDS_CONFIG_LEN]; 4015e2f1baSYong Zhi extern const s32 ipu3_css_downscale_4taps[IMGU_SCALER_DOWNSCALE_4TAPS_LEN]; 4115e2f1baSYong Zhi extern const s32 ipu3_css_downscale_2taps[IMGU_SCALER_DOWNSCALE_2TAPS_LEN]; 4215e2f1baSYong Zhi extern const s16 ipu3_css_gdc_lut[IMGU_GDC_LUT_UNIT][IMGU_GDC_LUT_LEN]; 4315e2f1baSYong Zhi extern const struct ipu3_css_xnr3_vmem_defaults ipu3_css_xnr3_vmem_defaults; 4415e2f1baSYong Zhi extern const struct ipu3_uapi_bnr_static_config ipu3_css_bnr_defaults; 4515e2f1baSYong Zhi extern const struct ipu3_uapi_dm_config ipu3_css_dm_defaults; 4615e2f1baSYong Zhi extern const struct ipu3_uapi_ccm_mat_config ipu3_css_ccm_defaults; 4715e2f1baSYong Zhi extern const struct ipu3_uapi_gamma_corr_lut ipu3_css_gamma_lut; 4815e2f1baSYong Zhi extern const struct ipu3_uapi_csc_mat_config ipu3_css_csc_defaults; 4915e2f1baSYong Zhi extern const struct ipu3_uapi_cds_params ipu3_css_cds_defaults; 5015e2f1baSYong Zhi extern const struct ipu3_uapi_shd_config_static ipu3_css_shd_defaults; 5115e2f1baSYong Zhi extern const struct ipu3_uapi_yuvp1_iefd_config ipu3_css_iefd_defaults; 5215e2f1baSYong Zhi extern const struct ipu3_uapi_yuvp1_yds_config ipu3_css_yds_defaults; 5315e2f1baSYong Zhi extern const struct ipu3_uapi_yuvp1_chnr_config ipu3_css_chnr_defaults; 5415e2f1baSYong Zhi extern const struct ipu3_uapi_yuvp1_y_ee_nr_config ipu3_css_y_ee_nr_defaults; 5515e2f1baSYong Zhi extern const struct ipu3_uapi_yuvp2_tcc_gain_pcwl_lut_static_config 5615e2f1baSYong Zhi ipu3_css_tcc_gain_pcwl_lut; 5715e2f1baSYong Zhi extern const struct ipu3_uapi_yuvp2_tcc_r_sqr_lut_static_config 5815e2f1baSYong Zhi ipu3_css_tcc_r_sqr_lut; 5915e2f1baSYong Zhi extern const struct imgu_abi_anr_config ipu3_css_anr_defaults; 6015e2f1baSYong Zhi extern const struct ipu3_uapi_awb_fr_config_s ipu3_css_awb_fr_defaults; 6115e2f1baSYong Zhi extern const struct ipu3_uapi_ae_grid_config ipu3_css_ae_grid_defaults; 6215e2f1baSYong Zhi extern const struct ipu3_uapi_ae_ccm ipu3_css_ae_ccm_defaults; 6315e2f1baSYong Zhi extern const struct ipu3_uapi_af_config_s ipu3_css_af_defaults; 6415e2f1baSYong Zhi extern const struct ipu3_uapi_awb_config_s ipu3_css_awb_defaults; 6515e2f1baSYong Zhi 6615e2f1baSYong Zhi #endif 67