1*989cf18eSMauro Carvalho Chehab // SPDX-License-Identifier: GPL-2.0-or-later
2*989cf18eSMauro Carvalho Chehab /*
3*989cf18eSMauro Carvalho Chehab  * budget-patch.c: driver for Budget Patch,
4*989cf18eSMauro Carvalho Chehab  * hardware modification of DVB-S cards enabling full TS
5*989cf18eSMauro Carvalho Chehab  *
6*989cf18eSMauro Carvalho Chehab  * Written by Emard <emard@softhome.net>
7*989cf18eSMauro Carvalho Chehab  *
8*989cf18eSMauro Carvalho Chehab  * Original idea by Roberto Deza <rdeza@unav.es>
9*989cf18eSMauro Carvalho Chehab  *
10*989cf18eSMauro Carvalho Chehab  * Special thanks to Holger Waechtler, Michael Hunold, Marian Durkovic
11*989cf18eSMauro Carvalho Chehab  * and Metzlerbros
12*989cf18eSMauro Carvalho Chehab  *
13*989cf18eSMauro Carvalho Chehab  * the project's page is at https://linuxtv.org
14*989cf18eSMauro Carvalho Chehab  */
15*989cf18eSMauro Carvalho Chehab 
16*989cf18eSMauro Carvalho Chehab #include "av7110.h"
17*989cf18eSMauro Carvalho Chehab #include "av7110_hw.h"
18*989cf18eSMauro Carvalho Chehab #include "budget.h"
19*989cf18eSMauro Carvalho Chehab #include "stv0299.h"
20*989cf18eSMauro Carvalho Chehab #include "ves1x93.h"
21*989cf18eSMauro Carvalho Chehab #include "tda8083.h"
22*989cf18eSMauro Carvalho Chehab 
23*989cf18eSMauro Carvalho Chehab #include "bsru6.h"
24*989cf18eSMauro Carvalho Chehab 
25*989cf18eSMauro Carvalho Chehab DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
26*989cf18eSMauro Carvalho Chehab 
27*989cf18eSMauro Carvalho Chehab #define budget_patch budget
28*989cf18eSMauro Carvalho Chehab 
29*989cf18eSMauro Carvalho Chehab static struct saa7146_extension budget_extension;
30*989cf18eSMauro Carvalho Chehab 
31*989cf18eSMauro Carvalho Chehab MAKE_BUDGET_INFO(ttbp, "TT-Budget/Patch DVB-S 1.x PCI", BUDGET_PATCH);
32*989cf18eSMauro Carvalho Chehab //MAKE_BUDGET_INFO(satel,"TT-Budget/Patch SATELCO PCI", BUDGET_TT_HW_DISEQC);
33*989cf18eSMauro Carvalho Chehab 
34*989cf18eSMauro Carvalho Chehab static const struct pci_device_id pci_tbl[] = {
35*989cf18eSMauro Carvalho Chehab 	MAKE_EXTENSION_PCI(ttbp,0x13c2, 0x0000),
36*989cf18eSMauro Carvalho Chehab //        MAKE_EXTENSION_PCI(satel, 0x13c2, 0x1013),
37*989cf18eSMauro Carvalho Chehab 	{
38*989cf18eSMauro Carvalho Chehab 		.vendor    = 0,
39*989cf18eSMauro Carvalho Chehab 	}
40*989cf18eSMauro Carvalho Chehab };
41*989cf18eSMauro Carvalho Chehab 
42*989cf18eSMauro Carvalho Chehab /* those lines are for budget-patch to be tried
43*989cf18eSMauro Carvalho Chehab ** on a true budget card and observe the
44*989cf18eSMauro Carvalho Chehab ** behaviour of VSYNC generated by rps1.
45*989cf18eSMauro Carvalho Chehab ** this code was shamelessly copy/pasted from budget.c
46*989cf18eSMauro Carvalho Chehab */
gpio_Set22K(struct budget * budget,int state)47*989cf18eSMauro Carvalho Chehab static void gpio_Set22K (struct budget *budget, int state)
48*989cf18eSMauro Carvalho Chehab {
49*989cf18eSMauro Carvalho Chehab 	struct saa7146_dev *dev=budget->dev;
50*989cf18eSMauro Carvalho Chehab 	dprintk(2, "budget: %p\n", budget);
51*989cf18eSMauro Carvalho Chehab 	saa7146_setgpio(dev, 3, (state ? SAA7146_GPIO_OUTHI : SAA7146_GPIO_OUTLO));
52*989cf18eSMauro Carvalho Chehab }
53*989cf18eSMauro Carvalho Chehab 
54*989cf18eSMauro Carvalho Chehab /* Diseqc functions only for TT Budget card */
55*989cf18eSMauro Carvalho Chehab /* taken from the Skyvision DVB driver by
56*989cf18eSMauro Carvalho Chehab    Ralph Metzler <rjkm@metzlerbros.de> */
57*989cf18eSMauro Carvalho Chehab 
DiseqcSendBit(struct budget * budget,int data)58*989cf18eSMauro Carvalho Chehab static void DiseqcSendBit (struct budget *budget, int data)
59*989cf18eSMauro Carvalho Chehab {
60*989cf18eSMauro Carvalho Chehab 	struct saa7146_dev *dev=budget->dev;
61*989cf18eSMauro Carvalho Chehab 	dprintk(2, "budget: %p\n", budget);
62*989cf18eSMauro Carvalho Chehab 
63*989cf18eSMauro Carvalho Chehab 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI);
64*989cf18eSMauro Carvalho Chehab 	udelay(data ? 500 : 1000);
65*989cf18eSMauro Carvalho Chehab 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);
66*989cf18eSMauro Carvalho Chehab 	udelay(data ? 1000 : 500);
67*989cf18eSMauro Carvalho Chehab }
68*989cf18eSMauro Carvalho Chehab 
DiseqcSendByte(struct budget * budget,int data)69*989cf18eSMauro Carvalho Chehab static void DiseqcSendByte (struct budget *budget, int data)
70*989cf18eSMauro Carvalho Chehab {
71*989cf18eSMauro Carvalho Chehab 	int i, par=1, d;
72*989cf18eSMauro Carvalho Chehab 
73*989cf18eSMauro Carvalho Chehab 	dprintk(2, "budget: %p\n", budget);
74*989cf18eSMauro Carvalho Chehab 
75*989cf18eSMauro Carvalho Chehab 	for (i=7; i>=0; i--) {
76*989cf18eSMauro Carvalho Chehab 		d = (data>>i)&1;
77*989cf18eSMauro Carvalho Chehab 		par ^= d;
78*989cf18eSMauro Carvalho Chehab 		DiseqcSendBit(budget, d);
79*989cf18eSMauro Carvalho Chehab 	}
80*989cf18eSMauro Carvalho Chehab 
81*989cf18eSMauro Carvalho Chehab 	DiseqcSendBit(budget, par);
82*989cf18eSMauro Carvalho Chehab }
83*989cf18eSMauro Carvalho Chehab 
SendDiSEqCMsg(struct budget * budget,int len,u8 * msg,unsigned long burst)84*989cf18eSMauro Carvalho Chehab static int SendDiSEqCMsg (struct budget *budget, int len, u8 *msg, unsigned long burst)
85*989cf18eSMauro Carvalho Chehab {
86*989cf18eSMauro Carvalho Chehab 	struct saa7146_dev *dev=budget->dev;
87*989cf18eSMauro Carvalho Chehab 	int i;
88*989cf18eSMauro Carvalho Chehab 
89*989cf18eSMauro Carvalho Chehab 	dprintk(2, "budget: %p\n", budget);
90*989cf18eSMauro Carvalho Chehab 
91*989cf18eSMauro Carvalho Chehab 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);
92*989cf18eSMauro Carvalho Chehab 	mdelay(16);
93*989cf18eSMauro Carvalho Chehab 
94*989cf18eSMauro Carvalho Chehab 	for (i=0; i<len; i++)
95*989cf18eSMauro Carvalho Chehab 		DiseqcSendByte(budget, msg[i]);
96*989cf18eSMauro Carvalho Chehab 
97*989cf18eSMauro Carvalho Chehab 	mdelay(16);
98*989cf18eSMauro Carvalho Chehab 
99*989cf18eSMauro Carvalho Chehab 	if (burst!=-1) {
100*989cf18eSMauro Carvalho Chehab 		if (burst)
101*989cf18eSMauro Carvalho Chehab 			DiseqcSendByte(budget, 0xff);
102*989cf18eSMauro Carvalho Chehab 		else {
103*989cf18eSMauro Carvalho Chehab 			saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI);
104*989cf18eSMauro Carvalho Chehab 			mdelay(12);
105*989cf18eSMauro Carvalho Chehab 			udelay(500);
106*989cf18eSMauro Carvalho Chehab 			saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);
107*989cf18eSMauro Carvalho Chehab 		}
108*989cf18eSMauro Carvalho Chehab 		msleep(20);
109*989cf18eSMauro Carvalho Chehab 	}
110*989cf18eSMauro Carvalho Chehab 
111*989cf18eSMauro Carvalho Chehab 	return 0;
112*989cf18eSMauro Carvalho Chehab }
113*989cf18eSMauro Carvalho Chehab 
114*989cf18eSMauro Carvalho Chehab /* shamelessly copy/pasted from budget.c */
budget_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)115*989cf18eSMauro Carvalho Chehab static int budget_set_tone(struct dvb_frontend *fe,
116*989cf18eSMauro Carvalho Chehab 			   enum fe_sec_tone_mode tone)
117*989cf18eSMauro Carvalho Chehab {
118*989cf18eSMauro Carvalho Chehab 	struct budget* budget = (struct budget*) fe->dvb->priv;
119*989cf18eSMauro Carvalho Chehab 
120*989cf18eSMauro Carvalho Chehab 	switch (tone) {
121*989cf18eSMauro Carvalho Chehab 	case SEC_TONE_ON:
122*989cf18eSMauro Carvalho Chehab 		gpio_Set22K (budget, 1);
123*989cf18eSMauro Carvalho Chehab 		break;
124*989cf18eSMauro Carvalho Chehab 
125*989cf18eSMauro Carvalho Chehab 	case SEC_TONE_OFF:
126*989cf18eSMauro Carvalho Chehab 		gpio_Set22K (budget, 0);
127*989cf18eSMauro Carvalho Chehab 		break;
128*989cf18eSMauro Carvalho Chehab 
129*989cf18eSMauro Carvalho Chehab 	default:
130*989cf18eSMauro Carvalho Chehab 		return -EINVAL;
131*989cf18eSMauro Carvalho Chehab 	}
132*989cf18eSMauro Carvalho Chehab 
133*989cf18eSMauro Carvalho Chehab 	return 0;
134*989cf18eSMauro Carvalho Chehab }
135*989cf18eSMauro Carvalho Chehab 
budget_diseqc_send_master_cmd(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)136*989cf18eSMauro Carvalho Chehab static int budget_diseqc_send_master_cmd(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd)
137*989cf18eSMauro Carvalho Chehab {
138*989cf18eSMauro Carvalho Chehab 	struct budget* budget = (struct budget*) fe->dvb->priv;
139*989cf18eSMauro Carvalho Chehab 
140*989cf18eSMauro Carvalho Chehab 	SendDiSEqCMsg (budget, cmd->msg_len, cmd->msg, 0);
141*989cf18eSMauro Carvalho Chehab 
142*989cf18eSMauro Carvalho Chehab 	return 0;
143*989cf18eSMauro Carvalho Chehab }
144*989cf18eSMauro Carvalho Chehab 
budget_diseqc_send_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd minicmd)145*989cf18eSMauro Carvalho Chehab static int budget_diseqc_send_burst(struct dvb_frontend *fe,
146*989cf18eSMauro Carvalho Chehab 				    enum fe_sec_mini_cmd minicmd)
147*989cf18eSMauro Carvalho Chehab {
148*989cf18eSMauro Carvalho Chehab 	struct budget* budget = (struct budget*) fe->dvb->priv;
149*989cf18eSMauro Carvalho Chehab 
150*989cf18eSMauro Carvalho Chehab 	SendDiSEqCMsg (budget, 0, NULL, minicmd);
151*989cf18eSMauro Carvalho Chehab 
152*989cf18eSMauro Carvalho Chehab 	return 0;
153*989cf18eSMauro Carvalho Chehab }
154*989cf18eSMauro Carvalho Chehab 
budget_av7110_send_fw_cmd(struct budget_patch * budget,u16 * buf,int length)155*989cf18eSMauro Carvalho Chehab static int budget_av7110_send_fw_cmd(struct budget_patch *budget, u16* buf, int length)
156*989cf18eSMauro Carvalho Chehab {
157*989cf18eSMauro Carvalho Chehab 	int i;
158*989cf18eSMauro Carvalho Chehab 
159*989cf18eSMauro Carvalho Chehab 	dprintk(2, "budget: %p\n", budget);
160*989cf18eSMauro Carvalho Chehab 
161*989cf18eSMauro Carvalho Chehab 	for (i = 2; i < length; i++)
162*989cf18eSMauro Carvalho Chehab 	{
163*989cf18eSMauro Carvalho Chehab 		  ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND + 2*i, 2, (u32) buf[i], 0,0);
164*989cf18eSMauro Carvalho Chehab 		  msleep(5);
165*989cf18eSMauro Carvalho Chehab 	}
166*989cf18eSMauro Carvalho Chehab 	if (length)
167*989cf18eSMauro Carvalho Chehab 		  ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND + 2, 2, (u32) buf[1], 0,0);
168*989cf18eSMauro Carvalho Chehab 	else
169*989cf18eSMauro Carvalho Chehab 		  ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND + 2, 2, 0, 0,0);
170*989cf18eSMauro Carvalho Chehab 	msleep(5);
171*989cf18eSMauro Carvalho Chehab 	ttpci_budget_debiwrite(budget, DEBINOSWAP, COMMAND, 2, (u32) buf[0], 0,0);
172*989cf18eSMauro Carvalho Chehab 	msleep(5);
173*989cf18eSMauro Carvalho Chehab 	return 0;
174*989cf18eSMauro Carvalho Chehab }
175*989cf18eSMauro Carvalho Chehab 
av7110_set22k(struct budget_patch * budget,int state)176*989cf18eSMauro Carvalho Chehab static void av7110_set22k(struct budget_patch *budget, int state)
177*989cf18eSMauro Carvalho Chehab {
178*989cf18eSMauro Carvalho Chehab 	u16 buf[2] = {( COMTYPE_AUDIODAC << 8) | (state ? ON22K : OFF22K), 0};
179*989cf18eSMauro Carvalho Chehab 
180*989cf18eSMauro Carvalho Chehab 	dprintk(2, "budget: %p\n", budget);
181*989cf18eSMauro Carvalho Chehab 	budget_av7110_send_fw_cmd(budget, buf, 2);
182*989cf18eSMauro Carvalho Chehab }
183*989cf18eSMauro Carvalho Chehab 
av7110_send_diseqc_msg(struct budget_patch * budget,int len,u8 * msg,int burst)184*989cf18eSMauro Carvalho Chehab static int av7110_send_diseqc_msg(struct budget_patch *budget, int len, u8 *msg, int burst)
185*989cf18eSMauro Carvalho Chehab {
186*989cf18eSMauro Carvalho Chehab 	int i;
187*989cf18eSMauro Carvalho Chehab 	u16 buf[18] = { ((COMTYPE_AUDIODAC << 8) | SendDiSEqC),
188*989cf18eSMauro Carvalho Chehab 		16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
189*989cf18eSMauro Carvalho Chehab 
190*989cf18eSMauro Carvalho Chehab 	dprintk(2, "budget: %p\n", budget);
191*989cf18eSMauro Carvalho Chehab 
192*989cf18eSMauro Carvalho Chehab 	if (len>10)
193*989cf18eSMauro Carvalho Chehab 		len=10;
194*989cf18eSMauro Carvalho Chehab 
195*989cf18eSMauro Carvalho Chehab 	buf[1] = len+2;
196*989cf18eSMauro Carvalho Chehab 	buf[2] = len;
197*989cf18eSMauro Carvalho Chehab 
198*989cf18eSMauro Carvalho Chehab 	if (burst != -1)
199*989cf18eSMauro Carvalho Chehab 		buf[3]=burst ? 0x01 : 0x00;
200*989cf18eSMauro Carvalho Chehab 	else
201*989cf18eSMauro Carvalho Chehab 		buf[3]=0xffff;
202*989cf18eSMauro Carvalho Chehab 
203*989cf18eSMauro Carvalho Chehab 	for (i=0; i<len; i++)
204*989cf18eSMauro Carvalho Chehab 		buf[i+4]=msg[i];
205*989cf18eSMauro Carvalho Chehab 
206*989cf18eSMauro Carvalho Chehab 	budget_av7110_send_fw_cmd(budget, buf, 18);
207*989cf18eSMauro Carvalho Chehab 	return 0;
208*989cf18eSMauro Carvalho Chehab }
209*989cf18eSMauro Carvalho Chehab 
budget_patch_set_tone(struct dvb_frontend * fe,enum fe_sec_tone_mode tone)210*989cf18eSMauro Carvalho Chehab static int budget_patch_set_tone(struct dvb_frontend *fe,
211*989cf18eSMauro Carvalho Chehab 				 enum fe_sec_tone_mode tone)
212*989cf18eSMauro Carvalho Chehab {
213*989cf18eSMauro Carvalho Chehab 	struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
214*989cf18eSMauro Carvalho Chehab 
215*989cf18eSMauro Carvalho Chehab 	switch (tone) {
216*989cf18eSMauro Carvalho Chehab 	case SEC_TONE_ON:
217*989cf18eSMauro Carvalho Chehab 		av7110_set22k (budget, 1);
218*989cf18eSMauro Carvalho Chehab 		break;
219*989cf18eSMauro Carvalho Chehab 
220*989cf18eSMauro Carvalho Chehab 	case SEC_TONE_OFF:
221*989cf18eSMauro Carvalho Chehab 		av7110_set22k (budget, 0);
222*989cf18eSMauro Carvalho Chehab 		break;
223*989cf18eSMauro Carvalho Chehab 
224*989cf18eSMauro Carvalho Chehab 	default:
225*989cf18eSMauro Carvalho Chehab 		return -EINVAL;
226*989cf18eSMauro Carvalho Chehab 	}
227*989cf18eSMauro Carvalho Chehab 
228*989cf18eSMauro Carvalho Chehab 	return 0;
229*989cf18eSMauro Carvalho Chehab }
230*989cf18eSMauro Carvalho Chehab 
budget_patch_diseqc_send_master_cmd(struct dvb_frontend * fe,struct dvb_diseqc_master_cmd * cmd)231*989cf18eSMauro Carvalho Chehab static int budget_patch_diseqc_send_master_cmd(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd* cmd)
232*989cf18eSMauro Carvalho Chehab {
233*989cf18eSMauro Carvalho Chehab 	struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
234*989cf18eSMauro Carvalho Chehab 
235*989cf18eSMauro Carvalho Chehab 	av7110_send_diseqc_msg (budget, cmd->msg_len, cmd->msg, 0);
236*989cf18eSMauro Carvalho Chehab 
237*989cf18eSMauro Carvalho Chehab 	return 0;
238*989cf18eSMauro Carvalho Chehab }
239*989cf18eSMauro Carvalho Chehab 
budget_patch_diseqc_send_burst(struct dvb_frontend * fe,enum fe_sec_mini_cmd minicmd)240*989cf18eSMauro Carvalho Chehab static int budget_patch_diseqc_send_burst(struct dvb_frontend *fe,
241*989cf18eSMauro Carvalho Chehab 					  enum fe_sec_mini_cmd minicmd)
242*989cf18eSMauro Carvalho Chehab {
243*989cf18eSMauro Carvalho Chehab 	struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
244*989cf18eSMauro Carvalho Chehab 
245*989cf18eSMauro Carvalho Chehab 	av7110_send_diseqc_msg (budget, 0, NULL, minicmd);
246*989cf18eSMauro Carvalho Chehab 
247*989cf18eSMauro Carvalho Chehab 	return 0;
248*989cf18eSMauro Carvalho Chehab }
249*989cf18eSMauro Carvalho Chehab 
alps_bsrv2_tuner_set_params(struct dvb_frontend * fe)250*989cf18eSMauro Carvalho Chehab static int alps_bsrv2_tuner_set_params(struct dvb_frontend *fe)
251*989cf18eSMauro Carvalho Chehab {
252*989cf18eSMauro Carvalho Chehab 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
253*989cf18eSMauro Carvalho Chehab 	struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
254*989cf18eSMauro Carvalho Chehab 	u8 pwr = 0;
255*989cf18eSMauro Carvalho Chehab 	u8 buf[4];
256*989cf18eSMauro Carvalho Chehab 	struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = buf, .len = sizeof(buf) };
257*989cf18eSMauro Carvalho Chehab 	u32 div = (p->frequency + 479500) / 125;
258*989cf18eSMauro Carvalho Chehab 
259*989cf18eSMauro Carvalho Chehab 	if (p->frequency > 2000000)
260*989cf18eSMauro Carvalho Chehab 		pwr = 3;
261*989cf18eSMauro Carvalho Chehab 	else if (p->frequency > 1800000)
262*989cf18eSMauro Carvalho Chehab 		pwr = 2;
263*989cf18eSMauro Carvalho Chehab 	else if (p->frequency > 1600000)
264*989cf18eSMauro Carvalho Chehab 		pwr = 1;
265*989cf18eSMauro Carvalho Chehab 	else if (p->frequency > 1200000)
266*989cf18eSMauro Carvalho Chehab 		pwr = 0;
267*989cf18eSMauro Carvalho Chehab 	else if (p->frequency >= 1100000)
268*989cf18eSMauro Carvalho Chehab 		pwr = 1;
269*989cf18eSMauro Carvalho Chehab 	else pwr = 2;
270*989cf18eSMauro Carvalho Chehab 
271*989cf18eSMauro Carvalho Chehab 	buf[0] = (div >> 8) & 0x7f;
272*989cf18eSMauro Carvalho Chehab 	buf[1] = div & 0xff;
273*989cf18eSMauro Carvalho Chehab 	buf[2] = ((div & 0x18000) >> 10) | 0x95;
274*989cf18eSMauro Carvalho Chehab 	buf[3] = (pwr << 6) | 0x30;
275*989cf18eSMauro Carvalho Chehab 
276*989cf18eSMauro Carvalho Chehab 	// NOTE: since we're using a prescaler of 2, we set the
277*989cf18eSMauro Carvalho Chehab 	// divisor frequency to 62.5kHz and divide by 125 above
278*989cf18eSMauro Carvalho Chehab 
279*989cf18eSMauro Carvalho Chehab 	if (fe->ops.i2c_gate_ctrl)
280*989cf18eSMauro Carvalho Chehab 		fe->ops.i2c_gate_ctrl(fe, 1);
281*989cf18eSMauro Carvalho Chehab 	if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1)
282*989cf18eSMauro Carvalho Chehab 		return -EIO;
283*989cf18eSMauro Carvalho Chehab 	return 0;
284*989cf18eSMauro Carvalho Chehab }
285*989cf18eSMauro Carvalho Chehab 
286*989cf18eSMauro Carvalho Chehab static struct ves1x93_config alps_bsrv2_config = {
287*989cf18eSMauro Carvalho Chehab 	.demod_address = 0x08,
288*989cf18eSMauro Carvalho Chehab 	.xin = 90100000UL,
289*989cf18eSMauro Carvalho Chehab 	.invert_pwm = 0,
290*989cf18eSMauro Carvalho Chehab };
291*989cf18eSMauro Carvalho Chehab 
grundig_29504_451_tuner_set_params(struct dvb_frontend * fe)292*989cf18eSMauro Carvalho Chehab static int grundig_29504_451_tuner_set_params(struct dvb_frontend *fe)
293*989cf18eSMauro Carvalho Chehab {
294*989cf18eSMauro Carvalho Chehab 	struct dtv_frontend_properties *p = &fe->dtv_property_cache;
295*989cf18eSMauro Carvalho Chehab 	struct budget_patch* budget = (struct budget_patch*) fe->dvb->priv;
296*989cf18eSMauro Carvalho Chehab 	u32 div;
297*989cf18eSMauro Carvalho Chehab 	u8 data[4];
298*989cf18eSMauro Carvalho Chehab 	struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) };
299*989cf18eSMauro Carvalho Chehab 
300*989cf18eSMauro Carvalho Chehab 	div = p->frequency / 125;
301*989cf18eSMauro Carvalho Chehab 	data[0] = (div >> 8) & 0x7f;
302*989cf18eSMauro Carvalho Chehab 	data[1] = div & 0xff;
303*989cf18eSMauro Carvalho Chehab 	data[2] = 0x8e;
304*989cf18eSMauro Carvalho Chehab 	data[3] = 0x00;
305*989cf18eSMauro Carvalho Chehab 
306*989cf18eSMauro Carvalho Chehab 	if (fe->ops.i2c_gate_ctrl)
307*989cf18eSMauro Carvalho Chehab 		fe->ops.i2c_gate_ctrl(fe, 1);
308*989cf18eSMauro Carvalho Chehab 	if (i2c_transfer (&budget->i2c_adap, &msg, 1) != 1)
309*989cf18eSMauro Carvalho Chehab 		return -EIO;
310*989cf18eSMauro Carvalho Chehab 	return 0;
311*989cf18eSMauro Carvalho Chehab }
312*989cf18eSMauro Carvalho Chehab 
313*989cf18eSMauro Carvalho Chehab static struct tda8083_config grundig_29504_451_config = {
314*989cf18eSMauro Carvalho Chehab 	.demod_address = 0x68,
315*989cf18eSMauro Carvalho Chehab };
316*989cf18eSMauro Carvalho Chehab 
frontend_init(struct budget_patch * budget)317*989cf18eSMauro Carvalho Chehab static void frontend_init(struct budget_patch* budget)
318*989cf18eSMauro Carvalho Chehab {
319*989cf18eSMauro Carvalho Chehab 	switch(budget->dev->pci->subsystem_device) {
320*989cf18eSMauro Carvalho Chehab 	case 0x0000: // Hauppauge/TT WinTV DVB-S rev1.X
321*989cf18eSMauro Carvalho Chehab 	case 0x1013: // SATELCO Multimedia PCI
322*989cf18eSMauro Carvalho Chehab 
323*989cf18eSMauro Carvalho Chehab 		// try the ALPS BSRV2 first of all
324*989cf18eSMauro Carvalho Chehab 		budget->dvb_frontend = dvb_attach(ves1x93_attach, &alps_bsrv2_config, &budget->i2c_adap);
325*989cf18eSMauro Carvalho Chehab 		if (budget->dvb_frontend) {
326*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsrv2_tuner_set_params;
327*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_patch_diseqc_send_master_cmd;
328*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.diseqc_send_burst = budget_patch_diseqc_send_burst;
329*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.set_tone = budget_patch_set_tone;
330*989cf18eSMauro Carvalho Chehab 			break;
331*989cf18eSMauro Carvalho Chehab 		}
332*989cf18eSMauro Carvalho Chehab 
333*989cf18eSMauro Carvalho Chehab 		// try the ALPS BSRU6 now
334*989cf18eSMauro Carvalho Chehab 		budget->dvb_frontend = dvb_attach(stv0299_attach, &alps_bsru6_config, &budget->i2c_adap);
335*989cf18eSMauro Carvalho Chehab 		if (budget->dvb_frontend) {
336*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params;
337*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->tuner_priv = &budget->i2c_adap;
338*989cf18eSMauro Carvalho Chehab 
339*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_diseqc_send_master_cmd;
340*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.diseqc_send_burst = budget_diseqc_send_burst;
341*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.set_tone = budget_set_tone;
342*989cf18eSMauro Carvalho Chehab 			break;
343*989cf18eSMauro Carvalho Chehab 		}
344*989cf18eSMauro Carvalho Chehab 
345*989cf18eSMauro Carvalho Chehab 		// Try the grundig 29504-451
346*989cf18eSMauro Carvalho Chehab 		budget->dvb_frontend = dvb_attach(tda8083_attach, &grundig_29504_451_config, &budget->i2c_adap);
347*989cf18eSMauro Carvalho Chehab 		if (budget->dvb_frontend) {
348*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.tuner_ops.set_params = grundig_29504_451_tuner_set_params;
349*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.diseqc_send_master_cmd = budget_diseqc_send_master_cmd;
350*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.diseqc_send_burst = budget_diseqc_send_burst;
351*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend->ops.set_tone = budget_set_tone;
352*989cf18eSMauro Carvalho Chehab 			break;
353*989cf18eSMauro Carvalho Chehab 		}
354*989cf18eSMauro Carvalho Chehab 		break;
355*989cf18eSMauro Carvalho Chehab 	}
356*989cf18eSMauro Carvalho Chehab 
357*989cf18eSMauro Carvalho Chehab 	if (budget->dvb_frontend == NULL) {
358*989cf18eSMauro Carvalho Chehab 		printk("dvb-ttpci: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n",
359*989cf18eSMauro Carvalho Chehab 		       budget->dev->pci->vendor,
360*989cf18eSMauro Carvalho Chehab 		       budget->dev->pci->device,
361*989cf18eSMauro Carvalho Chehab 		       budget->dev->pci->subsystem_vendor,
362*989cf18eSMauro Carvalho Chehab 		       budget->dev->pci->subsystem_device);
363*989cf18eSMauro Carvalho Chehab 	} else {
364*989cf18eSMauro Carvalho Chehab 		if (dvb_register_frontend(&budget->dvb_adapter, budget->dvb_frontend)) {
365*989cf18eSMauro Carvalho Chehab 			printk("budget-av: Frontend registration failed!\n");
366*989cf18eSMauro Carvalho Chehab 			dvb_frontend_detach(budget->dvb_frontend);
367*989cf18eSMauro Carvalho Chehab 			budget->dvb_frontend = NULL;
368*989cf18eSMauro Carvalho Chehab 		}
369*989cf18eSMauro Carvalho Chehab 	}
370*989cf18eSMauro Carvalho Chehab }
371*989cf18eSMauro Carvalho Chehab 
372*989cf18eSMauro Carvalho Chehab /* written by Emard */
budget_patch_attach(struct saa7146_dev * dev,struct saa7146_pci_extension_data * info)373*989cf18eSMauro Carvalho Chehab static int budget_patch_attach (struct saa7146_dev* dev, struct saa7146_pci_extension_data *info)
374*989cf18eSMauro Carvalho Chehab {
375*989cf18eSMauro Carvalho Chehab 	struct budget_patch *budget;
376*989cf18eSMauro Carvalho Chehab 	int err;
377*989cf18eSMauro Carvalho Chehab 	int count = 0;
378*989cf18eSMauro Carvalho Chehab 	int detected = 0;
379*989cf18eSMauro Carvalho Chehab 
380*989cf18eSMauro Carvalho Chehab #define PATCH_RESET 0
381*989cf18eSMauro Carvalho Chehab #define RPS_IRQ 0
382*989cf18eSMauro Carvalho Chehab #define HPS_SETUP 0
383*989cf18eSMauro Carvalho Chehab #if PATCH_RESET
384*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, MC1, MASK_31);
385*989cf18eSMauro Carvalho Chehab 	msleep(40);
386*989cf18eSMauro Carvalho Chehab #endif
387*989cf18eSMauro Carvalho Chehab #if HPS_SETUP
388*989cf18eSMauro Carvalho Chehab 	// initialize registers. Better to have it like this
389*989cf18eSMauro Carvalho Chehab 	// than leaving something unconfigured
390*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, DD1_STREAM_B, 0);
391*989cf18eSMauro Carvalho Chehab 	// port B VSYNC at rising edge
392*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, DD1_INIT, 0x00000200);  // have this in budget-core too!
393*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, BRS_CTRL, 0x00000000);  // VBI
394*989cf18eSMauro Carvalho Chehab 
395*989cf18eSMauro Carvalho Chehab 	// debi config
396*989cf18eSMauro Carvalho Chehab 	// saa7146_write(dev, DEBI_CONFIG, MASK_30|MASK_28|MASK_18);
397*989cf18eSMauro Carvalho Chehab 
398*989cf18eSMauro Carvalho Chehab 	// zero all HPS registers
399*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, HPS_H_PRESCALE, 0);                  // r68
400*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, HPS_H_SCALE, 0);                     // r6c
401*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, BCS_CTRL, 0);                        // r70
402*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, HPS_V_SCALE, 0);                     // r60
403*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, HPS_V_GAIN, 0);                      // r64
404*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, CHROMA_KEY_RANGE, 0);                // r74
405*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, CLIP_FORMAT_CTRL, 0);                // r78
406*989cf18eSMauro Carvalho Chehab 	// Set HPS prescaler for port B input
407*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, HPS_CTRL, (1<<30) | (0<<29) | (1<<28) | (0<<12) );
408*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, MC2,
409*989cf18eSMauro Carvalho Chehab 	  0 * (MASK_08 | MASK_24)  |   // BRS control
410*989cf18eSMauro Carvalho Chehab 	  0 * (MASK_09 | MASK_25)  |   // a
411*989cf18eSMauro Carvalho Chehab 	  0 * (MASK_10 | MASK_26)  |   // b
412*989cf18eSMauro Carvalho Chehab 	  1 * (MASK_06 | MASK_22)  |   // HPS_CTRL1
413*989cf18eSMauro Carvalho Chehab 	  1 * (MASK_05 | MASK_21)  |   // HPS_CTRL2
414*989cf18eSMauro Carvalho Chehab 	  0 * (MASK_01 | MASK_15)      // DEBI
415*989cf18eSMauro Carvalho Chehab 	   );
416*989cf18eSMauro Carvalho Chehab #endif
417*989cf18eSMauro Carvalho Chehab 	// Disable RPS1 and RPS0
418*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, MC1, ( MASK_29 | MASK_28));
419*989cf18eSMauro Carvalho Chehab 	// RPS1 timeout disable
420*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, RPS_TOV1, 0);
421*989cf18eSMauro Carvalho Chehab 
422*989cf18eSMauro Carvalho Chehab 	// code for autodetection
423*989cf18eSMauro Carvalho Chehab 	// will wait for VBI_B event (vertical blank at port B)
424*989cf18eSMauro Carvalho Chehab 	// and will reset GPIO3 after VBI_B is detected.
425*989cf18eSMauro Carvalho Chehab 	// (GPIO3 should be raised high by CPU to
426*989cf18eSMauro Carvalho Chehab 	// test if GPIO3 will generate vertical blank signal
427*989cf18eSMauro Carvalho Chehab 	// in budget patch GPIO3 is connected to VSYNC_B
428*989cf18eSMauro Carvalho Chehab 	count = 0;
429*989cf18eSMauro Carvalho Chehab #if 0
430*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_UPLOAD |
431*989cf18eSMauro Carvalho Chehab 	  MASK_10 | MASK_09 | MASK_08 | MASK_06 | MASK_05 | MASK_04 | MASK_03 | MASK_02 );
432*989cf18eSMauro Carvalho Chehab #endif
433*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_PAUSE | EVT_VBI_B);
434*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2));
435*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(GPIO3_MSK);
436*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(SAA7146_GPIO_OUTLO<<24);
437*989cf18eSMauro Carvalho Chehab #if RPS_IRQ
438*989cf18eSMauro Carvalho Chehab 	// issue RPS1 interrupt to increment counter
439*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_INTERRUPT);
440*989cf18eSMauro Carvalho Chehab 	// at least a NOP is neede between two interrupts
441*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_NOP);
442*989cf18eSMauro Carvalho Chehab 	// interrupt again
443*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_INTERRUPT);
444*989cf18eSMauro Carvalho Chehab #endif
445*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_STOP);
446*989cf18eSMauro Carvalho Chehab 
447*989cf18eSMauro Carvalho Chehab #if RPS_IRQ
448*989cf18eSMauro Carvalho Chehab 	// set event counter 1 source as RPS1 interrupt (0x03)          (rE4 p53)
449*989cf18eSMauro Carvalho Chehab 	// use 0x03 to track RPS1 interrupts - increase by 1 every gpio3 is toggled
450*989cf18eSMauro Carvalho Chehab 	// use 0x15 to track VPE  interrupts - increase by 1 every vpeirq() is called
451*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, EC1SSR, (0x03<<2) | 3 );
452*989cf18eSMauro Carvalho Chehab 	// set event counter 1 threshold to maximum allowed value        (rEC p55)
453*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, ECT1R,  0x3fff );
454*989cf18eSMauro Carvalho Chehab #endif
455*989cf18eSMauro Carvalho Chehab 	// Fix VSYNC level
456*989cf18eSMauro Carvalho Chehab 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);
457*989cf18eSMauro Carvalho Chehab 	// Set RPS1 Address register to point to RPS code               (r108 p42)
458*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
459*989cf18eSMauro Carvalho Chehab 	// Enable RPS1,                                                 (rFC p33)
460*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, MC1, (MASK_13 | MASK_29 ));
461*989cf18eSMauro Carvalho Chehab 
462*989cf18eSMauro Carvalho Chehab 
463*989cf18eSMauro Carvalho Chehab 	mdelay(50);
464*989cf18eSMauro Carvalho Chehab 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTHI);
465*989cf18eSMauro Carvalho Chehab 	mdelay(150);
466*989cf18eSMauro Carvalho Chehab 
467*989cf18eSMauro Carvalho Chehab 
468*989cf18eSMauro Carvalho Chehab 	if( (saa7146_read(dev, GPIO_CTRL) & 0x10000000) == 0)
469*989cf18eSMauro Carvalho Chehab 		detected = 1;
470*989cf18eSMauro Carvalho Chehab 
471*989cf18eSMauro Carvalho Chehab #if RPS_IRQ
472*989cf18eSMauro Carvalho Chehab 	printk("Event Counter 1 0x%04x\n", saa7146_read(dev, EC1R) & 0x3fff );
473*989cf18eSMauro Carvalho Chehab #endif
474*989cf18eSMauro Carvalho Chehab 	// Disable RPS1
475*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, MC1, ( MASK_29 ));
476*989cf18eSMauro Carvalho Chehab 
477*989cf18eSMauro Carvalho Chehab 	if(detected == 0)
478*989cf18eSMauro Carvalho Chehab 		printk("budget-patch not detected or saa7146 in non-default state.\n"
479*989cf18eSMauro Carvalho Chehab 		       "try enabling resetting of 7146 with MASK_31 in MC1 register\n");
480*989cf18eSMauro Carvalho Chehab 
481*989cf18eSMauro Carvalho Chehab 	else
482*989cf18eSMauro Carvalho Chehab 		printk("BUDGET-PATCH DETECTED.\n");
483*989cf18eSMauro Carvalho Chehab 
484*989cf18eSMauro Carvalho Chehab 
485*989cf18eSMauro Carvalho Chehab /*      OLD (Original design by Roberto Deza):
486*989cf18eSMauro Carvalho Chehab **      This code will setup the SAA7146_RPS1 to generate a square
487*989cf18eSMauro Carvalho Chehab **      wave on GPIO3, changing when a field (TS_HEIGHT/2 "lines" of
488*989cf18eSMauro Carvalho Chehab **      TS_WIDTH packets) has been acquired on SAA7146_D1B video port;
489*989cf18eSMauro Carvalho Chehab **      then, this GPIO3 output which is connected to the D1B_VSYNC
490*989cf18eSMauro Carvalho Chehab **      input, will trigger the acquisition of the alternate field
491*989cf18eSMauro Carvalho Chehab **      and so on.
492*989cf18eSMauro Carvalho Chehab **      Currently, the TT_budget / WinTV_Nova cards have two ICs
493*989cf18eSMauro Carvalho Chehab **      (74HCT4040, LVC74) for the generation of this VSYNC signal,
494*989cf18eSMauro Carvalho Chehab **      which seems that can be done perfectly without this :-)).
495*989cf18eSMauro Carvalho Chehab */
496*989cf18eSMauro Carvalho Chehab 
497*989cf18eSMauro Carvalho Chehab /*      New design (By Emard)
498*989cf18eSMauro Carvalho Chehab **      this rps1 code will copy internal HS event to GPIO3 pin.
499*989cf18eSMauro Carvalho Chehab **      GPIO3 is in budget-patch hardware connected to port B VSYNC
500*989cf18eSMauro Carvalho Chehab 
501*989cf18eSMauro Carvalho Chehab **      HS is an internal event of 7146, accessible with RPS
502*989cf18eSMauro Carvalho Chehab **      and temporarily raised high every n lines
503*989cf18eSMauro Carvalho Chehab **      (n in defined in the RPS_THRESH1 counter threshold)
504*989cf18eSMauro Carvalho Chehab **      I think HS is raised high on the beginning of the n-th line
505*989cf18eSMauro Carvalho Chehab **      and remains high until this n-th line that triggered
506*989cf18eSMauro Carvalho Chehab **      it is completely received. When the reception of n-th line
507*989cf18eSMauro Carvalho Chehab **      ends, HS is lowered.
508*989cf18eSMauro Carvalho Chehab 
509*989cf18eSMauro Carvalho Chehab **      To transmit data over DMA, 7146 needs changing state at
510*989cf18eSMauro Carvalho Chehab **      port B VSYNC pin. Any changing of port B VSYNC will
511*989cf18eSMauro Carvalho Chehab **      cause some DMA data transfer, with more or less packets loss.
512*989cf18eSMauro Carvalho Chehab **      It depends on the phase and frequency of VSYNC and
513*989cf18eSMauro Carvalho Chehab **      the way of 7146 is instructed to trigger on port B (defined
514*989cf18eSMauro Carvalho Chehab **      in DD1_INIT register, 3rd nibble from the right valid
515*989cf18eSMauro Carvalho Chehab **      numbers are 0-7, see datasheet)
516*989cf18eSMauro Carvalho Chehab **
517*989cf18eSMauro Carvalho Chehab **      The correct triggering can minimize packet loss,
518*989cf18eSMauro Carvalho Chehab **      dvbtraffic should give this stable bandwidths:
519*989cf18eSMauro Carvalho Chehab **        22k transponder = 33814 kbit/s
520*989cf18eSMauro Carvalho Chehab **      27.5k transponder = 38045 kbit/s
521*989cf18eSMauro Carvalho Chehab **      by experiment it is found that the best results
522*989cf18eSMauro Carvalho Chehab **      (stable bandwidths and almost no packet loss)
523*989cf18eSMauro Carvalho Chehab **      are obtained using DD1_INIT triggering number 2
524*989cf18eSMauro Carvalho Chehab **      (Va at rising edge of VS Fa = HS x VS-failing forced toggle)
525*989cf18eSMauro Carvalho Chehab **      and a VSYNC phase that occurs in the middle of DMA transfer
526*989cf18eSMauro Carvalho Chehab **      (about byte 188*512=96256 in the DMA window).
527*989cf18eSMauro Carvalho Chehab **
528*989cf18eSMauro Carvalho Chehab **      Phase of HS is still not clear to me how to control,
529*989cf18eSMauro Carvalho Chehab **      It just happens to be so. It can be seen if one enables
530*989cf18eSMauro Carvalho Chehab **      RPS_IRQ and print Event Counter 1 in vpeirq(). Every
531*989cf18eSMauro Carvalho Chehab **      time RPS_INTERRUPT is called, the Event Counter 1 will
532*989cf18eSMauro Carvalho Chehab **      increment. That's how the 7146 is programmed to do event
533*989cf18eSMauro Carvalho Chehab **      counting in this budget-patch.c
534*989cf18eSMauro Carvalho Chehab **      I *think* HPS setting has something to do with the phase
535*989cf18eSMauro Carvalho Chehab **      of HS but I can't be 100% sure in that.
536*989cf18eSMauro Carvalho Chehab 
537*989cf18eSMauro Carvalho Chehab **      hardware debug note: a working budget card (including budget patch)
538*989cf18eSMauro Carvalho Chehab **      with vpeirq() interrupt setup in mode "0x90" (every 64K) will
539*989cf18eSMauro Carvalho Chehab **      generate 3 interrupts per 25-Hz DMA frame of 2*188*512 bytes
540*989cf18eSMauro Carvalho Chehab **      and that means 3*25=75 Hz of interrupt frequency, as seen by
541*989cf18eSMauro Carvalho Chehab **      watch cat /proc/interrupts
542*989cf18eSMauro Carvalho Chehab **
543*989cf18eSMauro Carvalho Chehab **      If this frequency is 3x lower (and data received in the DMA
544*989cf18eSMauro Carvalho Chehab **      buffer don't start with 0x47, but in the middle of packets,
545*989cf18eSMauro Carvalho Chehab **      whose lengths appear to be like 188 292 188 104 etc.
546*989cf18eSMauro Carvalho Chehab **      this means VSYNC line is not connected in the hardware.
547*989cf18eSMauro Carvalho Chehab **      (check soldering pcb and pins)
548*989cf18eSMauro Carvalho Chehab **      The same behaviour of missing VSYNC can be duplicated on budget
549*989cf18eSMauro Carvalho Chehab **      cards, by setting DD1_INIT trigger mode 7 in 3rd nibble.
550*989cf18eSMauro Carvalho Chehab */
551*989cf18eSMauro Carvalho Chehab 
552*989cf18eSMauro Carvalho Chehab 	// Setup RPS1 "program" (p35)
553*989cf18eSMauro Carvalho Chehab 	count = 0;
554*989cf18eSMauro Carvalho Chehab 
555*989cf18eSMauro Carvalho Chehab 
556*989cf18eSMauro Carvalho Chehab 	// Wait Source Line Counter Threshold                           (p36)
557*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_PAUSE | EVT_HS);
558*989cf18eSMauro Carvalho Chehab 	// Set GPIO3=1                                                  (p42)
559*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2));
560*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(GPIO3_MSK);
561*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(SAA7146_GPIO_OUTHI<<24);
562*989cf18eSMauro Carvalho Chehab #if RPS_IRQ
563*989cf18eSMauro Carvalho Chehab 	// issue RPS1 interrupt
564*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_INTERRUPT);
565*989cf18eSMauro Carvalho Chehab #endif
566*989cf18eSMauro Carvalho Chehab 	// Wait reset Source Line Counter Threshold                     (p36)
567*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_PAUSE | RPS_INV | EVT_HS);
568*989cf18eSMauro Carvalho Chehab 	// Set GPIO3=0                                                  (p42)
569*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_WR_REG_MASK | (GPIO_CTRL>>2));
570*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(GPIO3_MSK);
571*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(SAA7146_GPIO_OUTLO<<24);
572*989cf18eSMauro Carvalho Chehab #if RPS_IRQ
573*989cf18eSMauro Carvalho Chehab 	// issue RPS1 interrupt
574*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_INTERRUPT);
575*989cf18eSMauro Carvalho Chehab #endif
576*989cf18eSMauro Carvalho Chehab 	// Jump to begin of RPS program                                 (p37)
577*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(CMD_JUMP);
578*989cf18eSMauro Carvalho Chehab 	WRITE_RPS1(dev->d_rps1.dma_handle);
579*989cf18eSMauro Carvalho Chehab 
580*989cf18eSMauro Carvalho Chehab 	// Fix VSYNC level
581*989cf18eSMauro Carvalho Chehab 	saa7146_setgpio(dev, 3, SAA7146_GPIO_OUTLO);
582*989cf18eSMauro Carvalho Chehab 	// Set RPS1 Address register to point to RPS code               (r108 p42)
583*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, RPS_ADDR1, dev->d_rps1.dma_handle);
584*989cf18eSMauro Carvalho Chehab 
585*989cf18eSMauro Carvalho Chehab 	if (!(budget = kmalloc (sizeof(struct budget_patch), GFP_KERNEL)))
586*989cf18eSMauro Carvalho Chehab 		return -ENOMEM;
587*989cf18eSMauro Carvalho Chehab 
588*989cf18eSMauro Carvalho Chehab 	dprintk(2, "budget: %p\n", budget);
589*989cf18eSMauro Carvalho Chehab 
590*989cf18eSMauro Carvalho Chehab 	err = ttpci_budget_init(budget, dev, info, THIS_MODULE, adapter_nr);
591*989cf18eSMauro Carvalho Chehab 	if (err) {
592*989cf18eSMauro Carvalho Chehab 		kfree(budget);
593*989cf18eSMauro Carvalho Chehab 		return err;
594*989cf18eSMauro Carvalho Chehab 	}
595*989cf18eSMauro Carvalho Chehab 
596*989cf18eSMauro Carvalho Chehab 	// Set Source Line Counter Threshold, using BRS                 (rCC p43)
597*989cf18eSMauro Carvalho Chehab 	// It generates HS event every TS_HEIGHT lines
598*989cf18eSMauro Carvalho Chehab 	// this is related to TS_WIDTH set in register
599*989cf18eSMauro Carvalho Chehab 	// NUM_LINE_BYTE3 in budget-core.c. If NUM_LINE_BYTE
600*989cf18eSMauro Carvalho Chehab 	// low 16 bits are set to TS_WIDTH bytes (TS_WIDTH=2*188
601*989cf18eSMauro Carvalho Chehab 	//,then RPS_THRESH1
602*989cf18eSMauro Carvalho Chehab 	// should be set to trigger every TS_HEIGHT (512) lines.
603*989cf18eSMauro Carvalho Chehab 	//
604*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, RPS_THRESH1, budget->buffer_height | MASK_12 );
605*989cf18eSMauro Carvalho Chehab 
606*989cf18eSMauro Carvalho Chehab 	// saa7146_write(dev, RPS_THRESH0, ((TS_HEIGHT/2)<<16) |MASK_28| (TS_HEIGHT/2) |MASK_12 );
607*989cf18eSMauro Carvalho Chehab 	// Enable RPS1                                                  (rFC p33)
608*989cf18eSMauro Carvalho Chehab 	saa7146_write(dev, MC1, (MASK_13 | MASK_29));
609*989cf18eSMauro Carvalho Chehab 
610*989cf18eSMauro Carvalho Chehab 
611*989cf18eSMauro Carvalho Chehab 	dev->ext_priv = budget;
612*989cf18eSMauro Carvalho Chehab 
613*989cf18eSMauro Carvalho Chehab 	budget->dvb_adapter.priv = budget;
614*989cf18eSMauro Carvalho Chehab 	frontend_init(budget);
615*989cf18eSMauro Carvalho Chehab 
616*989cf18eSMauro Carvalho Chehab 	ttpci_budget_init_hooks(budget);
617*989cf18eSMauro Carvalho Chehab 
618*989cf18eSMauro Carvalho Chehab 	return 0;
619*989cf18eSMauro Carvalho Chehab }
620*989cf18eSMauro Carvalho Chehab 
budget_patch_detach(struct saa7146_dev * dev)621*989cf18eSMauro Carvalho Chehab static int budget_patch_detach (struct saa7146_dev* dev)
622*989cf18eSMauro Carvalho Chehab {
623*989cf18eSMauro Carvalho Chehab 	struct budget_patch *budget = (struct budget_patch*) dev->ext_priv;
624*989cf18eSMauro Carvalho Chehab 	int err;
625*989cf18eSMauro Carvalho Chehab 
626*989cf18eSMauro Carvalho Chehab 	if (budget->dvb_frontend) {
627*989cf18eSMauro Carvalho Chehab 		dvb_unregister_frontend(budget->dvb_frontend);
628*989cf18eSMauro Carvalho Chehab 		dvb_frontend_detach(budget->dvb_frontend);
629*989cf18eSMauro Carvalho Chehab 	}
630*989cf18eSMauro Carvalho Chehab 	err = ttpci_budget_deinit (budget);
631*989cf18eSMauro Carvalho Chehab 
632*989cf18eSMauro Carvalho Chehab 	kfree (budget);
633*989cf18eSMauro Carvalho Chehab 
634*989cf18eSMauro Carvalho Chehab 	return err;
635*989cf18eSMauro Carvalho Chehab }
636*989cf18eSMauro Carvalho Chehab 
budget_patch_init(void)637*989cf18eSMauro Carvalho Chehab static int __init budget_patch_init(void)
638*989cf18eSMauro Carvalho Chehab {
639*989cf18eSMauro Carvalho Chehab 	return saa7146_register_extension(&budget_extension);
640*989cf18eSMauro Carvalho Chehab }
641*989cf18eSMauro Carvalho Chehab 
budget_patch_exit(void)642*989cf18eSMauro Carvalho Chehab static void __exit budget_patch_exit(void)
643*989cf18eSMauro Carvalho Chehab {
644*989cf18eSMauro Carvalho Chehab 	saa7146_unregister_extension(&budget_extension);
645*989cf18eSMauro Carvalho Chehab }
646*989cf18eSMauro Carvalho Chehab 
647*989cf18eSMauro Carvalho Chehab static struct saa7146_extension budget_extension = {
648*989cf18eSMauro Carvalho Chehab 	.name           = "budget_patch dvb",
649*989cf18eSMauro Carvalho Chehab 	.flags          = 0,
650*989cf18eSMauro Carvalho Chehab 
651*989cf18eSMauro Carvalho Chehab 	.module         = THIS_MODULE,
652*989cf18eSMauro Carvalho Chehab 	.pci_tbl        = pci_tbl,
653*989cf18eSMauro Carvalho Chehab 	.attach         = budget_patch_attach,
654*989cf18eSMauro Carvalho Chehab 	.detach         = budget_patch_detach,
655*989cf18eSMauro Carvalho Chehab 
656*989cf18eSMauro Carvalho Chehab 	.irq_mask       = MASK_10,
657*989cf18eSMauro Carvalho Chehab 	.irq_func       = ttpci_budget_irq10_handler,
658*989cf18eSMauro Carvalho Chehab };
659*989cf18eSMauro Carvalho Chehab 
660*989cf18eSMauro Carvalho Chehab module_init(budget_patch_init);
661*989cf18eSMauro Carvalho Chehab module_exit(budget_patch_exit);
662*989cf18eSMauro Carvalho Chehab 
663*989cf18eSMauro Carvalho Chehab MODULE_LICENSE("GPL");
664*989cf18eSMauro Carvalho Chehab MODULE_AUTHOR("Emard, Roberto Deza, Holger Waechtler, Michael Hunold, others");
665*989cf18eSMauro Carvalho Chehab MODULE_DESCRIPTION("Driver for full TS modified DVB-S SAA7146+AV7110 based so-called Budget Patch cards");
666