1 /* 2 * Support for Intel Camera Imaging ISP subsystem. 3 * Copyright (c) 2015, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _SH_CSS_INTERNAL_H_ 16 #define _SH_CSS_INTERNAL_H_ 17 18 #include <system_global.h> 19 #include <math_support.h> 20 #include <type_support.h> 21 #include <platform_support.h> 22 #include <stdarg.h> 23 24 #if !defined(HAS_NO_INPUT_FORMATTER) 25 #include "input_formatter.h" 26 #endif 27 #include "input_system.h" 28 29 #include "ia_css_types.h" 30 #include "ia_css_acc_types.h" 31 #include "ia_css_buffer.h" 32 33 #include "ia_css_binary.h" 34 #include "sh_css_firmware.h" /* not needed/desired on SP/ISP */ 35 #include "sh_css_legacy.h" 36 #include "sh_css_defs.h" 37 #include "sh_css_uds.h" 38 #include "dma.h" /* N_DMA_CHANNEL_ID */ 39 #include "ia_css_circbuf_comm.h" /* Circular buffer */ 40 #include "ia_css_frame_comm.h" 41 #include "ia_css_3a.h" 42 #include "ia_css_dvs.h" 43 #include "ia_css_metadata.h" 44 #include "runtime/bufq/interface/ia_css_bufq.h" 45 #include "ia_css_timer.h" 46 47 /* TODO: Move to a more suitable place when sp pipeline design is done. */ 48 #define IA_CSS_NUM_CB_SEM_READ_RESOURCE 2 49 #define IA_CSS_NUM_CB_SEM_WRITE_RESOURCE 1 50 #define IA_CSS_NUM_CBS 2 51 #define IA_CSS_CB_MAX_ELEMS 2 52 53 /* Use case specific. index limited to IA_CSS_NUM_CB_SEM_READ_RESOURCE or 54 * IA_CSS_NUM_CB_SEM_WRITE_RESOURCE for read and write respectively. 55 * TODO: Enforce the limitation above. 56 */ 57 #define IA_CSS_COPYSINK_SEM_INDEX 0 58 #define IA_CSS_TAGGER_SEM_INDEX 1 59 60 /* Force generation of output event. Used by acceleration pipe. */ 61 #define IA_CSS_POST_OUT_EVENT_FORCE 2 62 63 #define SH_CSS_MAX_BINARY_NAME 64 64 65 #define SP_DEBUG_NONE (0) 66 #define SP_DEBUG_DUMP (1) 67 #define SP_DEBUG_COPY (2) 68 #define SP_DEBUG_TRACE (3) 69 #define SP_DEBUG_MINIMAL (4) 70 71 #define SP_DEBUG SP_DEBUG_NONE 72 #define SP_DEBUG_MINIMAL_OVERWRITE 1 73 74 #define SH_CSS_TNR_BIT_DEPTH 8 75 #define SH_CSS_REF_BIT_DEPTH 8 76 77 /* keep next up to date with the definition for MAX_CB_ELEMS_FOR_TAGGER in tagger.sp.c */ 78 #if defined(HAS_SP_2400) 79 #define NUM_CONTINUOUS_FRAMES 15 80 #else 81 #define NUM_CONTINUOUS_FRAMES 10 82 #endif 83 #define NUM_MIPI_FRAMES_PER_STREAM 2 84 85 #define NUM_ONLINE_INIT_CONTINUOUS_FRAMES 2 86 87 #define NR_OF_PIPELINES IA_CSS_PIPE_ID_NUM /* Must match with IA_CSS_PIPE_ID_NUM */ 88 89 #define SH_CSS_MAX_IF_CONFIGS 3 /* Must match with IA_CSS_NR_OF_CONFIGS (not defined yet).*/ 90 #define SH_CSS_IF_CONFIG_NOT_NEEDED 0xFF 91 92 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) 93 #define SH_CSS_ENABLE_METADATA 94 #endif 95 96 #if defined(SH_CSS_ENABLE_METADATA) && !defined(USE_INPUT_SYSTEM_VERSION_2401) 97 #define SH_CSS_ENABLE_METADATA_THREAD 98 #endif 99 100 /* 101 * SH_CSS_MAX_SP_THREADS: 102 * sp threads visible to host with connected communication queues 103 * these threads are capable of running an image pipe 104 * SH_CSS_MAX_SP_INTERNAL_THREADS: 105 * internal sp service threads, no communication queues to host 106 * these threads can't be used as image pipe 107 */ 108 109 #if defined(SH_CSS_ENABLE_METADATA_THREAD) 110 #define SH_CSS_SP_INTERNAL_METADATA_THREAD 1 111 #else 112 #define SH_CSS_SP_INTERNAL_METADATA_THREAD 0 113 #endif 114 115 #define SH_CSS_SP_INTERNAL_SERVICE_THREAD 1 116 117 #define SH_CSS_MAX_SP_THREADS 5 118 119 #define SH_CSS_MAX_SP_INTERNAL_THREADS (\ 120 SH_CSS_SP_INTERNAL_SERVICE_THREAD +\ 121 SH_CSS_SP_INTERNAL_METADATA_THREAD) 122 123 #define SH_CSS_MAX_PIPELINES SH_CSS_MAX_SP_THREADS 124 125 /** 126 * The C99 standard does not specify the exact object representation of structs; 127 * the representation is compiler dependent. 128 * 129 * The structs that are communicated between host and SP/ISP should have the 130 * exact same object representation. The compiler that is used to compile the 131 * firmware is hivecc. 132 * 133 * To check if a different compiler, used to compile a host application, uses 134 * another object representation, macros are defined specifying the size of 135 * the structs as expected by the firmware. 136 * 137 * A host application shall verify that a sizeof( ) of the struct is equal to 138 * the SIZE_OF_XXX macro of the corresponding struct. If they are not 139 * equal, functionality will break. 140 */ 141 #define CALC_ALIGNMENT_MEMBER(x, y) (CEIL_MUL(x, y) - x) 142 #define SIZE_OF_HRT_VADDRESS sizeof(hive_uint32) 143 #define SIZE_OF_IA_CSS_PTR sizeof(uint32_t) 144 145 /* Number of SP's */ 146 #define NUM_OF_SPS 1 147 148 #define NUM_OF_BLS 0 149 150 /* Enum for order of Binaries */ 151 enum sh_css_order_binaries { 152 SP_FIRMWARE = 0, 153 ISP_FIRMWARE 154 }; 155 156 /* 157 * JB: keep next enum in sync with thread id's 158 * and pipe id's 159 */ 160 enum sh_css_pipe_config_override { 161 SH_CSS_PIPE_CONFIG_OVRD_NONE = 0, 162 SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD = 0xffff 163 }; 164 165 enum host2sp_commands { 166 host2sp_cmd_error = 0, 167 /* 168 * The host2sp_cmd_ready command is the only command written by the SP 169 * It acknowledges that is previous command has been received. 170 * (this does not mean that the command has been executed) 171 * It also indicates that a new command can be send (it is a queue 172 * with depth 1). 173 */ 174 host2sp_cmd_ready = 1, 175 /* Command written by the Host */ 176 host2sp_cmd_dummy, /* No action, can be used as watchdog */ 177 host2sp_cmd_start_flash, /* Request SP to start the flash */ 178 host2sp_cmd_terminate, /* SP should terminate itself */ 179 N_host2sp_cmd 180 }; 181 182 /* Enumeration used to indicate the events that are produced by 183 * the SP and consumed by the Host. 184 * 185 * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: 186 * 1) "enum ia_css_event_type" (ia_css_event_public.h) 187 * 2) "enum sh_css_sp_event_type" (sh_css_internal.h) 188 * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c) 189 * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c) 190 */ 191 enum sh_css_sp_event_type { 192 SH_CSS_SP_EVENT_OUTPUT_FRAME_DONE, 193 SH_CSS_SP_EVENT_SECOND_OUTPUT_FRAME_DONE, 194 SH_CSS_SP_EVENT_VF_OUTPUT_FRAME_DONE, 195 SH_CSS_SP_EVENT_SECOND_VF_OUTPUT_FRAME_DONE, 196 SH_CSS_SP_EVENT_3A_STATISTICS_DONE, 197 SH_CSS_SP_EVENT_DIS_STATISTICS_DONE, 198 SH_CSS_SP_EVENT_PIPELINE_DONE, 199 SH_CSS_SP_EVENT_FRAME_TAGGED, 200 SH_CSS_SP_EVENT_INPUT_FRAME_DONE, 201 SH_CSS_SP_EVENT_METADATA_DONE, 202 SH_CSS_SP_EVENT_LACE_STATISTICS_DONE, 203 SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE, 204 SH_CSS_SP_EVENT_TIMER, 205 SH_CSS_SP_EVENT_PORT_EOF, 206 SH_CSS_SP_EVENT_FW_WARNING, 207 SH_CSS_SP_EVENT_FW_ASSERT, 208 SH_CSS_SP_EVENT_NR_OF_TYPES /* must be last */ 209 }; 210 211 /* xmem address map allocation per pipeline, css pointers */ 212 /* Note that the struct below should only consist of ia_css_ptr-es 213 Otherwise this will cause a fail in the function ref_sh_css_ddr_address_map 214 */ 215 struct sh_css_ddr_address_map { 216 ia_css_ptr isp_param; 217 ia_css_ptr isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; 218 ia_css_ptr macc_tbl; 219 ia_css_ptr fpn_tbl; 220 ia_css_ptr sc_tbl; 221 ia_css_ptr tetra_r_x; 222 ia_css_ptr tetra_r_y; 223 ia_css_ptr tetra_gr_x; 224 ia_css_ptr tetra_gr_y; 225 ia_css_ptr tetra_gb_x; 226 ia_css_ptr tetra_gb_y; 227 ia_css_ptr tetra_b_x; 228 ia_css_ptr tetra_b_y; 229 ia_css_ptr tetra_ratb_x; 230 ia_css_ptr tetra_ratb_y; 231 ia_css_ptr tetra_batr_x; 232 ia_css_ptr tetra_batr_y; 233 ia_css_ptr dvs_6axis_params_y; 234 }; 235 236 #define SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT \ 237 (SIZE_OF_HRT_VADDRESS + \ 238 (SH_CSS_MAX_STAGES * IA_CSS_NUM_MEMORIES * SIZE_OF_HRT_VADDRESS) + \ 239 (16 * SIZE_OF_HRT_VADDRESS)) 240 241 /* xmem address map allocation per pipeline */ 242 struct sh_css_ddr_address_map_size { 243 size_t isp_param; 244 size_t isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; 245 size_t macc_tbl; 246 size_t fpn_tbl; 247 size_t sc_tbl; 248 size_t tetra_r_x; 249 size_t tetra_r_y; 250 size_t tetra_gr_x; 251 size_t tetra_gr_y; 252 size_t tetra_gb_x; 253 size_t tetra_gb_y; 254 size_t tetra_b_x; 255 size_t tetra_b_y; 256 size_t tetra_ratb_x; 257 size_t tetra_ratb_y; 258 size_t tetra_batr_x; 259 size_t tetra_batr_y; 260 size_t dvs_6axis_params_y; 261 }; 262 263 struct sh_css_ddr_address_map_compound { 264 struct sh_css_ddr_address_map map; 265 struct sh_css_ddr_address_map_size size; 266 }; 267 268 struct ia_css_isp_parameter_set_info { 269 struct sh_css_ddr_address_map 270 mem_map;/** pointers to Parameters in ISP format IMPT: 271 This should be first member of this struct */ 272 u32 273 isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */ 274 ia_css_ptr 275 output_frame_ptr;/** Output frame to which this config has to be applied (optional) */ 276 }; 277 278 /* this struct contains all arguments that can be passed to 279 a binary. It depends on the binary which ones are used. */ 280 struct sh_css_binary_args { 281 struct ia_css_frame *in_frame; /* input frame */ 282 const struct ia_css_frame 283 *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; /* reference input frame */ 284 const struct ia_css_frame *tnr_frames[NUM_TNR_FRAMES]; /* tnr frames */ 285 struct ia_css_frame 286 *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; /* output frame */ 287 struct ia_css_frame *out_vf_frame; /* viewfinder output frame */ 288 bool copy_vf; 289 bool copy_output; 290 unsigned int vf_downscale_log2; 291 }; 292 293 #if SP_DEBUG == SP_DEBUG_DUMP 294 295 #define SH_CSS_NUM_SP_DEBUG 48 296 297 struct sh_css_sp_debug_state { 298 unsigned int error; 299 unsigned int debug[SH_CSS_NUM_SP_DEBUG]; 300 }; 301 302 #elif SP_DEBUG == SP_DEBUG_COPY 303 304 #define SH_CSS_SP_DBG_TRACE_DEPTH (40) 305 306 struct sh_css_sp_debug_trace { 307 u16 frame; 308 u16 line; 309 u16 pixel_distance; 310 u16 mipi_used_dword; 311 u16 sp_index; 312 }; 313 314 struct sh_css_sp_debug_state { 315 u16 if_start_line; 316 u16 if_start_column; 317 u16 if_cropped_height; 318 u16 if_cropped_width; 319 unsigned int index; 320 struct sh_css_sp_debug_trace 321 trace[SH_CSS_SP_DBG_TRACE_DEPTH]; 322 }; 323 324 #elif SP_DEBUG == SP_DEBUG_TRACE 325 326 #if 1 327 /* Example of just one global trace */ 328 #define SH_CSS_SP_DBG_NR_OF_TRACES (1) 329 #define SH_CSS_SP_DBG_TRACE_DEPTH (40) 330 #else 331 /* E.g. if you like separate traces for 4 threads */ 332 #define SH_CSS_SP_DBG_NR_OF_TRACES (4) 333 #define SH_CSS_SP_DBG_TRACE_DEPTH (10) 334 #endif 335 336 #define SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS (13) 337 338 struct sh_css_sp_debug_trace { 339 u16 time_stamp; 340 u16 location; /* bit 15..13 = file_id, 12..0 = line nr. */ 341 u32 data; 342 }; 343 344 struct sh_css_sp_debug_state { 345 struct sh_css_sp_debug_trace 346 trace[SH_CSS_SP_DBG_NR_OF_TRACES][SH_CSS_SP_DBG_TRACE_DEPTH]; 347 u16 index_last[SH_CSS_SP_DBG_NR_OF_TRACES]; 348 u8 index[SH_CSS_SP_DBG_NR_OF_TRACES]; 349 }; 350 351 #elif SP_DEBUG == SP_DEBUG_MINIMAL 352 353 #define SH_CSS_NUM_SP_DEBUG 128 354 355 struct sh_css_sp_debug_state { 356 unsigned int error; 357 unsigned int debug[SH_CSS_NUM_SP_DEBUG]; 358 }; 359 360 #endif 361 362 struct sh_css_sp_debug_command { 363 /* 364 * The DMA software-mask, 365 * Bit 31...24: unused. 366 * Bit 23...16: unused. 367 * Bit 15...08: reading-request enabling bits for DMA channel 7..0 368 * Bit 07...00: writing-request enabling bits for DMA channel 7..0 369 * 370 * For example, "0...0 0...0 11111011 11111101" indicates that the 371 * writing request through DMA Channel 1 and the reading request 372 * through DMA channel 2 are both disabled. The others are enabled. 373 */ 374 u32 dma_sw_reg; 375 }; 376 377 #if !defined(HAS_NO_INPUT_FORMATTER) 378 /* SP input formatter configuration.*/ 379 struct sh_css_sp_input_formatter_set { 380 u32 stream_format; 381 input_formatter_cfg_t config_a; 382 input_formatter_cfg_t config_b; 383 }; 384 #endif 385 386 #define IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT (3) 387 388 /* SP configuration information */ 389 struct sh_css_sp_config { 390 u8 no_isp_sync; /* Signal host immediately after start */ 391 u8 enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */ 392 u8 lock_all; 393 /** If raw buffer locking is enabled, this flag indicates whether raw 394 frames are locked when their EOF event is successfully sent to the 395 host (true) or when they are passed to the preview/video pipe 396 (false). */ 397 #if !defined(HAS_NO_INPUT_FORMATTER) 398 struct { 399 u8 a_changed; 400 u8 b_changed; 401 u8 isp_2ppc; 402 struct sh_css_sp_input_formatter_set 403 set[SH_CSS_MAX_IF_CONFIGS]; /* CSI-2 port is used as index. */ 404 } input_formatter; 405 #endif 406 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) 407 sync_generator_cfg_t sync_gen; 408 tpg_cfg_t tpg; 409 prbs_cfg_t prbs; 410 input_system_cfg_t input_circuit; 411 u8 input_circuit_cfg_changed; 412 u32 mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT]; 413 #endif 414 u8 enable_isys_event_queue; 415 u8 disable_cont_vf; 416 }; 417 418 enum sh_css_stage_type { 419 SH_CSS_SP_STAGE_TYPE = 0, 420 SH_CSS_ISP_STAGE_TYPE = 1 421 }; 422 423 #define SH_CSS_NUM_STAGE_TYPES 2 424 425 #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS BIT(0) 426 #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS_MASK \ 427 ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS) - 1) 428 429 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) 430 struct sh_css_sp_pipeline_terminal { 431 union { 432 /* Input System 2401 */ 433 virtual_input_system_stream_t 434 virtual_input_system_stream[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; 435 } context; 436 /* 437 * TODO 438 * - Remove "virtual_input_system_cfg" when the ISYS2401 DLI is ready. 439 */ 440 union { 441 /* Input System 2401 */ 442 virtual_input_system_stream_cfg_t 443 virtual_input_system_stream_cfg[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; 444 } ctrl; 445 }; 446 447 struct sh_css_sp_pipeline_io { 448 struct sh_css_sp_pipeline_terminal input; 449 /* pqiao: comment out temporarily to save dmem */ 450 /*struct sh_css_sp_pipeline_terminal output;*/ 451 }; 452 453 /* This struct tracks how many streams are registered per CSI port. 454 * This is used to track which streams have already been configured. 455 * Only when all streams are configured, the CSI RX is started for that port. 456 */ 457 struct sh_css_sp_pipeline_io_status { 458 u32 active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */ 459 u32 running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */ 460 }; 461 462 #endif 463 enum sh_css_port_dir { 464 SH_CSS_PORT_INPUT = 0, 465 SH_CSS_PORT_OUTPUT = 1 466 }; 467 468 enum sh_css_port_type { 469 SH_CSS_HOST_TYPE = 0, 470 SH_CSS_COPYSINK_TYPE = 1, 471 SH_CSS_TAGGERSINK_TYPE = 2 472 }; 473 474 /* Pipe inout settings: output port on 7-4bits, input port on 3-0bits */ 475 #define SH_CSS_PORT_FLD_WIDTH_IN_BITS (4) 476 #define SH_CSS_PORT_TYPE_BIT_FLD(pt) (0x1 << (pt)) 477 #define SH_CSS_PORT_FLD(pd) ((pd) ? SH_CSS_PORT_FLD_WIDTH_IN_BITS : 0) 478 #define SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) ((p) |= (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) 479 #define SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt) ((p) &= ~(SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) 480 #define SH_CSS_PIPE_PORT_CONFIG_SET(p, pd, pt, val) ((val) ? \ 481 SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) : SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt)) 482 #define SH_CSS_PIPE_PORT_CONFIG_GET(p, pd, pt) ((p) & (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) 483 #define SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(p) \ 484 (!(SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_INPUT, SH_CSS_HOST_TYPE) && \ 485 SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_OUTPUT, SH_CSS_HOST_TYPE))) 486 487 #define IA_CSS_ACQUIRE_ISP_POS 31 488 489 /* Flags for metadata processing */ 490 #define SH_CSS_METADATA_ENABLED 0x01 491 #define SH_CSS_METADATA_PROCESSED 0x02 492 #define SH_CSS_METADATA_OFFLINE_MODE 0x04 493 #define SH_CSS_METADATA_WAIT_INPUT 0x08 494 495 /* @brief Free an array of metadata buffers. 496 * 497 * @param[in] num_bufs Number of metadata buffers to be freed. 498 * @param[in] bufs Pointer of array of metadata buffers. 499 * 500 * This function frees an array of metadata buffers. 501 */ 502 void 503 ia_css_metadata_free_multiple(unsigned int num_bufs, 504 struct ia_css_metadata **bufs); 505 506 /* Macro for handling pipe_qos_config */ 507 #define QOS_INVALID (~0U) 508 #define QOS_ALL_STAGES_DISABLED (0U) 509 #define QOS_STAGE_MASK(num) (0x00000001 << num) 510 #define SH_CSS_IS_QOS_PIPE(pipe) ((pipe)->pipe_qos_config != QOS_INVALID) 511 #define SH_CSS_QOS_STAGE_ENABLE(pipe, num) ((pipe)->pipe_qos_config |= QOS_STAGE_MASK(num)) 512 #define SH_CSS_QOS_STAGE_DISABLE(pipe, num) ((pipe)->pipe_qos_config &= ~QOS_STAGE_MASK(num)) 513 #define SH_CSS_QOS_STAGE_IS_ENABLED(pipe, num) ((pipe)->pipe_qos_config & QOS_STAGE_MASK(num)) 514 #define SH_CSS_QOS_STAGE_IS_ALL_DISABLED(pipe) ((pipe)->pipe_qos_config == QOS_ALL_STAGES_DISABLED) 515 #define SH_CSS_QOS_MODE_PIPE_ADD(mode, pipe) ((mode) |= (0x1 << (pipe)->pipe_id)) 516 #define SH_CSS_QOS_MODE_PIPE_REMOVE(mode, pipe) ((mode) &= ~(0x1 << (pipe)->pipe_id)) 517 #define SH_CSS_IS_QOS_ONLY_MODE(mode) ((mode) == (0x1 << IA_CSS_PIPE_ID_ACC)) 518 519 /* Information for a pipeline */ 520 struct sh_css_sp_pipeline { 521 u32 pipe_id; /* the pipe ID */ 522 u32 pipe_num; /* the dynamic pipe number */ 523 u32 thread_id; /* the sp thread ID */ 524 u32 pipe_config; /* the pipe config */ 525 u32 pipe_qos_config; /* Bitmap of multiple QOS extension fw state. 526 (0xFFFFFFFF) indicates non QOS pipe.*/ 527 u32 inout_port_config; 528 u32 required_bds_factor; 529 u32 dvs_frame_delay; 530 u32 input_system_mode; /* enum ia_css_input_mode */ 531 u32 port_id; /* port_id for input system */ 532 u32 num_stages; /* the pipe config */ 533 u32 running; /* needed for pipe termination */ 534 ia_css_ptr sp_stage_addr[SH_CSS_MAX_STAGES]; 535 ia_css_ptr scaler_pp_lut; /* Early bound LUT */ 536 u32 dummy; /* stage ptr is only used on sp but lives in 537 this struct; needs cleanup */ 538 s32 num_execs; /* number of times to run if this is 539 an acceleration pipe. */ 540 #if defined(SH_CSS_ENABLE_METADATA) 541 struct { 542 u32 format; /* Metadata format in hrt format */ 543 u32 width; /* Width of a line */ 544 u32 height; /* Number of lines */ 545 u32 stride; /* Stride (in bytes) per line */ 546 u32 size; /* Total size (in bytes) */ 547 ia_css_ptr cont_buf; /* Address of continuous buffer */ 548 } metadata; 549 #endif 550 #if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) 551 u32 output_frame_queue_id; 552 #endif 553 union { 554 struct { 555 u32 bytes_available; 556 } bin; 557 struct { 558 u32 height; 559 u32 width; 560 u32 padded_width; 561 u32 max_input_width; 562 u32 raw_bit_depth; 563 } raw; 564 } copy; 565 566 /* ISP2401 */ 567 568 /* Parameters passed to Shading Correction kernel. */ 569 struct { 570 u32 internal_frame_origin_x_bqs_on_sctbl; /* Origin X (bqs) of internal frame on shading table */ 571 u32 internal_frame_origin_y_bqs_on_sctbl; /* Origin Y (bqs) of internal frame on shading table */ 572 } shading; 573 }; 574 575 /* 576 * The first frames (with comment Dynamic) can be dynamic or static 577 * The other frames (ref_in and below) can only be static 578 * Static means that the data address will not change during the life time 579 * of the associated pipe. Dynamic means that the data address can 580 * change with every (frame) iteration of the associated pipe 581 * 582 * s3a and dis are now also dynamic but (stil) handled separately 583 */ 584 #define SH_CSS_NUM_DYNAMIC_FRAME_IDS (3) 585 586 struct ia_css_frames_sp { 587 struct ia_css_frame_sp in; 588 struct ia_css_frame_sp out[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; 589 struct ia_css_resolution effective_in_res; 590 struct ia_css_frame_sp out_vf; 591 struct ia_css_frame_sp_info internal_frame_info; 592 struct ia_css_buffer_sp s3a_buf; 593 struct ia_css_buffer_sp dvs_buf; 594 #if defined SH_CSS_ENABLE_METADATA 595 struct ia_css_buffer_sp metadata_buf; 596 #endif 597 }; 598 599 /* Information for a single pipeline stage for an ISP */ 600 struct sh_css_isp_stage { 601 /* 602 * For compatibility and portabilty, only types 603 * from "stdint.h" are allowed 604 * 605 * Use of "enum" and "bool" is prohibited 606 * Multiple boolean flags can be stored in an 607 * integer 608 */ 609 struct ia_css_blob_info blob_info; 610 struct ia_css_binary_info binary_info; 611 char binary_name[SH_CSS_MAX_BINARY_NAME]; 612 struct ia_css_isp_param_css_segments mem_initializers; 613 }; 614 615 /* Information for a single pipeline stage */ 616 struct sh_css_sp_stage { 617 /* 618 * For compatibility and portabilty, only types 619 * from "stdint.h" are allowed 620 * 621 * Use of "enum" and "bool" is prohibited 622 * Multiple boolean flags can be stored in an 623 * integer 624 */ 625 u8 num; /* Stage number */ 626 u8 isp_online; 627 u8 isp_copy_vf; 628 u8 isp_copy_output; 629 u8 sp_enable_xnr; 630 u8 isp_deci_log_factor; 631 u8 isp_vf_downscale_bits; 632 u8 deinterleaved; 633 /* 634 * NOTE: Programming the input circuit can only be done at the 635 * start of a session. It is illegal to program it during execution 636 * The input circuit defines the connectivity 637 */ 638 u8 program_input_circuit; 639 /* enum ia_css_pipeline_stage_sp_func func; */ 640 u8 func; 641 /* The type of the pipe-stage */ 642 /* enum sh_css_stage_type stage_type; */ 643 u8 stage_type; 644 u8 num_stripes; 645 u8 isp_pipe_version; 646 struct { 647 u8 vf_output; 648 u8 s3a; 649 u8 sdis; 650 u8 dvs_stats; 651 u8 lace_stats; 652 } enable; 653 /* Add padding to come to a word boundary */ 654 /* unsigned char padding[0]; */ 655 656 struct sh_css_crop_pos sp_out_crop_pos; 657 struct ia_css_frames_sp frames; 658 struct ia_css_resolution dvs_envelope; 659 struct sh_css_uds_info uds; 660 ia_css_ptr isp_stage_addr; 661 ia_css_ptr xmem_bin_addr; 662 ia_css_ptr xmem_map_addr; 663 664 u16 top_cropping; 665 u16 row_stripes_height; 666 u16 row_stripes_overlap_lines; 667 u8 if_config_index; /* Which should be applied by this stage. */ 668 }; 669 670 /* 671 * Time: 2012-07-19, 17:40. 672 * Note: Add a new data memeber "debug" in "sh_css_sp_group". This 673 * data member is used to pass the debugging command from the 674 * Host to the SP. 675 * 676 * Time: Before 2012-07-19. 677 * Note: 678 * Group all host initialized SP variables into this struct. 679 * This is initialized every stage through dma. 680 * The stage part itself is transferred through sh_css_sp_stage. 681 */ 682 struct sh_css_sp_group { 683 struct sh_css_sp_config config; 684 struct sh_css_sp_pipeline pipe[SH_CSS_MAX_SP_THREADS]; 685 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) 686 struct sh_css_sp_pipeline_io pipe_io[SH_CSS_MAX_SP_THREADS]; 687 struct sh_css_sp_pipeline_io_status pipe_io_status; 688 #endif 689 struct sh_css_sp_debug_command debug; 690 }; 691 692 /* Data in SP dmem that is set from the host every stage. */ 693 struct sh_css_sp_per_frame_data { 694 /* ddr address of sp_group and sp_stage */ 695 ia_css_ptr sp_group_addr; 696 }; 697 698 #define SH_CSS_NUM_SDW_IRQS 3 699 700 /* Output data from SP to css */ 701 struct sh_css_sp_output { 702 unsigned int bin_copy_bytes_copied; 703 #if SP_DEBUG != SP_DEBUG_NONE 704 struct sh_css_sp_debug_state debug; 705 #endif 706 unsigned int sw_interrupt_value[SH_CSS_NUM_SDW_IRQS]; 707 }; 708 709 #define CONFIG_ON_FRAME_ENQUEUE() 0 710 711 /** 712 * @brief Data structure for the circular buffer. 713 * The circular buffer is empty if "start == end". The 714 * circular buffer is full if "(end + 1) % size == start". 715 */ 716 /* Variable Sized Buffer Queue Elements */ 717 718 #define IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE 6 719 #define IA_CSS_NUM_ELEMS_HOST2SP_PARAM_QUEUE 3 720 #define IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE 6 721 722 /* sp-to-host queue is expected to be emptied in ISR since 723 * it is used instead of HW interrupts (due to HW design issue). 724 * We need one queue element per CSI port. */ 725 #define IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS) 726 /* The host-to-sp queue needs to allow for some delay 727 * in the emptying of this queue in the SP since there is no 728 * separate SP thread for this. */ 729 #define IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS) 730 731 #if defined(HAS_SP_2400) 732 #define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 13 733 #define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 19 734 #define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 26 /* holds events for all type of buffers, hence deeper */ 735 #else 736 #define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 6 737 #define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 6 738 #define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 6 739 #endif 740 741 struct sh_css_hmm_buffer { 742 union { 743 struct ia_css_isp_3a_statistics s3a; 744 struct ia_css_isp_dvs_statistics dis; 745 ia_css_ptr skc_dvs_statistics; 746 ia_css_ptr lace_stat; 747 struct ia_css_metadata metadata; 748 struct frame_data_wrapper { 749 ia_css_ptr frame_data; 750 u32 flashed; 751 u32 exp_id; 752 u32 isp_parameters_id; /** Unique ID to track which config was 753 actually applied to a particular frame */ 754 #if CONFIG_ON_FRAME_ENQUEUE() 755 struct sh_css_config_on_frame_enqueue config_on_frame_enqueue; 756 #endif 757 } frame; 758 ia_css_ptr ddr_ptrs; 759 } payload; 760 /* 761 * kernel_ptr is present for host administration purposes only. 762 * type is uint64_t in order to be 64-bit host compatible. 763 * uint64_t does not exist on SP/ISP. 764 * Size of the struct is checked by sp.hive.c. 765 */ 766 CSS_ALIGN(u64 cookie_ptr, 8); /* TODO: check if this alignment is needed */ 767 u64 kernel_ptr; 768 struct ia_css_time_meas timing_data; 769 clock_value_t isys_eof_clock_tick; 770 }; 771 772 #if CONFIG_ON_FRAME_ENQUEUE() 773 #define SIZE_OF_FRAME_STRUCT \ 774 (SIZE_OF_HRT_VADDRESS + \ 775 (3 * sizeof(uint32_t)) + \ 776 sizeof(uint32_t)) 777 #else 778 #define SIZE_OF_FRAME_STRUCT \ 779 (SIZE_OF_HRT_VADDRESS + \ 780 (3 * sizeof(uint32_t))) 781 #endif 782 783 #define SIZE_OF_PAYLOAD_UNION \ 784 (MAX(MAX(MAX(MAX( \ 785 SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT, \ 786 SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT), \ 787 SIZE_OF_IA_CSS_METADATA_STRUCT), \ 788 SIZE_OF_FRAME_STRUCT), \ 789 SIZE_OF_HRT_VADDRESS)) 790 791 /* Do not use sizeof(uint64_t) since that does not exist of SP */ 792 #define SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT \ 793 (SIZE_OF_PAYLOAD_UNION + \ 794 CALC_ALIGNMENT_MEMBER(SIZE_OF_PAYLOAD_UNION, 8) + \ 795 8 + \ 796 8 + \ 797 SIZE_OF_IA_CSS_TIME_MEAS_STRUCT + \ 798 SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT + \ 799 CALC_ALIGNMENT_MEMBER(SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT, 8)) 800 801 enum sh_css_queue_type { 802 sh_css_invalid_queue_type = -1, 803 sh_css_host2sp_buffer_queue, 804 sh_css_sp2host_buffer_queue, 805 sh_css_host2sp_psys_event_queue, 806 sh_css_sp2host_psys_event_queue, 807 sh_css_sp2host_isys_event_queue, 808 sh_css_host2sp_isys_event_queue, 809 sh_css_host2sp_tag_cmd_queue, 810 }; 811 812 struct sh_css_event_irq_mask { 813 u16 or_mask; 814 u16 and_mask; 815 }; 816 817 #define SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT \ 818 (2 * sizeof(uint16_t)) 819 820 struct host_sp_communication { 821 /* 822 * Don't use enum host2sp_commands, because the sizeof an enum is 823 * compiler dependent and thus non-portable 824 */ 825 u32 host2sp_command; 826 827 /* 828 * The frame buffers that are reused by the 829 * copy pipe in the offline preview mode. 830 * 831 * host2sp_offline_frames[0]: the input frame of the preview pipe. 832 * host2sp_offline_frames[1]: the output frame of the copy pipe. 833 * 834 * TODO: 835 * Remove it when the Host and the SP is decoupled. 836 */ 837 ia_css_ptr host2sp_offline_frames[NUM_CONTINUOUS_FRAMES]; 838 ia_css_ptr host2sp_offline_metadata[NUM_CONTINUOUS_FRAMES]; 839 840 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) 841 ia_css_ptr host2sp_mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; 842 ia_css_ptr host2sp_mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; 843 u32 host2sp_num_mipi_frames[N_CSI_PORTS]; 844 #endif 845 u32 host2sp_cont_avail_num_raw_frames; 846 u32 host2sp_cont_extra_num_raw_frames; 847 u32 host2sp_cont_target_num_raw_frames; 848 struct sh_css_event_irq_mask host2sp_event_irq_mask[NR_OF_PIPELINES]; 849 850 }; 851 852 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) 853 #define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \ 854 (sizeof(uint32_t) + \ 855 (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \ 856 (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM * SIZE_OF_HRT_VADDRESS * 2) + \ 857 ((3 + N_CSI_PORTS) * sizeof(uint32_t)) + \ 858 (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT)) 859 #else 860 #define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \ 861 (sizeof(uint32_t) + \ 862 (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \ 863 (3 * sizeof(uint32_t)) + \ 864 (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT)) 865 #endif 866 867 struct host_sp_queues { 868 /* 869 * Queues for the dynamic frame information, 870 * i.e. the "in_frame" buffer, the "out_frame" 871 * buffer and the "vf_out_frame" buffer. 872 */ 873 ia_css_circbuf_desc_t host2sp_buffer_queues_desc 874 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]; 875 ia_css_circbuf_elem_t host2sp_buffer_queues_elems 876 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES] 877 [IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE]; 878 ia_css_circbuf_desc_t sp2host_buffer_queues_desc 879 [SH_CSS_MAX_NUM_QUEUES]; 880 ia_css_circbuf_elem_t sp2host_buffer_queues_elems 881 [SH_CSS_MAX_NUM_QUEUES][IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE]; 882 883 /* 884 * The queues for the events. 885 */ 886 ia_css_circbuf_desc_t host2sp_psys_event_queue_desc; 887 888 ia_css_circbuf_elem_t host2sp_psys_event_queue_elems 889 [IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE]; 890 ia_css_circbuf_desc_t sp2host_psys_event_queue_desc; 891 892 ia_css_circbuf_elem_t sp2host_psys_event_queue_elems 893 [IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE]; 894 895 /* 896 * The queues for the ISYS events. 897 */ 898 ia_css_circbuf_desc_t host2sp_isys_event_queue_desc; 899 900 ia_css_circbuf_elem_t host2sp_isys_event_queue_elems 901 [IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE]; 902 ia_css_circbuf_desc_t sp2host_isys_event_queue_desc; 903 904 ia_css_circbuf_elem_t sp2host_isys_event_queue_elems 905 [IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE]; 906 /* 907 * The queue for the tagger commands. 908 * CHECK: are these last two present on the 2401 ? 909 */ 910 ia_css_circbuf_desc_t host2sp_tag_cmd_queue_desc; 911 912 ia_css_circbuf_elem_t host2sp_tag_cmd_queue_elems 913 [IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE]; 914 }; 915 916 #define SIZE_OF_QUEUES_ELEMS \ 917 (SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT * \ 918 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE) + \ 919 (SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE) + \ 920 (IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE) + \ 921 (IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE) + \ 922 (IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE) + \ 923 (IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE) + \ 924 (IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE))) 925 926 #define IA_CSS_NUM_CIRCBUF_DESCS 5 927 928 #define SIZE_OF_QUEUES_DESC \ 929 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * \ 930 SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \ 931 (SH_CSS_MAX_NUM_QUEUES * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \ 932 (IA_CSS_NUM_CIRCBUF_DESCS * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT)) 933 934 #define SIZE_OF_HOST_SP_QUEUES_STRUCT \ 935 (SIZE_OF_QUEUES_ELEMS + SIZE_OF_QUEUES_DESC) 936 937 extern int (*sh_css_printf)(const char *fmt, va_list args); 938 939 static inline void 940 sh_css_print(const char *fmt, ...) 941 { 942 va_list ap; 943 944 if (sh_css_printf) { 945 va_start(ap, fmt); 946 sh_css_printf(fmt, ap); 947 va_end(ap); 948 } 949 } 950 951 static inline void 952 sh_css_vprint(const char *fmt, va_list args) 953 { 954 if (sh_css_printf) 955 sh_css_printf(fmt, args); 956 } 957 958 /* The following #if is there because this header file is also included 959 by SP and ISP code but they do not need this data and HIVECC has alignment 960 issue with the firmware struct/union's. 961 More permanent solution will be to refactor this include. 962 */ 963 ia_css_ptr sh_css_params_ddr_address_map(void); 964 965 int 966 sh_css_params_init(void); 967 968 void 969 sh_css_params_uninit(void); 970 971 /* For Acceleration API: Flush FW (shared buffer pointer) arguments */ 972 void sh_css_flush(struct ia_css_acc_fw *fw); 973 974 void 975 sh_css_binary_args_reset(struct sh_css_binary_args *args); 976 977 /* Check two frames for equality (format, resolution, bits per element) */ 978 bool 979 sh_css_frame_equal_types(const struct ia_css_frame *frame_a, 980 const struct ia_css_frame *frame_b); 981 982 bool 983 sh_css_frame_info_equal_resolution(const struct ia_css_frame_info *info_a, 984 const struct ia_css_frame_info *info_b); 985 986 void 987 sh_css_capture_enable_bayer_downscaling(bool enable); 988 989 void 990 sh_css_binary_print(const struct ia_css_binary *binary); 991 992 /* aligned argument of sh_css_frame_info_set_width can be used for an extra alignment requirement. 993 When 0, no extra alignment is done. */ 994 void 995 sh_css_frame_info_set_width(struct ia_css_frame_info *info, 996 unsigned int width, 997 unsigned int aligned); 998 999 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) 1000 1001 unsigned int 1002 sh_css_get_mipi_sizes_for_check(const unsigned int port, 1003 const unsigned int idx); 1004 1005 #endif 1006 1007 ia_css_ptr 1008 sh_css_store_sp_group_to_ddr(void); 1009 1010 ia_css_ptr 1011 sh_css_store_sp_stage_to_ddr(unsigned int pipe, unsigned int stage); 1012 1013 ia_css_ptr 1014 sh_css_store_isp_stage_to_ddr(unsigned int pipe, unsigned int stage); 1015 1016 void 1017 sh_css_update_uds_and_crop_info( 1018 const struct ia_css_binary_info *info, 1019 const struct ia_css_frame_info *in_frame_info, 1020 const struct ia_css_frame_info *out_frame_info, 1021 const struct ia_css_resolution *dvs_env, 1022 const struct ia_css_dz_config *zoom, 1023 const struct ia_css_vector *motion_vector, 1024 struct sh_css_uds_info *uds, /* out */ 1025 struct sh_css_crop_pos *sp_out_crop_pos, /* out */ 1026 1027 bool enable_zoom 1028 ); 1029 1030 void 1031 sh_css_invalidate_shading_tables(struct ia_css_stream *stream); 1032 1033 struct ia_css_pipeline * 1034 ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe); 1035 1036 unsigned int 1037 ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe); 1038 1039 unsigned int 1040 ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe); 1041 1042 bool 1043 sh_css_continuous_is_enabled(uint8_t pipe_num); 1044 1045 struct ia_css_pipe * 1046 find_pipe_by_num(uint32_t pipe_num); 1047 1048 #ifdef USE_INPUT_SYSTEM_VERSION_2401 1049 void 1050 ia_css_get_crop_offsets( 1051 struct ia_css_pipe *pipe, 1052 struct ia_css_frame_info *in_frame); 1053 #endif 1054 1055 #endif /* _SH_CSS_INTERNAL_H_ */ 1056