1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef _SH_CSS_INTERNAL_H_ 17 #define _SH_CSS_INTERNAL_H_ 18 19 #include <system_global.h> 20 #include <math_support.h> 21 #include <type_support.h> 22 #include <platform_support.h> 23 #include <stdarg.h> 24 25 #if !defined(ISP2401) 26 #include "input_formatter.h" 27 #endif 28 #include "input_system.h" 29 30 #include "ia_css_types.h" 31 #include "ia_css_acc_types.h" 32 #include "ia_css_buffer.h" 33 34 #include "ia_css_binary.h" 35 #include "sh_css_firmware.h" /* not needed/desired on SP/ISP */ 36 #include "sh_css_legacy.h" 37 #include "sh_css_defs.h" 38 #include "sh_css_uds.h" 39 #include "dma.h" /* N_DMA_CHANNEL_ID */ 40 #include "ia_css_circbuf_comm.h" /* Circular buffer */ 41 #include "ia_css_frame_comm.h" 42 #include "ia_css_3a.h" 43 #include "ia_css_dvs.h" 44 #include "ia_css_metadata.h" 45 #include "runtime/bufq/interface/ia_css_bufq.h" 46 #include "ia_css_timer.h" 47 48 /* TODO: Move to a more suitable place when sp pipeline design is done. */ 49 #define IA_CSS_NUM_CB_SEM_READ_RESOURCE 2 50 #define IA_CSS_NUM_CB_SEM_WRITE_RESOURCE 1 51 #define IA_CSS_NUM_CBS 2 52 #define IA_CSS_CB_MAX_ELEMS 2 53 54 /* Use case specific. index limited to IA_CSS_NUM_CB_SEM_READ_RESOURCE or 55 * IA_CSS_NUM_CB_SEM_WRITE_RESOURCE for read and write respectively. 56 * TODO: Enforce the limitation above. 57 */ 58 #define IA_CSS_COPYSINK_SEM_INDEX 0 59 #define IA_CSS_TAGGER_SEM_INDEX 1 60 61 /* Force generation of output event. Used by acceleration pipe. */ 62 #define IA_CSS_POST_OUT_EVENT_FORCE 2 63 64 #define SH_CSS_MAX_BINARY_NAME 64 65 66 #define SP_DEBUG_NONE (0) 67 #define SP_DEBUG_DUMP (1) 68 #define SP_DEBUG_COPY (2) 69 #define SP_DEBUG_TRACE (3) 70 #define SP_DEBUG_MINIMAL (4) 71 72 #define SP_DEBUG SP_DEBUG_NONE 73 #define SP_DEBUG_MINIMAL_OVERWRITE 1 74 75 #define SH_CSS_TNR_BIT_DEPTH 8 76 #define SH_CSS_REF_BIT_DEPTH 8 77 78 /* keep next up to date with the definition for MAX_CB_ELEMS_FOR_TAGGER in tagger.sp.c */ 79 #define NUM_CONTINUOUS_FRAMES 15 80 #define NUM_MIPI_FRAMES_PER_STREAM 2 81 82 #define NUM_ONLINE_INIT_CONTINUOUS_FRAMES 2 83 84 #define NR_OF_PIPELINES IA_CSS_PIPE_ID_NUM /* Must match with IA_CSS_PIPE_ID_NUM */ 85 86 #define SH_CSS_MAX_IF_CONFIGS 3 /* Must match with IA_CSS_NR_OF_CONFIGS (not defined yet).*/ 87 #define SH_CSS_IF_CONFIG_NOT_NEEDED 0xFF 88 89 #define SH_CSS_ENABLE_METADATA 90 91 #if defined(SH_CSS_ENABLE_METADATA) && !defined(ISP2401) 92 #define SH_CSS_ENABLE_METADATA_THREAD 93 #endif 94 95 /* 96 * SH_CSS_MAX_SP_THREADS: 97 * sp threads visible to host with connected communication queues 98 * these threads are capable of running an image pipe 99 * SH_CSS_MAX_SP_INTERNAL_THREADS: 100 * internal sp service threads, no communication queues to host 101 * these threads can't be used as image pipe 102 */ 103 104 #if defined(SH_CSS_ENABLE_METADATA_THREAD) 105 #define SH_CSS_SP_INTERNAL_METADATA_THREAD 1 106 #else 107 #define SH_CSS_SP_INTERNAL_METADATA_THREAD 0 108 #endif 109 110 #define SH_CSS_SP_INTERNAL_SERVICE_THREAD 1 111 112 #define SH_CSS_MAX_SP_THREADS 5 113 114 #define SH_CSS_MAX_SP_INTERNAL_THREADS (\ 115 SH_CSS_SP_INTERNAL_SERVICE_THREAD +\ 116 SH_CSS_SP_INTERNAL_METADATA_THREAD) 117 118 #define SH_CSS_MAX_PIPELINES SH_CSS_MAX_SP_THREADS 119 120 /** 121 * The C99 standard does not specify the exact object representation of structs; 122 * the representation is compiler dependent. 123 * 124 * The structs that are communicated between host and SP/ISP should have the 125 * exact same object representation. The compiler that is used to compile the 126 * firmware is hivecc. 127 * 128 * To check if a different compiler, used to compile a host application, uses 129 * another object representation, macros are defined specifying the size of 130 * the structs as expected by the firmware. 131 * 132 * A host application shall verify that a sizeof( ) of the struct is equal to 133 * the SIZE_OF_XXX macro of the corresponding struct. If they are not 134 * equal, functionality will break. 135 */ 136 #define CALC_ALIGNMENT_MEMBER(x, y) (CEIL_MUL(x, y) - x) 137 #define SIZE_OF_HRT_VADDRESS sizeof(hive_uint32) 138 #define SIZE_OF_IA_CSS_PTR sizeof(uint32_t) 139 140 /* Number of SP's */ 141 #define NUM_OF_SPS 1 142 143 #define NUM_OF_BLS 0 144 145 /* Enum for order of Binaries */ 146 enum sh_css_order_binaries { 147 SP_FIRMWARE = 0, 148 ISP_FIRMWARE 149 }; 150 151 /* 152 * JB: keep next enum in sync with thread id's 153 * and pipe id's 154 */ 155 enum sh_css_pipe_config_override { 156 SH_CSS_PIPE_CONFIG_OVRD_NONE = 0, 157 SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD = 0xffff 158 }; 159 160 enum host2sp_commands { 161 host2sp_cmd_error = 0, 162 /* 163 * The host2sp_cmd_ready command is the only command written by the SP 164 * It acknowledges that is previous command has been received. 165 * (this does not mean that the command has been executed) 166 * It also indicates that a new command can be send (it is a queue 167 * with depth 1). 168 */ 169 host2sp_cmd_ready = 1, 170 /* Command written by the Host */ 171 host2sp_cmd_dummy, /* No action, can be used as watchdog */ 172 host2sp_cmd_start_flash, /* Request SP to start the flash */ 173 host2sp_cmd_terminate, /* SP should terminate itself */ 174 N_host2sp_cmd 175 }; 176 177 /* Enumeration used to indicate the events that are produced by 178 * the SP and consumed by the Host. 179 * 180 * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: 181 * 1) "enum ia_css_event_type" (ia_css_event_public.h) 182 * 2) "enum sh_css_sp_event_type" (sh_css_internal.h) 183 * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c) 184 * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c) 185 */ 186 enum sh_css_sp_event_type { 187 SH_CSS_SP_EVENT_OUTPUT_FRAME_DONE, 188 SH_CSS_SP_EVENT_SECOND_OUTPUT_FRAME_DONE, 189 SH_CSS_SP_EVENT_VF_OUTPUT_FRAME_DONE, 190 SH_CSS_SP_EVENT_SECOND_VF_OUTPUT_FRAME_DONE, 191 SH_CSS_SP_EVENT_3A_STATISTICS_DONE, 192 SH_CSS_SP_EVENT_DIS_STATISTICS_DONE, 193 SH_CSS_SP_EVENT_PIPELINE_DONE, 194 SH_CSS_SP_EVENT_FRAME_TAGGED, 195 SH_CSS_SP_EVENT_INPUT_FRAME_DONE, 196 SH_CSS_SP_EVENT_METADATA_DONE, 197 SH_CSS_SP_EVENT_LACE_STATISTICS_DONE, 198 SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE, 199 SH_CSS_SP_EVENT_TIMER, 200 SH_CSS_SP_EVENT_PORT_EOF, 201 SH_CSS_SP_EVENT_FW_WARNING, 202 SH_CSS_SP_EVENT_FW_ASSERT, 203 SH_CSS_SP_EVENT_NR_OF_TYPES /* must be last */ 204 }; 205 206 /* xmem address map allocation per pipeline, css pointers */ 207 /* Note that the struct below should only consist of ia_css_ptr-es 208 Otherwise this will cause a fail in the function ref_sh_css_ddr_address_map 209 */ 210 struct sh_css_ddr_address_map { 211 ia_css_ptr isp_param; 212 ia_css_ptr isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; 213 ia_css_ptr macc_tbl; 214 ia_css_ptr fpn_tbl; 215 ia_css_ptr sc_tbl; 216 ia_css_ptr tetra_r_x; 217 ia_css_ptr tetra_r_y; 218 ia_css_ptr tetra_gr_x; 219 ia_css_ptr tetra_gr_y; 220 ia_css_ptr tetra_gb_x; 221 ia_css_ptr tetra_gb_y; 222 ia_css_ptr tetra_b_x; 223 ia_css_ptr tetra_b_y; 224 ia_css_ptr tetra_ratb_x; 225 ia_css_ptr tetra_ratb_y; 226 ia_css_ptr tetra_batr_x; 227 ia_css_ptr tetra_batr_y; 228 ia_css_ptr dvs_6axis_params_y; 229 }; 230 231 #define SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT \ 232 (SIZE_OF_HRT_VADDRESS + \ 233 (SH_CSS_MAX_STAGES * IA_CSS_NUM_MEMORIES * SIZE_OF_HRT_VADDRESS) + \ 234 (16 * SIZE_OF_HRT_VADDRESS)) 235 236 /* xmem address map allocation per pipeline */ 237 struct sh_css_ddr_address_map_size { 238 size_t isp_param; 239 size_t isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; 240 size_t macc_tbl; 241 size_t fpn_tbl; 242 size_t sc_tbl; 243 size_t tetra_r_x; 244 size_t tetra_r_y; 245 size_t tetra_gr_x; 246 size_t tetra_gr_y; 247 size_t tetra_gb_x; 248 size_t tetra_gb_y; 249 size_t tetra_b_x; 250 size_t tetra_b_y; 251 size_t tetra_ratb_x; 252 size_t tetra_ratb_y; 253 size_t tetra_batr_x; 254 size_t tetra_batr_y; 255 size_t dvs_6axis_params_y; 256 }; 257 258 struct sh_css_ddr_address_map_compound { 259 struct sh_css_ddr_address_map map; 260 struct sh_css_ddr_address_map_size size; 261 }; 262 263 struct ia_css_isp_parameter_set_info { 264 struct sh_css_ddr_address_map 265 mem_map;/** pointers to Parameters in ISP format IMPT: 266 This should be first member of this struct */ 267 u32 268 isp_parameters_id;/** Unique ID to track which config was actually applied to a particular frame */ 269 ia_css_ptr 270 output_frame_ptr;/** Output frame to which this config has to be applied (optional) */ 271 }; 272 273 /* this struct contains all arguments that can be passed to 274 a binary. It depends on the binary which ones are used. */ 275 struct sh_css_binary_args { 276 struct ia_css_frame *in_frame; /* input frame */ 277 const struct ia_css_frame 278 *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; /* reference input frame */ 279 const struct ia_css_frame *tnr_frames[NUM_TNR_FRAMES]; /* tnr frames */ 280 struct ia_css_frame 281 *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; /* output frame */ 282 struct ia_css_frame *out_vf_frame; /* viewfinder output frame */ 283 bool copy_vf; 284 bool copy_output; 285 unsigned int vf_downscale_log2; 286 }; 287 288 #if SP_DEBUG == SP_DEBUG_DUMP 289 290 #define SH_CSS_NUM_SP_DEBUG 48 291 292 struct sh_css_sp_debug_state { 293 unsigned int error; 294 unsigned int debug[SH_CSS_NUM_SP_DEBUG]; 295 }; 296 297 #elif SP_DEBUG == SP_DEBUG_COPY 298 299 #define SH_CSS_SP_DBG_TRACE_DEPTH (40) 300 301 struct sh_css_sp_debug_trace { 302 u16 frame; 303 u16 line; 304 u16 pixel_distance; 305 u16 mipi_used_dword; 306 u16 sp_index; 307 }; 308 309 struct sh_css_sp_debug_state { 310 u16 if_start_line; 311 u16 if_start_column; 312 u16 if_cropped_height; 313 u16 if_cropped_width; 314 unsigned int index; 315 struct sh_css_sp_debug_trace 316 trace[SH_CSS_SP_DBG_TRACE_DEPTH]; 317 }; 318 319 #elif SP_DEBUG == SP_DEBUG_TRACE 320 321 /* Example of just one global trace */ 322 #define SH_CSS_SP_DBG_NR_OF_TRACES (1) 323 #define SH_CSS_SP_DBG_TRACE_DEPTH (40) 324 325 #define SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS (13) 326 327 struct sh_css_sp_debug_trace { 328 u16 time_stamp; 329 u16 location; /* bit 15..13 = file_id, 12..0 = line nr. */ 330 u32 data; 331 }; 332 333 struct sh_css_sp_debug_state { 334 struct sh_css_sp_debug_trace 335 trace[SH_CSS_SP_DBG_NR_OF_TRACES][SH_CSS_SP_DBG_TRACE_DEPTH]; 336 u16 index_last[SH_CSS_SP_DBG_NR_OF_TRACES]; 337 u8 index[SH_CSS_SP_DBG_NR_OF_TRACES]; 338 }; 339 340 #elif SP_DEBUG == SP_DEBUG_MINIMAL 341 342 #define SH_CSS_NUM_SP_DEBUG 128 343 344 struct sh_css_sp_debug_state { 345 unsigned int error; 346 unsigned int debug[SH_CSS_NUM_SP_DEBUG]; 347 }; 348 349 #endif 350 351 struct sh_css_sp_debug_command { 352 /* 353 * The DMA software-mask, 354 * Bit 31...24: unused. 355 * Bit 23...16: unused. 356 * Bit 15...08: reading-request enabling bits for DMA channel 7..0 357 * Bit 07...00: writing-request enabling bits for DMA channel 7..0 358 * 359 * For example, "0...0 0...0 11111011 11111101" indicates that the 360 * writing request through DMA Channel 1 and the reading request 361 * through DMA channel 2 are both disabled. The others are enabled. 362 */ 363 u32 dma_sw_reg; 364 }; 365 366 #if !defined(ISP2401) 367 /* SP input formatter configuration.*/ 368 struct sh_css_sp_input_formatter_set { 369 u32 stream_format; 370 input_formatter_cfg_t config_a; 371 input_formatter_cfg_t config_b; 372 }; 373 #endif 374 375 #define IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT (3) 376 377 /* SP configuration information */ 378 struct sh_css_sp_config { 379 u8 no_isp_sync; /* Signal host immediately after start */ 380 u8 enable_raw_pool_locking; /** Enable Raw Buffer Locking for HALv3 Support */ 381 u8 lock_all; 382 /** If raw buffer locking is enabled, this flag indicates whether raw 383 frames are locked when their EOF event is successfully sent to the 384 host (true) or when they are passed to the preview/video pipe 385 (false). */ 386 #if !defined(ISP2401) 387 struct { 388 u8 a_changed; 389 u8 b_changed; 390 u8 isp_2ppc; 391 struct sh_css_sp_input_formatter_set 392 set[SH_CSS_MAX_IF_CONFIGS]; /* CSI-2 port is used as index. */ 393 } input_formatter; 394 #endif 395 #if !defined(ISP2401) 396 sync_generator_cfg_t sync_gen; 397 tpg_cfg_t tpg; 398 prbs_cfg_t prbs; 399 input_system_cfg_t input_circuit; 400 u8 input_circuit_cfg_changed; 401 u32 mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT]; 402 #endif 403 u8 enable_isys_event_queue; 404 u8 disable_cont_vf; 405 }; 406 407 enum sh_css_stage_type { 408 SH_CSS_SP_STAGE_TYPE = 0, 409 SH_CSS_ISP_STAGE_TYPE = 1 410 }; 411 412 #define SH_CSS_NUM_STAGE_TYPES 2 413 414 #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS BIT(0) 415 #define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS_MASK \ 416 ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS) - 1) 417 418 #if defined(ISP2401) 419 struct sh_css_sp_pipeline_terminal { 420 union { 421 /* Input System 2401 */ 422 virtual_input_system_stream_t 423 virtual_input_system_stream[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; 424 } context; 425 /* 426 * TODO 427 * - Remove "virtual_input_system_cfg" when the ISYS2401 DLI is ready. 428 */ 429 union { 430 /* Input System 2401 */ 431 virtual_input_system_stream_cfg_t 432 virtual_input_system_stream_cfg[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; 433 } ctrl; 434 }; 435 436 struct sh_css_sp_pipeline_io { 437 struct sh_css_sp_pipeline_terminal input; 438 /* pqiao: comment out temporarily to save dmem */ 439 /*struct sh_css_sp_pipeline_terminal output;*/ 440 }; 441 442 /* This struct tracks how many streams are registered per CSI port. 443 * This is used to track which streams have already been configured. 444 * Only when all streams are configured, the CSI RX is started for that port. 445 */ 446 struct sh_css_sp_pipeline_io_status { 447 u32 active[N_INPUT_SYSTEM_CSI_PORT]; /** registered streams */ 448 u32 running[N_INPUT_SYSTEM_CSI_PORT]; /** configured streams */ 449 }; 450 451 #endif 452 enum sh_css_port_dir { 453 SH_CSS_PORT_INPUT = 0, 454 SH_CSS_PORT_OUTPUT = 1 455 }; 456 457 enum sh_css_port_type { 458 SH_CSS_HOST_TYPE = 0, 459 SH_CSS_COPYSINK_TYPE = 1, 460 SH_CSS_TAGGERSINK_TYPE = 2 461 }; 462 463 /* Pipe inout settings: output port on 7-4bits, input port on 3-0bits */ 464 #define SH_CSS_PORT_FLD_WIDTH_IN_BITS (4) 465 #define SH_CSS_PORT_TYPE_BIT_FLD(pt) (0x1 << (pt)) 466 #define SH_CSS_PORT_FLD(pd) ((pd) ? SH_CSS_PORT_FLD_WIDTH_IN_BITS : 0) 467 #define SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) ((p) |= (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) 468 #define SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt) ((p) &= ~(SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) 469 #define SH_CSS_PIPE_PORT_CONFIG_SET(p, pd, pt, val) ((val) ? \ 470 SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) : SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt)) 471 #define SH_CSS_PIPE_PORT_CONFIG_GET(p, pd, pt) ((p) & (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) 472 #define SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(p) \ 473 (!(SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_INPUT, SH_CSS_HOST_TYPE) && \ 474 SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_OUTPUT, SH_CSS_HOST_TYPE))) 475 476 #define IA_CSS_ACQUIRE_ISP_POS 31 477 478 /* Flags for metadata processing */ 479 #define SH_CSS_METADATA_ENABLED 0x01 480 #define SH_CSS_METADATA_PROCESSED 0x02 481 #define SH_CSS_METADATA_OFFLINE_MODE 0x04 482 #define SH_CSS_METADATA_WAIT_INPUT 0x08 483 484 /* @brief Free an array of metadata buffers. 485 * 486 * @param[in] num_bufs Number of metadata buffers to be freed. 487 * @param[in] bufs Pointer of array of metadata buffers. 488 * 489 * This function frees an array of metadata buffers. 490 */ 491 void 492 ia_css_metadata_free_multiple(unsigned int num_bufs, 493 struct ia_css_metadata **bufs); 494 495 /* Macro for handling pipe_qos_config */ 496 #define QOS_INVALID (~0U) 497 #define QOS_ALL_STAGES_DISABLED (0U) 498 #define QOS_STAGE_MASK(num) (0x00000001 << num) 499 #define SH_CSS_IS_QOS_PIPE(pipe) ((pipe)->pipe_qos_config != QOS_INVALID) 500 #define SH_CSS_QOS_STAGE_ENABLE(pipe, num) ((pipe)->pipe_qos_config |= QOS_STAGE_MASK(num)) 501 #define SH_CSS_QOS_STAGE_DISABLE(pipe, num) ((pipe)->pipe_qos_config &= ~QOS_STAGE_MASK(num)) 502 #define SH_CSS_QOS_STAGE_IS_ENABLED(pipe, num) ((pipe)->pipe_qos_config & QOS_STAGE_MASK(num)) 503 #define SH_CSS_QOS_STAGE_IS_ALL_DISABLED(pipe) ((pipe)->pipe_qos_config == QOS_ALL_STAGES_DISABLED) 504 #define SH_CSS_QOS_MODE_PIPE_ADD(mode, pipe) ((mode) |= (0x1 << (pipe)->pipe_id)) 505 #define SH_CSS_QOS_MODE_PIPE_REMOVE(mode, pipe) ((mode) &= ~(0x1 << (pipe)->pipe_id)) 506 #define SH_CSS_IS_QOS_ONLY_MODE(mode) ((mode) == (0x1 << IA_CSS_PIPE_ID_ACC)) 507 508 /* Information for a pipeline */ 509 struct sh_css_sp_pipeline { 510 u32 pipe_id; /* the pipe ID */ 511 u32 pipe_num; /* the dynamic pipe number */ 512 u32 thread_id; /* the sp thread ID */ 513 u32 pipe_config; /* the pipe config */ 514 u32 pipe_qos_config; /* Bitmap of multiple QOS extension fw state. 515 (0xFFFFFFFF) indicates non QOS pipe.*/ 516 u32 inout_port_config; 517 u32 required_bds_factor; 518 u32 dvs_frame_delay; 519 u32 input_system_mode; /* enum ia_css_input_mode */ 520 u32 port_id; /* port_id for input system */ 521 u32 num_stages; /* the pipe config */ 522 u32 running; /* needed for pipe termination */ 523 ia_css_ptr sp_stage_addr[SH_CSS_MAX_STAGES]; 524 ia_css_ptr scaler_pp_lut; /* Early bound LUT */ 525 u32 dummy; /* stage ptr is only used on sp but lives in 526 this struct; needs cleanup */ 527 s32 num_execs; /* number of times to run if this is 528 an acceleration pipe. */ 529 #if defined(SH_CSS_ENABLE_METADATA) 530 struct { 531 u32 format; /* Metadata format in hrt format */ 532 u32 width; /* Width of a line */ 533 u32 height; /* Number of lines */ 534 u32 stride; /* Stride (in bytes) per line */ 535 u32 size; /* Total size (in bytes) */ 536 ia_css_ptr cont_buf; /* Address of continuous buffer */ 537 } metadata; 538 #endif 539 #if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) 540 u32 output_frame_queue_id; 541 #endif 542 union { 543 struct { 544 u32 bytes_available; 545 } bin; 546 struct { 547 u32 height; 548 u32 width; 549 u32 padded_width; 550 u32 max_input_width; 551 u32 raw_bit_depth; 552 } raw; 553 } copy; 554 555 /* ISP2401 */ 556 557 /* Parameters passed to Shading Correction kernel. */ 558 struct { 559 u32 internal_frame_origin_x_bqs_on_sctbl; /* Origin X (bqs) of internal frame on shading table */ 560 u32 internal_frame_origin_y_bqs_on_sctbl; /* Origin Y (bqs) of internal frame on shading table */ 561 } shading; 562 }; 563 564 /* 565 * The first frames (with comment Dynamic) can be dynamic or static 566 * The other frames (ref_in and below) can only be static 567 * Static means that the data address will not change during the life time 568 * of the associated pipe. Dynamic means that the data address can 569 * change with every (frame) iteration of the associated pipe 570 * 571 * s3a and dis are now also dynamic but (stil) handled separately 572 */ 573 #define SH_CSS_NUM_DYNAMIC_FRAME_IDS (3) 574 575 struct ia_css_frames_sp { 576 struct ia_css_frame_sp in; 577 struct ia_css_frame_sp out[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; 578 struct ia_css_resolution effective_in_res; 579 struct ia_css_frame_sp out_vf; 580 struct ia_css_frame_sp_info internal_frame_info; 581 struct ia_css_buffer_sp s3a_buf; 582 struct ia_css_buffer_sp dvs_buf; 583 #if defined SH_CSS_ENABLE_METADATA 584 struct ia_css_buffer_sp metadata_buf; 585 #endif 586 }; 587 588 /* Information for a single pipeline stage for an ISP */ 589 struct sh_css_isp_stage { 590 /* 591 * For compatibility and portabilty, only types 592 * from "stdint.h" are allowed 593 * 594 * Use of "enum" and "bool" is prohibited 595 * Multiple boolean flags can be stored in an 596 * integer 597 */ 598 struct ia_css_blob_info blob_info; 599 struct ia_css_binary_info binary_info; 600 char binary_name[SH_CSS_MAX_BINARY_NAME]; 601 struct ia_css_isp_param_css_segments mem_initializers; 602 }; 603 604 /* Information for a single pipeline stage */ 605 struct sh_css_sp_stage { 606 /* 607 * For compatibility and portabilty, only types 608 * from "stdint.h" are allowed 609 * 610 * Use of "enum" and "bool" is prohibited 611 * Multiple boolean flags can be stored in an 612 * integer 613 */ 614 u8 num; /* Stage number */ 615 u8 isp_online; 616 u8 isp_copy_vf; 617 u8 isp_copy_output; 618 u8 sp_enable_xnr; 619 u8 isp_deci_log_factor; 620 u8 isp_vf_downscale_bits; 621 u8 deinterleaved; 622 /* 623 * NOTE: Programming the input circuit can only be done at the 624 * start of a session. It is illegal to program it during execution 625 * The input circuit defines the connectivity 626 */ 627 u8 program_input_circuit; 628 /* enum ia_css_pipeline_stage_sp_func func; */ 629 u8 func; 630 /* The type of the pipe-stage */ 631 /* enum sh_css_stage_type stage_type; */ 632 u8 stage_type; 633 u8 num_stripes; 634 u8 isp_pipe_version; 635 struct { 636 u8 vf_output; 637 u8 s3a; 638 u8 sdis; 639 u8 dvs_stats; 640 u8 lace_stats; 641 } enable; 642 /* Add padding to come to a word boundary */ 643 /* unsigned char padding[0]; */ 644 645 struct sh_css_crop_pos sp_out_crop_pos; 646 struct ia_css_frames_sp frames; 647 struct ia_css_resolution dvs_envelope; 648 struct sh_css_uds_info uds; 649 ia_css_ptr isp_stage_addr; 650 ia_css_ptr xmem_bin_addr; 651 ia_css_ptr xmem_map_addr; 652 653 u16 top_cropping; 654 u16 row_stripes_height; 655 u16 row_stripes_overlap_lines; 656 u8 if_config_index; /* Which should be applied by this stage. */ 657 }; 658 659 /* 660 * Time: 2012-07-19, 17:40. 661 * Note: Add a new data memeber "debug" in "sh_css_sp_group". This 662 * data member is used to pass the debugging command from the 663 * Host to the SP. 664 * 665 * Time: Before 2012-07-19. 666 * Note: 667 * Group all host initialized SP variables into this struct. 668 * This is initialized every stage through dma. 669 * The stage part itself is transferred through sh_css_sp_stage. 670 */ 671 struct sh_css_sp_group { 672 struct sh_css_sp_config config; 673 struct sh_css_sp_pipeline pipe[SH_CSS_MAX_SP_THREADS]; 674 #if defined(ISP2401) 675 struct sh_css_sp_pipeline_io pipe_io[SH_CSS_MAX_SP_THREADS]; 676 struct sh_css_sp_pipeline_io_status pipe_io_status; 677 #endif 678 struct sh_css_sp_debug_command debug; 679 }; 680 681 /* Data in SP dmem that is set from the host every stage. */ 682 struct sh_css_sp_per_frame_data { 683 /* ddr address of sp_group and sp_stage */ 684 ia_css_ptr sp_group_addr; 685 }; 686 687 #define SH_CSS_NUM_SDW_IRQS 3 688 689 /* Output data from SP to css */ 690 struct sh_css_sp_output { 691 unsigned int bin_copy_bytes_copied; 692 #if SP_DEBUG != SP_DEBUG_NONE 693 struct sh_css_sp_debug_state debug; 694 #endif 695 unsigned int sw_interrupt_value[SH_CSS_NUM_SDW_IRQS]; 696 }; 697 698 #define CONFIG_ON_FRAME_ENQUEUE() 0 699 700 /** 701 * @brief Data structure for the circular buffer. 702 * The circular buffer is empty if "start == end". The 703 * circular buffer is full if "(end + 1) % size == start". 704 */ 705 /* Variable Sized Buffer Queue Elements */ 706 707 #define IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE 6 708 #define IA_CSS_NUM_ELEMS_HOST2SP_PARAM_QUEUE 3 709 #define IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE 6 710 711 /* sp-to-host queue is expected to be emptied in ISR since 712 * it is used instead of HW interrupts (due to HW design issue). 713 * We need one queue element per CSI port. */ 714 #define IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS) 715 /* The host-to-sp queue needs to allow for some delay 716 * in the emptying of this queue in the SP since there is no 717 * separate SP thread for this. */ 718 #define IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS) 719 720 #define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 13 721 #define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 19 722 #define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 26 /* holds events for all type of buffers, hence deeper */ 723 724 struct sh_css_hmm_buffer { 725 union { 726 struct ia_css_isp_3a_statistics s3a; 727 struct ia_css_isp_dvs_statistics dis; 728 ia_css_ptr skc_dvs_statistics; 729 ia_css_ptr lace_stat; 730 struct ia_css_metadata metadata; 731 struct frame_data_wrapper { 732 ia_css_ptr frame_data; 733 u32 flashed; 734 u32 exp_id; 735 u32 isp_parameters_id; /** Unique ID to track which config was 736 actually applied to a particular frame */ 737 #if CONFIG_ON_FRAME_ENQUEUE() 738 struct sh_css_config_on_frame_enqueue config_on_frame_enqueue; 739 #endif 740 } frame; 741 ia_css_ptr ddr_ptrs; 742 } payload; 743 /* 744 * kernel_ptr is present for host administration purposes only. 745 * type is uint64_t in order to be 64-bit host compatible. 746 * uint64_t does not exist on SP/ISP. 747 * Size of the struct is checked by sp.hive.c. 748 */ 749 CSS_ALIGN(u64 cookie_ptr, 8); /* TODO: check if this alignment is needed */ 750 u64 kernel_ptr; 751 struct ia_css_time_meas timing_data; 752 clock_value_t isys_eof_clock_tick; 753 }; 754 755 #if CONFIG_ON_FRAME_ENQUEUE() 756 #define SIZE_OF_FRAME_STRUCT \ 757 (SIZE_OF_HRT_VADDRESS + \ 758 (3 * sizeof(uint32_t)) + \ 759 sizeof(uint32_t)) 760 #else 761 #define SIZE_OF_FRAME_STRUCT \ 762 (SIZE_OF_HRT_VADDRESS + \ 763 (3 * sizeof(uint32_t))) 764 #endif 765 766 #define SIZE_OF_PAYLOAD_UNION \ 767 (MAX(MAX(MAX(MAX( \ 768 SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT, \ 769 SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT), \ 770 SIZE_OF_IA_CSS_METADATA_STRUCT), \ 771 SIZE_OF_FRAME_STRUCT), \ 772 SIZE_OF_HRT_VADDRESS)) 773 774 /* Do not use sizeof(uint64_t) since that does not exist of SP */ 775 #define SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT \ 776 (SIZE_OF_PAYLOAD_UNION + \ 777 CALC_ALIGNMENT_MEMBER(SIZE_OF_PAYLOAD_UNION, 8) + \ 778 8 + \ 779 8 + \ 780 SIZE_OF_IA_CSS_TIME_MEAS_STRUCT + \ 781 SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT + \ 782 CALC_ALIGNMENT_MEMBER(SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT, 8)) 783 784 enum sh_css_queue_type { 785 sh_css_invalid_queue_type = -1, 786 sh_css_host2sp_buffer_queue, 787 sh_css_sp2host_buffer_queue, 788 sh_css_host2sp_psys_event_queue, 789 sh_css_sp2host_psys_event_queue, 790 sh_css_sp2host_isys_event_queue, 791 sh_css_host2sp_isys_event_queue, 792 sh_css_host2sp_tag_cmd_queue, 793 }; 794 795 struct sh_css_event_irq_mask { 796 u16 or_mask; 797 u16 and_mask; 798 }; 799 800 #define SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT \ 801 (2 * sizeof(uint16_t)) 802 803 struct host_sp_communication { 804 /* 805 * Don't use enum host2sp_commands, because the sizeof an enum is 806 * compiler dependent and thus non-portable 807 */ 808 u32 host2sp_command; 809 810 /* 811 * The frame buffers that are reused by the 812 * copy pipe in the offline preview mode. 813 * 814 * host2sp_offline_frames[0]: the input frame of the preview pipe. 815 * host2sp_offline_frames[1]: the output frame of the copy pipe. 816 * 817 * TODO: 818 * Remove it when the Host and the SP is decoupled. 819 */ 820 ia_css_ptr host2sp_offline_frames[NUM_CONTINUOUS_FRAMES]; 821 ia_css_ptr host2sp_offline_metadata[NUM_CONTINUOUS_FRAMES]; 822 823 ia_css_ptr host2sp_mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; 824 ia_css_ptr host2sp_mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; 825 u32 host2sp_num_mipi_frames[N_CSI_PORTS]; 826 u32 host2sp_cont_avail_num_raw_frames; 827 u32 host2sp_cont_extra_num_raw_frames; 828 u32 host2sp_cont_target_num_raw_frames; 829 struct sh_css_event_irq_mask host2sp_event_irq_mask[NR_OF_PIPELINES]; 830 831 }; 832 833 #define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \ 834 (sizeof(uint32_t) + \ 835 (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \ 836 (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM * SIZE_OF_HRT_VADDRESS * 2) + \ 837 ((3 + N_CSI_PORTS) * sizeof(uint32_t)) + \ 838 (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT)) 839 840 struct host_sp_queues { 841 /* 842 * Queues for the dynamic frame information, 843 * i.e. the "in_frame" buffer, the "out_frame" 844 * buffer and the "vf_out_frame" buffer. 845 */ 846 ia_css_circbuf_desc_t host2sp_buffer_queues_desc 847 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]; 848 ia_css_circbuf_elem_t host2sp_buffer_queues_elems 849 [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES] 850 [IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE]; 851 ia_css_circbuf_desc_t sp2host_buffer_queues_desc 852 [SH_CSS_MAX_NUM_QUEUES]; 853 ia_css_circbuf_elem_t sp2host_buffer_queues_elems 854 [SH_CSS_MAX_NUM_QUEUES][IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE]; 855 856 /* 857 * The queues for the events. 858 */ 859 ia_css_circbuf_desc_t host2sp_psys_event_queue_desc; 860 861 ia_css_circbuf_elem_t host2sp_psys_event_queue_elems 862 [IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE]; 863 ia_css_circbuf_desc_t sp2host_psys_event_queue_desc; 864 865 ia_css_circbuf_elem_t sp2host_psys_event_queue_elems 866 [IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE]; 867 868 /* 869 * The queues for the ISYS events. 870 */ 871 ia_css_circbuf_desc_t host2sp_isys_event_queue_desc; 872 873 ia_css_circbuf_elem_t host2sp_isys_event_queue_elems 874 [IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE]; 875 ia_css_circbuf_desc_t sp2host_isys_event_queue_desc; 876 877 ia_css_circbuf_elem_t sp2host_isys_event_queue_elems 878 [IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE]; 879 /* 880 * The queue for the tagger commands. 881 * CHECK: are these last two present on the 2401 ? 882 */ 883 ia_css_circbuf_desc_t host2sp_tag_cmd_queue_desc; 884 885 ia_css_circbuf_elem_t host2sp_tag_cmd_queue_elems 886 [IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE]; 887 }; 888 889 #define SIZE_OF_QUEUES_ELEMS \ 890 (SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT * \ 891 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE) + \ 892 (SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE) + \ 893 (IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE) + \ 894 (IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE) + \ 895 (IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE) + \ 896 (IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE) + \ 897 (IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE))) 898 899 #define IA_CSS_NUM_CIRCBUF_DESCS 5 900 901 #define SIZE_OF_QUEUES_DESC \ 902 ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * \ 903 SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \ 904 (SH_CSS_MAX_NUM_QUEUES * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \ 905 (IA_CSS_NUM_CIRCBUF_DESCS * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT)) 906 907 #define SIZE_OF_HOST_SP_QUEUES_STRUCT \ 908 (SIZE_OF_QUEUES_ELEMS + SIZE_OF_QUEUES_DESC) 909 910 extern int __printf(1, 0) (*sh_css_printf)(const char *fmt, va_list args); 911 912 static inline void __printf(1, 2) sh_css_print(const char *fmt, ...) 913 { 914 va_list ap; 915 916 if (sh_css_printf) { 917 va_start(ap, fmt); 918 sh_css_printf(fmt, ap); 919 va_end(ap); 920 } 921 } 922 923 static inline void __printf(1, 0) sh_css_vprint(const char *fmt, va_list args) 924 { 925 if (sh_css_printf) 926 sh_css_printf(fmt, args); 927 } 928 929 /* The following #if is there because this header file is also included 930 by SP and ISP code but they do not need this data and HIVECC has alignment 931 issue with the firmware struct/union's. 932 More permanent solution will be to refactor this include. 933 */ 934 ia_css_ptr sh_css_params_ddr_address_map(void); 935 936 int 937 sh_css_params_init(void); 938 939 void 940 sh_css_params_uninit(void); 941 942 /* For Acceleration API: Flush FW (shared buffer pointer) arguments */ 943 void sh_css_flush(struct ia_css_acc_fw *fw); 944 945 void 946 sh_css_binary_args_reset(struct sh_css_binary_args *args); 947 948 /* Check two frames for equality (format, resolution, bits per element) */ 949 bool 950 sh_css_frame_equal_types(const struct ia_css_frame *frame_a, 951 const struct ia_css_frame *frame_b); 952 953 bool 954 sh_css_frame_info_equal_resolution(const struct ia_css_frame_info *info_a, 955 const struct ia_css_frame_info *info_b); 956 957 void 958 sh_css_capture_enable_bayer_downscaling(bool enable); 959 960 void 961 sh_css_binary_print(const struct ia_css_binary *binary); 962 963 /* aligned argument of sh_css_frame_info_set_width can be used for an extra alignment requirement. 964 When 0, no extra alignment is done. */ 965 void 966 sh_css_frame_info_set_width(struct ia_css_frame_info *info, 967 unsigned int width, 968 unsigned int aligned); 969 970 #if !defined(ISP2401) 971 972 unsigned int 973 sh_css_get_mipi_sizes_for_check(const unsigned int port, 974 const unsigned int idx); 975 976 #endif 977 978 ia_css_ptr 979 sh_css_store_sp_group_to_ddr(void); 980 981 ia_css_ptr 982 sh_css_store_sp_stage_to_ddr(unsigned int pipe, unsigned int stage); 983 984 ia_css_ptr 985 sh_css_store_isp_stage_to_ddr(unsigned int pipe, unsigned int stage); 986 987 void 988 sh_css_update_uds_and_crop_info( 989 const struct ia_css_binary_info *info, 990 const struct ia_css_frame_info *in_frame_info, 991 const struct ia_css_frame_info *out_frame_info, 992 const struct ia_css_resolution *dvs_env, 993 const struct ia_css_dz_config *zoom, 994 const struct ia_css_vector *motion_vector, 995 struct sh_css_uds_info *uds, /* out */ 996 struct sh_css_crop_pos *sp_out_crop_pos, /* out */ 997 998 bool enable_zoom 999 ); 1000 1001 void 1002 sh_css_invalidate_shading_tables(struct ia_css_stream *stream); 1003 1004 struct ia_css_pipeline * 1005 ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe); 1006 1007 unsigned int 1008 ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe); 1009 1010 unsigned int 1011 ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe); 1012 1013 bool 1014 sh_css_continuous_is_enabled(uint8_t pipe_num); 1015 1016 struct ia_css_pipe * 1017 find_pipe_by_num(uint32_t pipe_num); 1018 1019 #ifdef ISP2401 1020 void 1021 ia_css_get_crop_offsets( 1022 struct ia_css_pipe *pipe, 1023 struct ia_css_frame_info *in_frame); 1024 #endif 1025 1026 #endif /* _SH_CSS_INTERNAL_H_ */ 1027