1 /* 2 * Support for Intel Camera Imaging ISP subsystem. 3 * Copyright (c) 2015, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include "debug.h" 16 #include "memory_access.h" 17 18 #ifndef __INLINE_INPUT_SYSTEM__ 19 #define __INLINE_INPUT_SYSTEM__ 20 #endif 21 #ifndef __INLINE_IBUF_CTRL__ 22 #define __INLINE_IBUF_CTRL__ 23 #endif 24 #ifndef __INLINE_CSI_RX__ 25 #define __INLINE_CSI_RX__ 26 #endif 27 #ifndef __INLINE_PIXELGEN__ 28 #define __INLINE_PIXELGEN__ 29 #endif 30 #ifndef __INLINE_STREAM2MMIO__ 31 #define __INLINE_STREAM2MMIO__ 32 #endif 33 34 #include "ia_css_debug.h" 35 #include "ia_css_debug_pipe.h" 36 #include "ia_css_irq.h" 37 #include "ia_css_stream.h" 38 #include "ia_css_pipeline.h" 39 #include "ia_css_isp_param.h" 40 #include "sh_css_params.h" 41 #include "ia_css_bufq.h" 42 /* ISP2401 */ 43 #include "ia_css_queue.h" 44 45 #include "ia_css_isp_params.h" 46 47 #include "system_local.h" 48 #include "assert_support.h" 49 #include "print_support.h" 50 #include "string_support.h" 51 52 #include "fifo_monitor.h" 53 54 #if !defined(HAS_NO_INPUT_FORMATTER) 55 #include "input_formatter.h" 56 #endif 57 #include "dma.h" 58 #include "irq.h" 59 #include "gp_device.h" 60 #include "sp.h" 61 #include "isp.h" 62 #include "type_support.h" 63 #include "math_support.h" /* CEIL_DIV */ 64 #if defined(HAS_INPUT_FORMATTER_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) 65 #include "input_system.h" /* input_formatter_reg_load */ 66 #endif 67 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) 68 #include "ia_css_tagger_common.h" 69 #endif 70 71 #include "sh_css_internal.h" 72 #if !defined(HAS_NO_INPUT_SYSTEM) 73 #include "ia_css_isys.h" 74 #endif 75 #include "sh_css_sp.h" /* sh_css_sp_get_debug_state() */ 76 77 #include "css_trace.h" /* tracer */ 78 79 #include "device_access.h" /* for ia_css_device_load_uint32 */ 80 81 /* Include all kernel host interfaces for ISP1 */ 82 #include "anr/anr_1.0/ia_css_anr.host.h" 83 #include "cnr/cnr_1.0/ia_css_cnr.host.h" 84 #include "csc/csc_1.0/ia_css_csc.host.h" 85 #include "de/de_1.0/ia_css_de.host.h" 86 #include "dp/dp_1.0/ia_css_dp.host.h" 87 #include "bnr/bnr_1.0/ia_css_bnr.host.h" 88 #include "fpn/fpn_1.0/ia_css_fpn.host.h" 89 #include "gc/gc_1.0/ia_css_gc.host.h" 90 #include "ob/ob_1.0/ia_css_ob.host.h" 91 #include "s3a/s3a_1.0/ia_css_s3a.host.h" 92 #include "sc/sc_1.0/ia_css_sc.host.h" 93 #include "tnr/tnr_1.0/ia_css_tnr.host.h" 94 #include "uds/uds_1.0/ia_css_uds_param.h" 95 #include "wb/wb_1.0/ia_css_wb.host.h" 96 #include "ynr/ynr_1.0/ia_css_ynr.host.h" 97 98 /* Include additional kernel host interfaces for ISP2 */ 99 #include "aa/aa_2/ia_css_aa2.host.h" 100 #include "anr/anr_2/ia_css_anr2.host.h" 101 #include "cnr/cnr_2/ia_css_cnr2.host.h" 102 #include "de/de_2/ia_css_de2.host.h" 103 #include "gc/gc_2/ia_css_gc2.host.h" 104 #include "ynr/ynr_2/ia_css_ynr2.host.h" 105 106 #define DPG_START "ia_css_debug_pipe_graph_dump_start " 107 #define DPG_END " ia_css_debug_pipe_graph_dump_end\n" 108 109 #define ENABLE_LINE_MAX_LENGTH (25) 110 111 #ifdef ISP2401 112 #define DBG_EXT_CMD_TRACE_PNTS_DUMP BIT(8) 113 #define DBG_EXT_CMD_PUB_CFG_DUMP BIT(9) 114 #define DBG_EXT_CMD_GAC_REG_DUMP BIT(10) 115 #define DBG_EXT_CMD_GAC_ACB_REG_DUMP BIT(11) 116 #define DBG_EXT_CMD_FIFO_DUMP BIT(12) 117 #define DBG_EXT_CMD_QUEUE_DUMP BIT(13) 118 #define DBG_EXT_CMD_DMA_DUMP BIT(14) 119 #define DBG_EXT_CMD_MASK 0xAB0000CD 120 121 #endif 122 /* 123 * TODO:SH_CSS_MAX_SP_THREADS is not the max number of sp threads 124 * future rework should fix this and remove the define MAX_THREAD_NUM 125 */ 126 #define MAX_THREAD_NUM (SH_CSS_MAX_SP_THREADS + SH_CSS_MAX_SP_INTERNAL_THREADS) 127 128 static struct pipe_graph_class { 129 bool do_init; 130 int height; 131 int width; 132 int eff_height; 133 int eff_width; 134 enum atomisp_input_format stream_format; 135 } pg_inst = {true, 0, 0, 0, 0, N_ATOMISP_INPUT_FORMAT}; 136 137 static const char *const queue_id_to_str[] = { 138 /* [SH_CSS_QUEUE_A_ID] =*/ "queue_A", 139 /* [SH_CSS_QUEUE_B_ID] =*/ "queue_B", 140 /* [SH_CSS_QUEUE_C_ID] =*/ "queue_C", 141 /* [SH_CSS_QUEUE_D_ID] =*/ "queue_D", 142 /* [SH_CSS_QUEUE_E_ID] =*/ "queue_E", 143 /* [SH_CSS_QUEUE_F_ID] =*/ "queue_F", 144 /* [SH_CSS_QUEUE_G_ID] =*/ "queue_G", 145 /* [SH_CSS_QUEUE_H_ID] =*/ "queue_H" 146 }; 147 148 static const char *const pipe_id_to_str[] = { 149 /* [IA_CSS_PIPE_ID_PREVIEW] =*/ "preview", 150 /* [IA_CSS_PIPE_ID_COPY] =*/ "copy", 151 /* [IA_CSS_PIPE_ID_VIDEO] =*/ "video", 152 /* [IA_CSS_PIPE_ID_CAPTURE] =*/ "capture", 153 /* [IA_CSS_PIPE_ID_YUVPP] =*/ "yuvpp", 154 /* [IA_CSS_PIPE_ID_ACC] =*/ "accelerator" 155 }; 156 157 static char dot_id_input_bin[SH_CSS_MAX_BINARY_NAME + 10]; 158 static char ring_buffer[200]; 159 160 void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...) 161 { 162 va_list ap; 163 164 va_start(ap, fmt); 165 ia_css_debug_vdtrace(level, fmt, ap); 166 va_end(ap); 167 } 168 169 static void debug_dump_long_array_formatted( 170 const sp_ID_t sp_id, 171 hrt_address stack_sp_addr, 172 unsigned int stack_size) 173 { 174 unsigned int i; 175 u32 val; 176 u32 addr = (uint32_t)stack_sp_addr; 177 u32 stack_size_words = CEIL_DIV(stack_size, sizeof(uint32_t)); 178 179 /* When size is not multiple of four, last word is only relevant for 180 * remaining bytes */ 181 for (i = 0; i < stack_size_words; i++) { 182 val = sp_dmem_load_uint32(sp_id, (hrt_address)addr); 183 if ((i % 8) == 0) 184 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n"); 185 186 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "0x%08x ", val); 187 addr += sizeof(uint32_t); 188 } 189 190 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n"); 191 } 192 193 static void debug_dump_sp_stack_info( 194 const sp_ID_t sp_id) 195 { 196 const struct ia_css_fw_info *fw; 197 unsigned int HIVE_ADDR_sp_threads_stack; 198 unsigned int HIVE_ADDR_sp_threads_stack_size; 199 u32 stack_sizes[MAX_THREAD_NUM]; 200 u32 stack_sp_addr[MAX_THREAD_NUM]; 201 unsigned int i; 202 203 fw = &sh_css_sp_fw; 204 205 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "sp_id(%u) stack info\n", sp_id); 206 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 207 "from objects stack_addr_offset:0x%x stack_size_offset:0x%x\n", 208 fw->info.sp.threads_stack, 209 fw->info.sp.threads_stack_size); 210 211 HIVE_ADDR_sp_threads_stack = fw->info.sp.threads_stack; 212 HIVE_ADDR_sp_threads_stack_size = fw->info.sp.threads_stack_size; 213 214 if (fw->info.sp.threads_stack == 0 || 215 fw->info.sp.threads_stack_size == 0) 216 return; 217 218 (void)HIVE_ADDR_sp_threads_stack; 219 (void)HIVE_ADDR_sp_threads_stack_size; 220 221 sp_dmem_load(sp_id, 222 (unsigned int)sp_address_of(sp_threads_stack), 223 &stack_sp_addr, sizeof(stack_sp_addr)); 224 sp_dmem_load(sp_id, 225 (unsigned int)sp_address_of(sp_threads_stack_size), 226 &stack_sizes, sizeof(stack_sizes)); 227 228 for (i = 0 ; i < MAX_THREAD_NUM; i++) { 229 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 230 "thread: %u stack_addr: 0x%08x stack_size: %u\n", 231 i, stack_sp_addr[i], stack_sizes[i]); 232 debug_dump_long_array_formatted(sp_id, (hrt_address)stack_sp_addr[i], 233 stack_sizes[i]); 234 } 235 } 236 237 void ia_css_debug_dump_sp_stack_info(void) 238 { 239 debug_dump_sp_stack_info(SP0_ID); 240 } 241 242 void ia_css_debug_set_dtrace_level(const unsigned int trace_level) 243 { 244 dbg_level = trace_level; 245 return; 246 } 247 248 unsigned int ia_css_debug_get_dtrace_level(void) 249 { 250 return dbg_level; 251 } 252 253 static const char *debug_stream_format2str(const enum atomisp_input_format 254 stream_format) 255 { 256 switch (stream_format) { 257 case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: 258 return "yuv420-8-legacy"; 259 case ATOMISP_INPUT_FORMAT_YUV420_8: 260 return "yuv420-8"; 261 case ATOMISP_INPUT_FORMAT_YUV420_10: 262 return "yuv420-10"; 263 case ATOMISP_INPUT_FORMAT_YUV420_16: 264 return "yuv420-16"; 265 case ATOMISP_INPUT_FORMAT_YUV422_8: 266 return "yuv422-8"; 267 case ATOMISP_INPUT_FORMAT_YUV422_10: 268 return "yuv422-10"; 269 case ATOMISP_INPUT_FORMAT_YUV422_16: 270 return "yuv422-16"; 271 case ATOMISP_INPUT_FORMAT_RGB_444: 272 return "rgb444"; 273 case ATOMISP_INPUT_FORMAT_RGB_555: 274 return "rgb555"; 275 case ATOMISP_INPUT_FORMAT_RGB_565: 276 return "rgb565"; 277 case ATOMISP_INPUT_FORMAT_RGB_666: 278 return "rgb666"; 279 case ATOMISP_INPUT_FORMAT_RGB_888: 280 return "rgb888"; 281 case ATOMISP_INPUT_FORMAT_RAW_6: 282 return "raw6"; 283 case ATOMISP_INPUT_FORMAT_RAW_7: 284 return "raw7"; 285 case ATOMISP_INPUT_FORMAT_RAW_8: 286 return "raw8"; 287 case ATOMISP_INPUT_FORMAT_RAW_10: 288 return "raw10"; 289 case ATOMISP_INPUT_FORMAT_RAW_12: 290 return "raw12"; 291 case ATOMISP_INPUT_FORMAT_RAW_14: 292 return "raw14"; 293 case ATOMISP_INPUT_FORMAT_RAW_16: 294 return "raw16"; 295 case ATOMISP_INPUT_FORMAT_BINARY_8: 296 return "binary8"; 297 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT1: 298 return "generic-short1"; 299 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT2: 300 return "generic-short2"; 301 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT3: 302 return "generic-short3"; 303 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT4: 304 return "generic-short4"; 305 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT5: 306 return "generic-short5"; 307 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT6: 308 return "generic-short6"; 309 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT7: 310 return "generic-short7"; 311 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT8: 312 return "generic-short8"; 313 case ATOMISP_INPUT_FORMAT_YUV420_8_SHIFT: 314 return "yuv420-8-shift"; 315 case ATOMISP_INPUT_FORMAT_YUV420_10_SHIFT: 316 return "yuv420-10-shift"; 317 case ATOMISP_INPUT_FORMAT_EMBEDDED: 318 return "embedded-8"; 319 case ATOMISP_INPUT_FORMAT_USER_DEF1: 320 return "user-def-8-type-1"; 321 case ATOMISP_INPUT_FORMAT_USER_DEF2: 322 return "user-def-8-type-2"; 323 case ATOMISP_INPUT_FORMAT_USER_DEF3: 324 return "user-def-8-type-3"; 325 case ATOMISP_INPUT_FORMAT_USER_DEF4: 326 return "user-def-8-type-4"; 327 case ATOMISP_INPUT_FORMAT_USER_DEF5: 328 return "user-def-8-type-5"; 329 case ATOMISP_INPUT_FORMAT_USER_DEF6: 330 return "user-def-8-type-6"; 331 case ATOMISP_INPUT_FORMAT_USER_DEF7: 332 return "user-def-8-type-7"; 333 case ATOMISP_INPUT_FORMAT_USER_DEF8: 334 return "user-def-8-type-8"; 335 336 default: 337 assert(!"Unknown stream format"); 338 return "unknown-stream-format"; 339 } 340 }; 341 342 static const char *debug_frame_format2str(const enum ia_css_frame_format 343 frame_format) 344 { 345 switch (frame_format) { 346 case IA_CSS_FRAME_FORMAT_NV11: 347 return "NV11"; 348 case IA_CSS_FRAME_FORMAT_NV12: 349 return "NV12"; 350 case IA_CSS_FRAME_FORMAT_NV12_16: 351 return "NV12_16"; 352 case IA_CSS_FRAME_FORMAT_NV12_TILEY: 353 return "NV12_TILEY"; 354 case IA_CSS_FRAME_FORMAT_NV16: 355 return "NV16"; 356 case IA_CSS_FRAME_FORMAT_NV21: 357 return "NV21"; 358 case IA_CSS_FRAME_FORMAT_NV61: 359 return "NV61"; 360 case IA_CSS_FRAME_FORMAT_YV12: 361 return "YV12"; 362 case IA_CSS_FRAME_FORMAT_YV16: 363 return "YV16"; 364 case IA_CSS_FRAME_FORMAT_YUV420: 365 return "YUV420"; 366 case IA_CSS_FRAME_FORMAT_YUV420_16: 367 return "YUV420_16"; 368 case IA_CSS_FRAME_FORMAT_YUV422: 369 return "YUV422"; 370 case IA_CSS_FRAME_FORMAT_YUV422_16: 371 return "YUV422_16"; 372 case IA_CSS_FRAME_FORMAT_UYVY: 373 return "UYVY"; 374 case IA_CSS_FRAME_FORMAT_YUYV: 375 return "YUYV"; 376 case IA_CSS_FRAME_FORMAT_YUV444: 377 return "YUV444"; 378 case IA_CSS_FRAME_FORMAT_YUV_LINE: 379 return "YUV_LINE"; 380 case IA_CSS_FRAME_FORMAT_RAW: 381 return "RAW"; 382 case IA_CSS_FRAME_FORMAT_RGB565: 383 return "RGB565"; 384 case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: 385 return "PLANAR_RGB888"; 386 case IA_CSS_FRAME_FORMAT_RGBA888: 387 return "RGBA888"; 388 case IA_CSS_FRAME_FORMAT_QPLANE6: 389 return "QPLANE6"; 390 case IA_CSS_FRAME_FORMAT_BINARY_8: 391 return "BINARY_8"; 392 case IA_CSS_FRAME_FORMAT_MIPI: 393 return "MIPI"; 394 case IA_CSS_FRAME_FORMAT_RAW_PACKED: 395 return "RAW_PACKED"; 396 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: 397 return "CSI_MIPI_YUV420_8"; 398 case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: 399 return "CSI_MIPI_LEGACY_YUV420_8"; 400 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10: 401 return "CSI_MIPI_YUV420_10"; 402 403 default: 404 assert(!"Unknown frame format"); 405 return "unknown-frame-format"; 406 } 407 } 408 409 static void debug_print_sp_state(const sp_state_t *state, const char *cell) 410 { 411 assert(cell); 412 assert(state); 413 414 ia_css_debug_dtrace(2, "%s state:\n", cell); 415 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc); 416 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register", 417 state->status_register); 418 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken); 419 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle); 420 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping", 421 state->is_sleeping); 422 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling", 423 state->is_stalling); 424 return; 425 } 426 427 static void debug_print_isp_state(const isp_state_t *state, const char *cell) 428 { 429 assert(state); 430 assert(cell); 431 432 ia_css_debug_dtrace(2, "%s state:\n", cell); 433 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc); 434 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register", 435 state->status_register); 436 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken); 437 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle); 438 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping", 439 state->is_sleeping); 440 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling", 441 state->is_stalling); 442 return; 443 } 444 445 void ia_css_debug_dump_isp_state(void) 446 { 447 isp_state_t state; 448 isp_stall_t stall; 449 450 isp_get_state(ISP0_ID, &state, &stall); 451 452 debug_print_isp_state(&state, "ISP"); 453 454 if (state.is_stalling) { 455 #if !defined(HAS_NO_INPUT_FORMATTER) 456 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 457 "[0] if_prim_a_FIFO stalled", stall.fifo0); 458 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 459 "[1] if_prim_b_FIFO stalled", stall.fifo1); 460 #endif 461 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[2] dma_FIFO stalled", 462 stall.fifo2); 463 #if defined(HAS_ISP_2400_MAMOIADA) || defined(HAS_ISP_2401_MAMOIADA) || defined(IS_ISP_2500_SYSTEM) 464 465 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[3] gdc0_FIFO stalled", 466 stall.fifo3); 467 #if !defined(IS_ISP_2500_SYSTEM) 468 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[4] gdc1_FIFO stalled", 469 stall.fifo4); 470 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[5] gpio_FIFO stalled", 471 stall.fifo5); 472 #endif 473 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[6] sp_FIFO stalled", 474 stall.fifo6); 475 #else 476 #error "ia_css_debug: ISP cell must be one of {2400_MAMOIADA,, 2401_MAMOIADA, 2500_SKYCAM}" 477 #endif 478 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 479 "status & control stalled", 480 stall.stat_ctrl); 481 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled", 482 stall.dmem); 483 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vmem stalled", 484 stall.vmem); 485 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem1 stalled", 486 stall.vamem1); 487 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem2 stalled", 488 stall.vamem2); 489 #if defined(HAS_ISP_2400_MAMOIADA) || defined(HAS_ISP_2401_MAMOIADA) 490 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem3 stalled", 491 stall.vamem3); 492 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "hmem stalled", 493 stall.hmem); 494 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "pmem stalled", 495 stall.pmem); 496 #endif 497 } 498 return; 499 } 500 501 void ia_css_debug_dump_sp_state(void) 502 { 503 sp_state_t state; 504 sp_stall_t stall; 505 506 sp_get_state(SP0_ID, &state, &stall); 507 debug_print_sp_state(&state, "SP"); 508 if (state.is_stalling) { 509 #if defined(HAS_SP_2400) || defined(IS_ISP_2500_SYSTEM) 510 #if !defined(HAS_NO_INPUT_SYSTEM) 511 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isys_FIFO stalled", 512 stall.fifo0); 513 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "if_sec_FIFO stalled", 514 stall.fifo1); 515 #endif 516 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 517 "str_to_mem_FIFO stalled", stall.fifo2); 518 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dma_FIFO stalled", 519 stall.fifo3); 520 #if !defined(HAS_NO_INPUT_FORMATTER) 521 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 522 "if_prim_a_FIFO stalled", stall.fifo4); 523 #endif 524 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isp_FIFO stalled", 525 stall.fifo5); 526 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gp_FIFO stalled", 527 stall.fifo6); 528 #if !defined(HAS_NO_INPUT_FORMATTER) 529 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 530 "if_prim_b_FIFO stalled", stall.fifo7); 531 #endif 532 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc0_FIFO stalled", 533 stall.fifo8); 534 #if !defined(IS_ISP_2500_SYSTEM) 535 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc1_FIFO stalled", 536 stall.fifo9); 537 #endif 538 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "irq FIFO stalled", 539 stall.fifoa); 540 #else 541 #error "ia_css_debug: SP cell must be one of {SP2400, SP2500}" 542 #endif 543 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled", 544 stall.dmem); 545 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 546 "control master stalled", 547 stall.control_master); 548 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 549 "i-cache master stalled", 550 stall.icache_master); 551 } 552 ia_css_debug_dump_trace(); 553 return; 554 } 555 556 static void debug_print_fifo_channel_state(const fifo_channel_state_t *state, 557 const char *descr) 558 { 559 assert(state); 560 assert(descr); 561 562 ia_css_debug_dtrace(2, "FIFO channel: %s\n", descr); 563 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "source valid", 564 state->src_valid); 565 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo accept", 566 state->fifo_accept); 567 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo valid", 568 state->fifo_valid); 569 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "sink accept", 570 state->sink_accept); 571 return; 572 } 573 574 #if !defined(HAS_NO_INPUT_FORMATTER) && defined(USE_INPUT_SYSTEM_VERSION_2) 575 void ia_css_debug_dump_pif_a_isp_fifo_state(void) 576 { 577 fifo_channel_state_t pif_to_isp, isp_to_pif; 578 579 fifo_channel_get_state(FIFO_MONITOR0_ID, 580 FIFO_CHANNEL_IF0_TO_ISP0, &pif_to_isp); 581 fifo_channel_get_state(FIFO_MONITOR0_ID, 582 FIFO_CHANNEL_ISP0_TO_IF0, &isp_to_pif); 583 debug_print_fifo_channel_state(&pif_to_isp, "Primary IF A to ISP"); 584 debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF A"); 585 } 586 587 void ia_css_debug_dump_pif_b_isp_fifo_state(void) 588 { 589 fifo_channel_state_t pif_to_isp, isp_to_pif; 590 591 fifo_channel_get_state(FIFO_MONITOR0_ID, 592 FIFO_CHANNEL_IF1_TO_ISP0, &pif_to_isp); 593 fifo_channel_get_state(FIFO_MONITOR0_ID, 594 FIFO_CHANNEL_ISP0_TO_IF1, &isp_to_pif); 595 debug_print_fifo_channel_state(&pif_to_isp, "Primary IF B to ISP"); 596 debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF B"); 597 } 598 599 void ia_css_debug_dump_str2mem_sp_fifo_state(void) 600 { 601 fifo_channel_state_t s2m_to_sp, sp_to_s2m; 602 603 fifo_channel_get_state(FIFO_MONITOR0_ID, 604 FIFO_CHANNEL_STREAM2MEM0_TO_SP0, &s2m_to_sp); 605 fifo_channel_get_state(FIFO_MONITOR0_ID, 606 FIFO_CHANNEL_SP0_TO_STREAM2MEM0, &sp_to_s2m); 607 debug_print_fifo_channel_state(&s2m_to_sp, "Stream-to-memory to SP"); 608 debug_print_fifo_channel_state(&sp_to_s2m, "SP to stream-to-memory"); 609 } 610 611 static void debug_print_if_state(input_formatter_state_t *state, const char *id) 612 { 613 unsigned int val; 614 615 #if defined(HAS_INPUT_FORMATTER_VERSION_1) 616 const char *st_reset = (state->reset ? "Active" : "Not active"); 617 #endif 618 const char *st_vsync_active_low = 619 (state->vsync_active_low ? "low" : "high"); 620 const char *st_hsync_active_low = 621 (state->hsync_active_low ? "low" : "high"); 622 623 const char *fsm_sync_status_str = "unknown"; 624 const char *fsm_crop_status_str = "unknown"; 625 const char *fsm_padding_status_str = "unknown"; 626 627 int st_stline = state->start_line; 628 int st_stcol = state->start_column; 629 int st_crpht = state->cropped_height; 630 int st_crpwd = state->cropped_width; 631 int st_verdcm = state->ver_decimation; 632 int st_hordcm = state->hor_decimation; 633 int st_ver_deinterleaving = state->ver_deinterleaving; 634 int st_hor_deinterleaving = state->hor_deinterleaving; 635 int st_leftpd = state->left_padding; 636 int st_eoloff = state->eol_offset; 637 int st_vmstartaddr = state->vmem_start_address; 638 int st_vmendaddr = state->vmem_end_address; 639 int st_vmincr = state->vmem_increment; 640 int st_yuv420 = state->is_yuv420; 641 int st_allow_fifo_overflow = state->allow_fifo_overflow; 642 int st_block_fifo_when_no_req = state->block_fifo_when_no_req; 643 644 assert(state); 645 ia_css_debug_dtrace(2, "InputFormatter State (%s):\n", id); 646 647 ia_css_debug_dtrace(2, "\tConfiguration:\n"); 648 649 #if defined(HAS_INPUT_FORMATTER_VERSION_1) 650 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "Software reset", st_reset); 651 #endif 652 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start line", st_stline); 653 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start column", st_stcol); 654 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped height", st_crpht); 655 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped width", st_crpwd); 656 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Ver decimation", st_verdcm); 657 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Hor decimation", st_hordcm); 658 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 659 "Ver deinterleaving", st_ver_deinterleaving); 660 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 661 "Hor deinterleaving", st_hor_deinterleaving); 662 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Left padding", st_leftpd); 663 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 664 "EOL offset (bytes)", st_eoloff); 665 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", 666 "VMEM start address", st_vmstartaddr); 667 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", 668 "VMEM end address", st_vmendaddr); 669 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", 670 "VMEM increment", st_vmincr); 671 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "YUV 420 format", st_yuv420); 672 ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n", 673 "Vsync", st_vsync_active_low); 674 ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n", 675 "Hsync", st_hsync_active_low); 676 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 677 "Allow FIFO overflow", st_allow_fifo_overflow); 678 /* Flag that tells whether the IF gives backpressure on frames */ 679 /* 680 * FYI, this is only on the frame request (indicate), when the IF has 681 * synch'd on a frame it will always give back pressure 682 */ 683 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 684 "Block when no request", st_block_fifo_when_no_req); 685 686 #if defined(HAS_INPUT_FORMATTER_VERSION_2) 687 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 688 "IF_BLOCKED_FIFO_NO_REQ_ADDRESS", 689 input_formatter_reg_load(INPUT_FORMATTER0_ID, 690 HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS) 691 ); 692 693 ia_css_debug_dtrace(2, "\t%-32s:\n", "InputSwitch State"); 694 695 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 696 "_REG_GP_IFMT_input_switch_lut_reg0", 697 gp_device_reg_load(GP_DEVICE0_ID, 698 _REG_GP_IFMT_input_switch_lut_reg0)); 699 700 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 701 "_REG_GP_IFMT_input_switch_lut_reg1", 702 gp_device_reg_load(GP_DEVICE0_ID, 703 _REG_GP_IFMT_input_switch_lut_reg1)); 704 705 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 706 "_REG_GP_IFMT_input_switch_lut_reg2", 707 gp_device_reg_load(GP_DEVICE0_ID, 708 _REG_GP_IFMT_input_switch_lut_reg2)); 709 710 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 711 "_REG_GP_IFMT_input_switch_lut_reg3", 712 gp_device_reg_load(GP_DEVICE0_ID, 713 _REG_GP_IFMT_input_switch_lut_reg3)); 714 715 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 716 "_REG_GP_IFMT_input_switch_lut_reg4", 717 gp_device_reg_load(GP_DEVICE0_ID, 718 _REG_GP_IFMT_input_switch_lut_reg4)); 719 720 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 721 "_REG_GP_IFMT_input_switch_lut_reg5", 722 gp_device_reg_load(GP_DEVICE0_ID, 723 _REG_GP_IFMT_input_switch_lut_reg5)); 724 725 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 726 "_REG_GP_IFMT_input_switch_lut_reg6", 727 gp_device_reg_load(GP_DEVICE0_ID, 728 _REG_GP_IFMT_input_switch_lut_reg6)); 729 730 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 731 "_REG_GP_IFMT_input_switch_lut_reg7", 732 gp_device_reg_load(GP_DEVICE0_ID, 733 _REG_GP_IFMT_input_switch_lut_reg7)); 734 735 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 736 "_REG_GP_IFMT_input_switch_fsync_lut", 737 gp_device_reg_load(GP_DEVICE0_ID, 738 _REG_GP_IFMT_input_switch_fsync_lut)); 739 740 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 741 "_REG_GP_IFMT_srst", 742 gp_device_reg_load(GP_DEVICE0_ID, 743 _REG_GP_IFMT_srst)); 744 745 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 746 "_REG_GP_IFMT_slv_reg_srst", 747 gp_device_reg_load(GP_DEVICE0_ID, 748 _REG_GP_IFMT_slv_reg_srst)); 749 #endif 750 751 ia_css_debug_dtrace(2, "\tFSM Status:\n"); 752 753 val = state->fsm_sync_status; 754 755 if (val > 7) 756 fsm_sync_status_str = "ERROR"; 757 758 switch (val & 0x7) { 759 case 0: 760 fsm_sync_status_str = "idle"; 761 break; 762 case 1: 763 fsm_sync_status_str = "request frame"; 764 break; 765 case 2: 766 fsm_sync_status_str = "request lines"; 767 break; 768 case 3: 769 fsm_sync_status_str = "request vectors"; 770 break; 771 case 4: 772 fsm_sync_status_str = "send acknowledge"; 773 break; 774 default: 775 fsm_sync_status_str = "unknown"; 776 break; 777 } 778 779 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", 780 "FSM Synchronization Status", val, 781 fsm_sync_status_str); 782 783 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 784 "FSM Synchronization Counter", 785 state->fsm_sync_counter); 786 787 val = state->fsm_crop_status; 788 789 if (val > 7) 790 fsm_crop_status_str = "ERROR"; 791 792 switch (val & 0x7) { 793 case 0: 794 fsm_crop_status_str = "idle"; 795 break; 796 case 1: 797 fsm_crop_status_str = "wait line"; 798 break; 799 case 2: 800 fsm_crop_status_str = "crop line"; 801 break; 802 case 3: 803 fsm_crop_status_str = "crop pixel"; 804 break; 805 case 4: 806 fsm_crop_status_str = "pass pixel"; 807 break; 808 case 5: 809 fsm_crop_status_str = "pass line"; 810 break; 811 case 6: 812 fsm_crop_status_str = "lost line"; 813 break; 814 default: 815 fsm_crop_status_str = "unknown"; 816 break; 817 } 818 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", 819 "FSM Crop Status", val, fsm_crop_status_str); 820 821 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 822 "FSM Crop Line Counter", 823 state->fsm_crop_line_counter); 824 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 825 "FSM Crop Pixel Counter", 826 state->fsm_crop_pixel_counter); 827 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 828 "FSM Deinterleaving idx buffer", 829 state->fsm_deinterleaving_index); 830 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 831 "FSM H decimation counter", 832 state->fsm_dec_h_counter); 833 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 834 "FSM V decimation counter", 835 state->fsm_dec_v_counter); 836 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 837 "FSM block V decimation counter", 838 state->fsm_dec_block_v_counter); 839 840 val = state->fsm_padding_status; 841 842 if (val > 7) 843 fsm_padding_status_str = "ERROR"; 844 845 switch (val & 0x7) { 846 case 0: 847 fsm_padding_status_str = "idle"; 848 break; 849 case 1: 850 fsm_padding_status_str = "left pad"; 851 break; 852 case 2: 853 fsm_padding_status_str = "write"; 854 break; 855 case 3: 856 fsm_padding_status_str = "right pad"; 857 break; 858 case 4: 859 fsm_padding_status_str = "send end of line"; 860 break; 861 default: 862 fsm_padding_status_str = "unknown"; 863 break; 864 } 865 866 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", "FSM Padding Status", 867 val, fsm_padding_status_str); 868 869 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 870 "FSM Padding element idx counter", 871 state->fsm_padding_elem_counter); 872 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support error", 873 state->fsm_vector_support_error); 874 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support buf full", 875 state->fsm_vector_buffer_full); 876 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support", 877 state->vector_support); 878 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Fifo sensor data lost", 879 state->sensor_data_lost); 880 return; 881 } 882 883 static void debug_print_if_bin_state(input_formatter_bin_state_t *state) 884 { 885 ia_css_debug_dtrace(2, "Stream-to-memory state:\n"); 886 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "reset", state->reset); 887 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "input endianness", 888 state->input_endianness); 889 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "output endianness", 890 state->output_endianness); 891 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "bitswap", state->bitswap); 892 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "block_synch", 893 state->block_synch); 894 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "packet_synch", 895 state->packet_synch); 896 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "readpostwrite_sync", 897 state->readpostwrite_synch); 898 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "is_2ppc", state->is_2ppc); 899 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "en_status_update", 900 state->en_status_update); 901 } 902 903 void ia_css_debug_dump_if_state(void) 904 { 905 input_formatter_state_t if_state; 906 input_formatter_bin_state_t if_bin_state; 907 908 input_formatter_get_state(INPUT_FORMATTER0_ID, &if_state); 909 debug_print_if_state(&if_state, "Primary IF A"); 910 ia_css_debug_dump_pif_a_isp_fifo_state(); 911 912 input_formatter_get_state(INPUT_FORMATTER1_ID, &if_state); 913 debug_print_if_state(&if_state, "Primary IF B"); 914 ia_css_debug_dump_pif_b_isp_fifo_state(); 915 916 input_formatter_bin_get_state(INPUT_FORMATTER3_ID, &if_bin_state); 917 debug_print_if_bin_state(&if_bin_state); 918 ia_css_debug_dump_str2mem_sp_fifo_state(); 919 } 920 #endif 921 922 void ia_css_debug_dump_dma_state(void) 923 { 924 /* note: the var below is made static as it is quite large; 925 if it is not static it ends up on the stack which could 926 cause issues for drivers 927 */ 928 static dma_state_t state; 929 int i, ch_id; 930 931 const char *fsm_cmd_st_lbl = "FSM Command flag state"; 932 const char *fsm_ctl_st_lbl = "FSM Control flag state"; 933 const char *fsm_ctl_state = NULL; 934 const char *fsm_ctl_flag = NULL; 935 const char *fsm_pack_st = NULL; 936 const char *fsm_read_st = NULL; 937 const char *fsm_write_st = NULL; 938 char last_cmd_str[64]; 939 940 dma_get_state(DMA0_ID, &state); 941 /* Print header for DMA dump status */ 942 ia_css_debug_dtrace(2, "DMA dump status:\n"); 943 944 /* Print FSM command flag state */ 945 if (state.fsm_command_idle) 946 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "IDLE"); 947 if (state.fsm_command_run) 948 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "RUN"); 949 if (state.fsm_command_stalling) 950 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, 951 "STALL"); 952 if (state.fsm_command_error) 953 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, 954 "ERROR"); 955 956 /* Print last command along with the channel */ 957 ch_id = state.last_command_channel; 958 959 switch (state.last_command) { 960 case DMA_COMMAND_READ: 961 snprintf(last_cmd_str, 64, 962 "Read 2D Block [Channel: %d]", ch_id); 963 break; 964 case DMA_COMMAND_WRITE: 965 snprintf(last_cmd_str, 64, 966 "Write 2D Block [Channel: %d]", ch_id); 967 break; 968 case DMA_COMMAND_SET_CHANNEL: 969 snprintf(last_cmd_str, 64, "Set Channel [Channel: %d]", ch_id); 970 break; 971 case DMA_COMMAND_SET_PARAM: 972 snprintf(last_cmd_str, 64, 973 "Set Param: %d [Channel: %d]", 974 state.last_command_param, ch_id); 975 break; 976 case DMA_COMMAND_READ_SPECIFIC: 977 snprintf(last_cmd_str, 64, 978 "Read Specific 2D Block [Channel: %d]", ch_id); 979 break; 980 case DMA_COMMAND_WRITE_SPECIFIC: 981 snprintf(last_cmd_str, 64, 982 "Write Specific 2D Block [Channel: %d]", ch_id); 983 break; 984 case DMA_COMMAND_INIT: 985 snprintf(last_cmd_str, 64, 986 "Init 2D Block on Device A [Channel: %d]", ch_id); 987 break; 988 case DMA_COMMAND_INIT_SPECIFIC: 989 snprintf(last_cmd_str, 64, 990 "Init Specific 2D Block [Channel: %d]", ch_id); 991 break; 992 case DMA_COMMAND_RST: 993 snprintf(last_cmd_str, 64, "DMA SW Reset"); 994 break; 995 case N_DMA_COMMANDS: 996 snprintf(last_cmd_str, 64, "UNKNOWN"); 997 break; 998 default: 999 snprintf(last_cmd_str, 64, 1000 "unknown [Channel: %d]", ch_id); 1001 break; 1002 } 1003 ia_css_debug_dtrace(2, "\t%-32s: (0x%X : %s)\n", 1004 "last command received", state.last_command, 1005 last_cmd_str); 1006 1007 /* Print DMA registers */ 1008 ia_css_debug_dtrace(2, "\t%-32s\n", 1009 "DMA registers, connection group 0"); 1010 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Command", 1011 state.current_command); 1012 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address A", 1013 state.current_addr_a); 1014 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address B", 1015 state.current_addr_b); 1016 1017 if (state.fsm_ctrl_idle) 1018 fsm_ctl_flag = "IDLE"; 1019 else if (state.fsm_ctrl_run) 1020 fsm_ctl_flag = "RUN"; 1021 else if (state.fsm_ctrl_stalling) 1022 fsm_ctl_flag = "STAL"; 1023 else if (state.fsm_ctrl_error) 1024 fsm_ctl_flag = "ERROR"; 1025 else 1026 fsm_ctl_flag = "UNKNOWN"; 1027 1028 switch (state.fsm_ctrl_state) { 1029 case DMA_CTRL_STATE_IDLE: 1030 fsm_ctl_state = "Idle state"; 1031 break; 1032 case DMA_CTRL_STATE_REQ_RCV: 1033 fsm_ctl_state = "Req Rcv state"; 1034 break; 1035 case DMA_CTRL_STATE_RCV: 1036 fsm_ctl_state = "Rcv state"; 1037 break; 1038 case DMA_CTRL_STATE_RCV_REQ: 1039 fsm_ctl_state = "Rcv Req state"; 1040 break; 1041 case DMA_CTRL_STATE_INIT: 1042 fsm_ctl_state = "Init state"; 1043 break; 1044 case N_DMA_CTRL_STATES: 1045 fsm_ctl_state = "Unknown"; 1046 break; 1047 } 1048 1049 ia_css_debug_dtrace(2, "\t\t%-32s: %s -> %s\n", fsm_ctl_st_lbl, 1050 fsm_ctl_flag, fsm_ctl_state); 1051 1052 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source dev", 1053 state.fsm_ctrl_source_dev); 1054 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source addr", 1055 state.fsm_ctrl_source_addr); 1056 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source stride", 1057 state.fsm_ctrl_source_stride); 1058 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source width", 1059 state.fsm_ctrl_source_width); 1060 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source height", 1061 state.fsm_ctrl_source_height); 1062 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source dev", 1063 state.fsm_ctrl_pack_source_dev); 1064 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest dev", 1065 state.fsm_ctrl_pack_dest_dev); 1066 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest addr", 1067 state.fsm_ctrl_dest_addr); 1068 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest stride", 1069 state.fsm_ctrl_dest_stride); 1070 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source width", 1071 state.fsm_ctrl_pack_source_width); 1072 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest height", 1073 state.fsm_ctrl_pack_dest_height); 1074 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest width", 1075 state.fsm_ctrl_pack_dest_width); 1076 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source elems", 1077 state.fsm_ctrl_pack_source_elems); 1078 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest elems", 1079 state.fsm_ctrl_pack_dest_elems); 1080 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack extension", 1081 state.fsm_ctrl_pack_extension); 1082 1083 if (state.pack_idle) 1084 fsm_pack_st = "IDLE"; 1085 if (state.pack_run) 1086 fsm_pack_st = "RUN"; 1087 if (state.pack_stalling) 1088 fsm_pack_st = "STALL"; 1089 if (state.pack_error) 1090 fsm_pack_st = "ERROR"; 1091 1092 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Pack flag state", 1093 fsm_pack_st); 1094 1095 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack cnt height", 1096 state.pack_cnt_height); 1097 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack src cnt width", 1098 state.pack_src_cnt_width); 1099 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack dest cnt width", 1100 state.pack_dest_cnt_width); 1101 1102 if (state.read_state == DMA_RW_STATE_IDLE) 1103 fsm_read_st = "Idle state"; 1104 if (state.read_state == DMA_RW_STATE_REQ) 1105 fsm_read_st = "Req state"; 1106 if (state.read_state == DMA_RW_STATE_NEXT_LINE) 1107 fsm_read_st = "Next line"; 1108 if (state.read_state == DMA_RW_STATE_UNLOCK_CHANNEL) 1109 fsm_read_st = "Unlock channel"; 1110 1111 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Read state", 1112 fsm_read_st); 1113 1114 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt height", 1115 state.read_cnt_height); 1116 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt width", 1117 state.read_cnt_width); 1118 1119 if (state.write_state == DMA_RW_STATE_IDLE) 1120 fsm_write_st = "Idle state"; 1121 if (state.write_state == DMA_RW_STATE_REQ) 1122 fsm_write_st = "Req state"; 1123 if (state.write_state == DMA_RW_STATE_NEXT_LINE) 1124 fsm_write_st = "Next line"; 1125 if (state.write_state == DMA_RW_STATE_UNLOCK_CHANNEL) 1126 fsm_write_st = "Unlock channel"; 1127 1128 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Write state", 1129 fsm_write_st); 1130 1131 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write height", 1132 state.write_height); 1133 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write width", 1134 state.write_width); 1135 1136 for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) { 1137 dma_port_state_t *port = &state.port_states[i]; 1138 1139 ia_css_debug_dtrace(2, "\tDMA device interface %d\n", i); 1140 ia_css_debug_dtrace(2, "\t\tDMA internal side state\n"); 1141 ia_css_debug_dtrace(2, 1142 "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n", 1143 port->req_cs, port->req_we_n, port->req_run, 1144 port->req_ack); 1145 ia_css_debug_dtrace(2, "\t\tMaster Output side state\n"); 1146 ia_css_debug_dtrace(2, 1147 "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n", 1148 port->send_cs, port->send_we_n, 1149 port->send_run, port->send_ack); 1150 ia_css_debug_dtrace(2, "\t\tFifo state\n"); 1151 if (port->fifo_state == DMA_FIFO_STATE_WILL_BE_FULL) 1152 ia_css_debug_dtrace(2, "\t\t\tFiFo will be full\n"); 1153 else if (port->fifo_state == DMA_FIFO_STATE_FULL) 1154 ia_css_debug_dtrace(2, "\t\t\tFifo Full\n"); 1155 else if (port->fifo_state == DMA_FIFO_STATE_EMPTY) 1156 ia_css_debug_dtrace(2, "\t\t\tFifo Empty\n"); 1157 else 1158 ia_css_debug_dtrace(2, "\t\t\tFifo state unknown\n"); 1159 1160 ia_css_debug_dtrace(2, "\t\tFifo counter %d\n\n", 1161 port->fifo_counter); 1162 } 1163 1164 for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) { 1165 dma_channel_state_t *ch = &state.channel_states[i]; 1166 1167 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "DMA channel register", 1168 i); 1169 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Connection", 1170 ch->connection); 1171 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Sign extend", 1172 ch->sign_extend); 1173 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev A", 1174 ch->stride_a); 1175 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev A", 1176 ch->elems_a); 1177 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev A", 1178 ch->cropping_a); 1179 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev A", 1180 ch->width_a); 1181 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev B", 1182 ch->stride_b); 1183 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev B", 1184 ch->elems_b); 1185 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev B", 1186 ch->cropping_b); 1187 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev B", 1188 ch->width_b); 1189 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Height", ch->height); 1190 } 1191 ia_css_debug_dtrace(2, "\n"); 1192 return; 1193 } 1194 1195 void ia_css_debug_dump_dma_sp_fifo_state(void) 1196 { 1197 fifo_channel_state_t dma_to_sp, sp_to_dma; 1198 1199 fifo_channel_get_state(FIFO_MONITOR0_ID, 1200 FIFO_CHANNEL_DMA0_TO_SP0, &dma_to_sp); 1201 fifo_channel_get_state(FIFO_MONITOR0_ID, 1202 FIFO_CHANNEL_SP0_TO_DMA0, &sp_to_dma); 1203 debug_print_fifo_channel_state(&dma_to_sp, "DMA to SP"); 1204 debug_print_fifo_channel_state(&sp_to_dma, "SP to DMA"); 1205 return; 1206 } 1207 1208 void ia_css_debug_dump_dma_isp_fifo_state(void) 1209 { 1210 fifo_channel_state_t dma_to_isp, isp_to_dma; 1211 1212 fifo_channel_get_state(FIFO_MONITOR0_ID, 1213 FIFO_CHANNEL_DMA0_TO_ISP0, &dma_to_isp); 1214 fifo_channel_get_state(FIFO_MONITOR0_ID, 1215 FIFO_CHANNEL_ISP0_TO_DMA0, &isp_to_dma); 1216 debug_print_fifo_channel_state(&dma_to_isp, "DMA to ISP"); 1217 debug_print_fifo_channel_state(&isp_to_dma, "ISP to DMA"); 1218 return; 1219 } 1220 1221 void ia_css_debug_dump_isp_sp_fifo_state(void) 1222 { 1223 fifo_channel_state_t sp_to_isp, isp_to_sp; 1224 1225 fifo_channel_get_state(FIFO_MONITOR0_ID, 1226 FIFO_CHANNEL_SP0_TO_ISP0, &sp_to_isp); 1227 fifo_channel_get_state(FIFO_MONITOR0_ID, 1228 FIFO_CHANNEL_ISP0_TO_SP0, &isp_to_sp); 1229 debug_print_fifo_channel_state(&sp_to_isp, "SP to ISP"); 1230 debug_print_fifo_channel_state(&isp_to_sp, "ISP to SP"); 1231 return; 1232 } 1233 1234 void ia_css_debug_dump_isp_gdc_fifo_state(void) 1235 { 1236 fifo_channel_state_t gdc_to_isp, isp_to_gdc; 1237 1238 fifo_channel_get_state(FIFO_MONITOR0_ID, 1239 FIFO_CHANNEL_GDC0_TO_ISP0, &gdc_to_isp); 1240 fifo_channel_get_state(FIFO_MONITOR0_ID, 1241 FIFO_CHANNEL_ISP0_TO_GDC0, &isp_to_gdc); 1242 debug_print_fifo_channel_state(&gdc_to_isp, "GDC to ISP"); 1243 debug_print_fifo_channel_state(&isp_to_gdc, "ISP to GDC"); 1244 return; 1245 } 1246 1247 void ia_css_debug_dump_all_fifo_state(void) 1248 { 1249 int i; 1250 fifo_monitor_state_t state; 1251 1252 fifo_monitor_get_state(FIFO_MONITOR0_ID, &state); 1253 1254 for (i = 0; i < N_FIFO_CHANNEL; i++) 1255 debug_print_fifo_channel_state(&state.fifo_channels[i], 1256 "squepfstqkt"); 1257 return; 1258 } 1259 1260 static void debug_binary_info_print(const struct ia_css_binary_xinfo *info) 1261 { 1262 assert(info); 1263 ia_css_debug_dtrace(2, "id = %d\n", info->sp.id); 1264 ia_css_debug_dtrace(2, "mode = %d\n", info->sp.pipeline.mode); 1265 ia_css_debug_dtrace(2, "max_input_width = %d\n", info->sp.input.max_width); 1266 ia_css_debug_dtrace(2, "min_output_width = %d\n", 1267 info->sp.output.min_width); 1268 ia_css_debug_dtrace(2, "max_output_width = %d\n", 1269 info->sp.output.max_width); 1270 ia_css_debug_dtrace(2, "top_cropping = %d\n", info->sp.pipeline.top_cropping); 1271 ia_css_debug_dtrace(2, "left_cropping = %d\n", info->sp.pipeline.left_cropping); 1272 ia_css_debug_dtrace(2, "xmem_addr = %d\n", info->xmem_addr); 1273 ia_css_debug_dtrace(2, "enable_vf_veceven = %d\n", 1274 info->sp.enable.vf_veceven); 1275 ia_css_debug_dtrace(2, "enable_dis = %d\n", info->sp.enable.dis); 1276 ia_css_debug_dtrace(2, "enable_uds = %d\n", info->sp.enable.uds); 1277 ia_css_debug_dtrace(2, "enable ds = %d\n", info->sp.enable.ds); 1278 ia_css_debug_dtrace(2, "s3atbl_use_dmem = %d\n", info->sp.s3a.s3atbl_use_dmem); 1279 return; 1280 } 1281 1282 void ia_css_debug_binary_print(const struct ia_css_binary *bi) 1283 { 1284 unsigned int i; 1285 1286 debug_binary_info_print(bi->info); 1287 ia_css_debug_dtrace(2, 1288 "input: %dx%d, format = %d, padded width = %d\n", 1289 bi->in_frame_info.res.width, 1290 bi->in_frame_info.res.height, 1291 bi->in_frame_info.format, 1292 bi->in_frame_info.padded_width); 1293 ia_css_debug_dtrace(2, 1294 "internal :%dx%d, format = %d, padded width = %d\n", 1295 bi->internal_frame_info.res.width, 1296 bi->internal_frame_info.res.height, 1297 bi->internal_frame_info.format, 1298 bi->internal_frame_info.padded_width); 1299 for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { 1300 if (bi->out_frame_info[i].res.width != 0) { 1301 ia_css_debug_dtrace(2, 1302 "out%d: %dx%d, format = %d, padded width = %d\n", 1303 i, 1304 bi->out_frame_info[i].res.width, 1305 bi->out_frame_info[i].res.height, 1306 bi->out_frame_info[i].format, 1307 bi->out_frame_info[i].padded_width); 1308 } 1309 } 1310 ia_css_debug_dtrace(2, 1311 "vf out: %dx%d, format = %d, padded width = %d\n", 1312 bi->vf_frame_info.res.width, 1313 bi->vf_frame_info.res.height, 1314 bi->vf_frame_info.format, 1315 bi->vf_frame_info.padded_width); 1316 ia_css_debug_dtrace(2, "online = %d\n", bi->online); 1317 ia_css_debug_dtrace(2, "input_buf_vectors = %d\n", 1318 bi->input_buf_vectors); 1319 ia_css_debug_dtrace(2, "deci_factor_log2 = %d\n", bi->deci_factor_log2); 1320 ia_css_debug_dtrace(2, "vf_downscale_log2 = %d\n", 1321 bi->vf_downscale_log2); 1322 ia_css_debug_dtrace(2, "dis_deci_factor_log2 = %d\n", 1323 bi->dis.deci_factor_log2); 1324 ia_css_debug_dtrace(2, "dis hor coef num = %d\n", 1325 bi->dis.coef.pad.width); 1326 ia_css_debug_dtrace(2, "dis ver coef num = %d\n", 1327 bi->dis.coef.pad.height); 1328 ia_css_debug_dtrace(2, "dis hor proj num = %d\n", 1329 bi->dis.proj.pad.height); 1330 ia_css_debug_dtrace(2, "sctbl_width_per_color = %d\n", 1331 bi->sctbl_width_per_color); 1332 ia_css_debug_dtrace(2, "s3atbl_width = %d\n", bi->s3atbl_width); 1333 ia_css_debug_dtrace(2, "s3atbl_height = %d\n", bi->s3atbl_height); 1334 return; 1335 } 1336 1337 void ia_css_debug_frame_print(const struct ia_css_frame *frame, 1338 const char *descr) 1339 { 1340 char *data = NULL; 1341 1342 assert(frame); 1343 assert(descr); 1344 1345 data = (char *)HOST_ADDRESS(frame->data); 1346 ia_css_debug_dtrace(2, "frame %s (%p):\n", descr, frame); 1347 ia_css_debug_dtrace(2, " resolution = %dx%d\n", 1348 frame->info.res.width, frame->info.res.height); 1349 ia_css_debug_dtrace(2, " padded width = %d\n", 1350 frame->info.padded_width); 1351 ia_css_debug_dtrace(2, " format = %d\n", frame->info.format); 1352 ia_css_debug_dtrace(2, " is contiguous = %s\n", 1353 frame->contiguous ? "yes" : "no"); 1354 switch (frame->info.format) { 1355 case IA_CSS_FRAME_FORMAT_NV12: 1356 case IA_CSS_FRAME_FORMAT_NV16: 1357 case IA_CSS_FRAME_FORMAT_NV21: 1358 case IA_CSS_FRAME_FORMAT_NV61: 1359 ia_css_debug_dtrace(2, " Y = %p\n", 1360 data + frame->planes.nv.y.offset); 1361 ia_css_debug_dtrace(2, " UV = %p\n", 1362 data + frame->planes.nv.uv.offset); 1363 break; 1364 case IA_CSS_FRAME_FORMAT_YUYV: 1365 case IA_CSS_FRAME_FORMAT_UYVY: 1366 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: 1367 case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: 1368 case IA_CSS_FRAME_FORMAT_YUV_LINE: 1369 ia_css_debug_dtrace(2, " YUYV = %p\n", 1370 data + frame->planes.yuyv.offset); 1371 break; 1372 case IA_CSS_FRAME_FORMAT_YUV420: 1373 case IA_CSS_FRAME_FORMAT_YUV422: 1374 case IA_CSS_FRAME_FORMAT_YUV444: 1375 case IA_CSS_FRAME_FORMAT_YV12: 1376 case IA_CSS_FRAME_FORMAT_YV16: 1377 case IA_CSS_FRAME_FORMAT_YUV420_16: 1378 case IA_CSS_FRAME_FORMAT_YUV422_16: 1379 ia_css_debug_dtrace(2, " Y = %p\n", 1380 data + frame->planes.yuv.y.offset); 1381 ia_css_debug_dtrace(2, " U = %p\n", 1382 data + frame->planes.yuv.u.offset); 1383 ia_css_debug_dtrace(2, " V = %p\n", 1384 data + frame->planes.yuv.v.offset); 1385 break; 1386 case IA_CSS_FRAME_FORMAT_RAW_PACKED: 1387 ia_css_debug_dtrace(2, " RAW PACKED = %p\n", 1388 data + frame->planes.raw.offset); 1389 break; 1390 case IA_CSS_FRAME_FORMAT_RAW: 1391 ia_css_debug_dtrace(2, " RAW = %p\n", 1392 data + frame->planes.raw.offset); 1393 break; 1394 case IA_CSS_FRAME_FORMAT_RGBA888: 1395 case IA_CSS_FRAME_FORMAT_RGB565: 1396 ia_css_debug_dtrace(2, " RGB = %p\n", 1397 data + frame->planes.rgb.offset); 1398 break; 1399 case IA_CSS_FRAME_FORMAT_QPLANE6: 1400 ia_css_debug_dtrace(2, " R = %p\n", 1401 data + frame->planes.plane6.r.offset); 1402 ia_css_debug_dtrace(2, " RatB = %p\n", 1403 data + frame->planes.plane6.r_at_b.offset); 1404 ia_css_debug_dtrace(2, " Gr = %p\n", 1405 data + frame->planes.plane6.gr.offset); 1406 ia_css_debug_dtrace(2, " Gb = %p\n", 1407 data + frame->planes.plane6.gb.offset); 1408 ia_css_debug_dtrace(2, " B = %p\n", 1409 data + frame->planes.plane6.b.offset); 1410 ia_css_debug_dtrace(2, " BatR = %p\n", 1411 data + frame->planes.plane6.b_at_r.offset); 1412 break; 1413 case IA_CSS_FRAME_FORMAT_BINARY_8: 1414 ia_css_debug_dtrace(2, " Binary data = %p\n", 1415 data + frame->planes.binary.data.offset); 1416 break; 1417 default: 1418 ia_css_debug_dtrace(2, " unknown frame type\n"); 1419 break; 1420 } 1421 return; 1422 } 1423 1424 #if SP_DEBUG != SP_DEBUG_NONE 1425 1426 void ia_css_debug_print_sp_debug_state(const struct sh_css_sp_debug_state 1427 *state) 1428 { 1429 #endif 1430 1431 #if SP_DEBUG == SP_DEBUG_DUMP 1432 1433 assert(state); 1434 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1435 "current SP software counter: %d\n", 1436 state->debug[0]); 1437 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1438 "empty output buffer queue head: 0x%x\n", 1439 state->debug[1]); 1440 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1441 "empty output buffer queue tail: 0x%x\n", 1442 state->debug[2]); 1443 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1444 "empty s3a buffer queue head: 0x%x\n", 1445 state->debug[3]); 1446 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1447 "empty s3a buffer queue tail: 0x%x\n", 1448 state->debug[4]); 1449 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1450 "full output buffer queue head: 0x%x\n", 1451 state->debug[5]); 1452 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1453 "full output buffer queue tail: 0x%x\n", 1454 state->debug[6]); 1455 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1456 "full s3a buffer queue head: 0x%x\n", 1457 state->debug[7]); 1458 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1459 "full s3a buffer queue tail: 0x%x\n", 1460 state->debug[8]); 1461 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue head: 0x%x\n", 1462 state->debug[9]); 1463 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue tail: 0x%x\n", 1464 state->debug[10]); 1465 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1466 "num of stages of current pipeline: 0x%x\n", 1467 state->debug[11]); 1468 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 1: 0x%x\n", 1469 state->debug[12]); 1470 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 2: 0x%x\n", 1471 state->debug[13]); 1472 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1473 "current stage out_vf buffer idx: 0x%x\n", 1474 state->debug[14]); 1475 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1476 "current stage output buffer idx: 0x%x\n", 1477 state->debug[15]); 1478 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1479 "current stage s3a buffer idx: 0x%x\n", 1480 state->debug[16]); 1481 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1482 "first char of current stage name: 0x%x\n", 1483 state->debug[17]); 1484 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "current SP thread id: 0x%x\n", 1485 state->debug[18]); 1486 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1487 "empty output buffer address 1: 0x%x\n", 1488 state->debug[19]); 1489 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1490 "empty output buffer address 2: 0x%x\n", 1491 state->debug[20]); 1492 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1493 "empty out_vf buffer address 1: 0x%x\n", 1494 state->debug[21]); 1495 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1496 "empty out_vf buffer address 2: 0x%x\n", 1497 state->debug[22]); 1498 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1499 "empty s3a_hi buffer address 1: 0x%x\n", 1500 state->debug[23]); 1501 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1502 "empty s3a_hi buffer address 2: 0x%x\n", 1503 state->debug[24]); 1504 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1505 "empty s3a_lo buffer address 1: 0x%x\n", 1506 state->debug[25]); 1507 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1508 "empty s3a_lo buffer address 2: 0x%x\n", 1509 state->debug[26]); 1510 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1511 "empty dis_hor buffer address 1: 0x%x\n", 1512 state->debug[27]); 1513 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1514 "empty dis_hor buffer address 2: 0x%x\n", 1515 state->debug[28]); 1516 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1517 "empty dis_ver buffer address 1: 0x%x\n", 1518 state->debug[29]); 1519 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1520 "empty dis_ver buffer address 2: 0x%x\n", 1521 state->debug[30]); 1522 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1523 "empty param buffer address: 0x%x\n", 1524 state->debug[31]); 1525 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1526 "first incorrect frame address: 0x%x\n", 1527 state->debug[32]); 1528 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1529 "first incorrect frame container address: 0x%x\n", 1530 state->debug[33]); 1531 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1532 "first incorrect frame container payload: 0x%x\n", 1533 state->debug[34]); 1534 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1535 "first incorrect s3a_hi address: 0x%x\n", 1536 state->debug[35]); 1537 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1538 "first incorrect s3a_hi container address: 0x%x\n", 1539 state->debug[36]); 1540 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1541 "first incorrect s3a_hi container payload: 0x%x\n", 1542 state->debug[37]); 1543 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1544 "first incorrect s3a_lo address: 0x%x\n", 1545 state->debug[38]); 1546 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1547 "first incorrect s3a_lo container address: 0x%x\n", 1548 state->debug[39]); 1549 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1550 "first incorrect s3a_lo container payload: 0x%x\n", 1551 state->debug[40]); 1552 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1553 "number of calling flash start function: 0x%x\n", 1554 state->debug[41]); 1555 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1556 "number of calling flash close function: 0x%x\n", 1557 state->debug[42]); 1558 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "number of flashed frame: 0x%x\n", 1559 state->debug[43]); 1560 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "flash in use flag: 0x%x\n", 1561 state->debug[44]); 1562 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1563 "number of update frame flashed flag: 0x%x\n", 1564 state->debug[46]); 1565 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1566 "number of active threads: 0x%x\n", 1567 state->debug[45]); 1568 1569 #elif SP_DEBUG == SP_DEBUG_COPY 1570 1571 /* Remember last_index because we only want to print new entries */ 1572 static int last_index; 1573 int sp_index = state->index; 1574 int n; 1575 1576 assert(state); 1577 if (sp_index < last_index) { 1578 /* SP has been reset */ 1579 last_index = 0; 1580 } 1581 1582 if (last_index == 0) { 1583 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1584 "copy-trace init: sp_dbg_if_start_line=%d, sp_dbg_if_start_column=%d, sp_dbg_if_cropped_height=%d, sp_debg_if_cropped_width=%d\n", 1585 state->if_start_line, 1586 state->if_start_column, 1587 state->if_cropped_height, 1588 state->if_cropped_width); 1589 } 1590 1591 if ((last_index + SH_CSS_SP_DBG_TRACE_DEPTH) < sp_index) { 1592 /* last index can be multiple rounds behind */ 1593 /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */ 1594 last_index = sp_index - SH_CSS_SP_DBG_TRACE_DEPTH; 1595 } 1596 1597 for (n = last_index; n < sp_index; n++) { 1598 int i = n % SH_CSS_SP_DBG_TRACE_DEPTH; 1599 1600 if (state->trace[i].frame != 0) { 1601 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1602 "copy-trace: frame=%d, line=%d, pixel_distance=%d, mipi_used_dword=%d, sp_index=%d\n", 1603 state->trace[i].frame, 1604 state->trace[i].line, 1605 state->trace[i].pixel_distance, 1606 state->trace[i].mipi_used_dword, 1607 state->trace[i].sp_index); 1608 } 1609 } 1610 1611 last_index = sp_index; 1612 1613 #elif SP_DEBUG == SP_DEBUG_TRACE 1614 1615 /* 1616 * This is just an example how TRACE_FILE_ID (see ia_css_debug.sp.h) will 1617 * me mapped on the file name string. 1618 * 1619 * Adjust this to your trace case! 1620 */ 1621 static char const *const id2filename[8] = { 1622 "param_buffer.sp.c | tagger.sp.c | pipe_data.sp.c", 1623 "isp_init.sp.c", 1624 "sp_raw_copy.hive.c", 1625 "dma_configure.sp.c", 1626 "sp.hive.c", 1627 "event_proxy_sp.hive.c", 1628 "circular_buffer.sp.c", 1629 "frame_buffer.sp.c" 1630 }; 1631 1632 #if 1 1633 /* Example SH_CSS_SP_DBG_NR_OF_TRACES==1 */ 1634 /* Adjust this to your trace case */ 1635 static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = { 1636 "default" 1637 }; 1638 #else 1639 /* Example SH_CSS_SP_DBG_NR_OF_TRACES==4 */ 1640 /* Adjust this to your trace case */ 1641 static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = { 1642 "copy", "preview/video", "capture", "acceleration" 1643 }; 1644 #endif 1645 1646 /* Remember host_index_last because we only want to print new entries */ 1647 static int host_index_last[SH_CSS_SP_DBG_NR_OF_TRACES] = { 0 }; 1648 int t, n; 1649 1650 assert(state); 1651 1652 for (t = 0; t < SH_CSS_SP_DBG_NR_OF_TRACES; t++) { 1653 int sp_index_last = state->index_last[t]; 1654 1655 if (sp_index_last < host_index_last[t]) { 1656 /* SP has been reset */ 1657 host_index_last[t] = 0; 1658 } 1659 1660 if ((host_index_last[t] + SH_CSS_SP_DBG_TRACE_DEPTH) < 1661 sp_index_last) { 1662 /* last index can be multiple rounds behind */ 1663 /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */ 1664 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1665 "Warning: trace %s has gap of %d traces\n", 1666 trace_name[t], 1667 (sp_index_last - 1668 (host_index_last[t] + 1669 SH_CSS_SP_DBG_TRACE_DEPTH))); 1670 1671 host_index_last[t] = 1672 sp_index_last - SH_CSS_SP_DBG_TRACE_DEPTH; 1673 } 1674 1675 for (n = host_index_last[t]; n < sp_index_last; n++) { 1676 int i = n % SH_CSS_SP_DBG_TRACE_DEPTH; 1677 int l = state->trace[t][i].location & 1678 ((1 << SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS) - 1); 1679 int fid = state->trace[t][i].location >> 1680 SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS; 1681 int ts = state->trace[t][i].time_stamp; 1682 1683 if (ts) { 1684 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1685 "%05d trace=%s, file=%s:%d, data=0x%08x\n", 1686 ts, 1687 trace_name[t], 1688 id2filename[fid], l, 1689 state->trace[t][i].data); 1690 } 1691 } 1692 host_index_last[t] = sp_index_last; 1693 } 1694 1695 #elif SP_DEBUG == SP_DEBUG_MINIMAL 1696 int i; 1697 int base = 0; 1698 int limit = SH_CSS_NUM_SP_DEBUG; 1699 int step = 1; 1700 1701 assert(state); 1702 1703 for (i = base; i < limit; i += step) { 1704 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1705 "sp_dbg_trace[%d] = %d\n", 1706 i, state->debug[i]); 1707 } 1708 #endif 1709 1710 #if SP_DEBUG != SP_DEBUG_NONE 1711 1712 return; 1713 } 1714 #endif 1715 1716 #if defined(HAS_INPUT_FORMATTER_VERSION_2) && !defined(HAS_NO_INPUT_FORMATTER) 1717 static void debug_print_rx_mipi_port_state(mipi_port_state_t *state) 1718 { 1719 int i; 1720 unsigned int bits, infos; 1721 1722 assert(state); 1723 1724 bits = state->irq_status; 1725 infos = ia_css_isys_rx_translate_irq_infos(bits); 1726 1727 ia_css_debug_dtrace(2, "\t\t%-32s: (irq reg = 0x%X)\n", 1728 "receiver errors", bits); 1729 1730 if (infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN) 1731 ia_css_debug_dtrace(2, "\t\t\tbuffer overrun\n"); 1732 if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT) 1733 ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission error\n"); 1734 if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC) 1735 ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission sync error\n"); 1736 if (infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL) 1737 ia_css_debug_dtrace(2, "\t\t\tcontrol error\n"); 1738 if (infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE) 1739 ia_css_debug_dtrace(2, "\t\t\t2 or more ECC errors\n"); 1740 if (infos & IA_CSS_RX_IRQ_INFO_ERR_CRC) 1741 ia_css_debug_dtrace(2, "\t\t\tCRC mismatch\n"); 1742 if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID) 1743 ia_css_debug_dtrace(2, "\t\t\tunknown error\n"); 1744 if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC) 1745 ia_css_debug_dtrace(2, "\t\t\tframe sync error\n"); 1746 if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA) 1747 ia_css_debug_dtrace(2, "\t\t\tframe data error\n"); 1748 if (infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT) 1749 ia_css_debug_dtrace(2, "\t\t\tdata timeout\n"); 1750 if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC) 1751 ia_css_debug_dtrace(2, "\t\t\tunknown escape command entry\n"); 1752 if (infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC) 1753 ia_css_debug_dtrace(2, "\t\t\tline sync error\n"); 1754 1755 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1756 "device_ready", state->device_ready); 1757 1758 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1759 "irq_status", state->irq_status); 1760 1761 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1762 "irq_enable", state->irq_enable); 1763 1764 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1765 "timeout_count", state->timeout_count); 1766 1767 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1768 "init_count", state->init_count); 1769 1770 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16_18", state->raw16_18); 1771 1772 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1773 "sync_count", state->sync_count); 1774 1775 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "rx_count", state->rx_count); 1776 1777 for (i = 0; i < MIPI_4LANE_CFG; i++) { 1778 ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n", 1779 "lane_sync_count[", i, "]", 1780 state->lane_sync_count[i]); 1781 } 1782 1783 for (i = 0; i < MIPI_4LANE_CFG; i++) { 1784 ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n", 1785 "lane_rx_count[", i, "]", 1786 state->lane_rx_count[i]); 1787 } 1788 1789 return; 1790 } 1791 1792 static void debug_print_rx_channel_state(rx_channel_state_t *state) 1793 { 1794 int i; 1795 1796 assert(state); 1797 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1798 "compression_scheme0", state->comp_scheme0); 1799 1800 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1801 "compression_scheme1", state->comp_scheme1); 1802 1803 for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) { 1804 ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n", 1805 "MIPI Predictor ", i, state->pred[i]); 1806 } 1807 1808 for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) { 1809 ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n", 1810 "MIPI Compressor ", i, state->comp[i]); 1811 } 1812 1813 return; 1814 } 1815 1816 static void debug_print_rx_state(receiver_state_t *state) 1817 { 1818 int i; 1819 1820 assert(state); 1821 ia_css_debug_dtrace(2, "CSI Receiver State:\n"); 1822 1823 ia_css_debug_dtrace(2, "\tConfiguration:\n"); 1824 1825 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1826 "fs_to_ls_delay", state->fs_to_ls_delay); 1827 1828 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1829 "ls_to_data_delay", state->ls_to_data_delay); 1830 1831 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1832 "data_to_le_delay", state->data_to_le_delay); 1833 1834 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1835 "le_to_fe_delay", state->le_to_fe_delay); 1836 1837 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1838 "fe_to_fs_delay", state->fe_to_fs_delay); 1839 1840 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1841 "le_to_fs_delay", state->le_to_fs_delay); 1842 1843 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1844 "is_two_ppc", state->is_two_ppc); 1845 1846 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1847 "backend_rst", state->backend_rst); 1848 1849 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw18", state->raw18); 1850 1851 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1852 "force_raw8", state->force_raw8); 1853 1854 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16", state->raw16); 1855 1856 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1857 "be_gsp_acc_ovl", state->be_gsp_acc_ovl); 1858 1859 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_srst", state->be_srst); 1860 1861 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1862 "be_is_two_ppc", state->be_is_two_ppc); 1863 1864 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1865 "be_comp_format0", state->be_comp_format0); 1866 1867 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1868 "be_comp_format1", state->be_comp_format1); 1869 1870 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1871 "be_comp_format2", state->be_comp_format2); 1872 1873 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1874 "be_comp_format3", state->be_comp_format3); 1875 1876 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_sel", state->be_sel); 1877 1878 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1879 "be_raw16_config", state->be_raw16_config); 1880 1881 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1882 "be_raw18_config", state->be_raw18_config); 1883 1884 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1885 "be_force_raw8", state->be_force_raw8); 1886 1887 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1888 "be_irq_status", state->be_irq_status); 1889 1890 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1891 "be_irq_clear", state->be_irq_clear); 1892 1893 /* mipi port state */ 1894 for (i = 0; i < N_MIPI_PORT_ID; i++) { 1895 ia_css_debug_dtrace(2, "\tMIPI Port %d State:\n", i); 1896 1897 debug_print_rx_mipi_port_state(&state->mipi_port_state[i]); 1898 } 1899 /* end of mipi port state */ 1900 1901 /* rx channel state */ 1902 for (i = 0; i < N_RX_CHANNEL_ID; i++) { 1903 ia_css_debug_dtrace(2, "\tRX Channel %d State:\n", i); 1904 1905 debug_print_rx_channel_state(&state->rx_channel_state[i]); 1906 } 1907 /* end of rx channel state */ 1908 1909 return; 1910 } 1911 #endif 1912 1913 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) 1914 void ia_css_debug_dump_rx_state(void) 1915 { 1916 #if defined(HAS_INPUT_FORMATTER_VERSION_2) && !defined(HAS_NO_INPUT_FORMATTER) 1917 receiver_state_t state; 1918 1919 receiver_get_state(RX0_ID, &state); 1920 debug_print_rx_state(&state); 1921 #endif 1922 } 1923 #endif 1924 1925 void ia_css_debug_dump_sp_sw_debug_info(void) 1926 { 1927 #if SP_DEBUG != SP_DEBUG_NONE 1928 struct sh_css_sp_debug_state state; 1929 1930 sh_css_sp_get_debug_state(&state); 1931 ia_css_debug_print_sp_debug_state(&state); 1932 #endif 1933 ia_css_bufq_dump_queue_info(); 1934 ia_css_pipeline_dump_thread_map_info(); 1935 return; 1936 } 1937 1938 #if defined(USE_INPUT_SYSTEM_VERSION_2) 1939 static void debug_print_isys_capture_unit_state(capture_unit_state_t *state) 1940 { 1941 assert(state); 1942 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1943 "Packet_Length", state->Packet_Length); 1944 1945 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1946 "Received_Length", state->Received_Length); 1947 1948 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1949 "Received_Short_Packets", 1950 state->Received_Short_Packets); 1951 1952 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1953 "Received_Long_Packets", 1954 state->Received_Long_Packets); 1955 1956 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1957 "Last_Command", state->Last_Command); 1958 1959 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1960 "Next_Command", state->Next_Command); 1961 1962 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1963 "Last_Acknowledge", state->Last_Acknowledge); 1964 1965 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1966 "Next_Acknowledge", state->Next_Acknowledge); 1967 1968 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1969 "FSM_State_Info", state->FSM_State_Info); 1970 1971 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1972 "StartMode", state->StartMode); 1973 1974 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1975 "Start_Addr", state->Start_Addr); 1976 1977 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1978 "Mem_Region_Size", state->Mem_Region_Size); 1979 1980 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1981 "Num_Mem_Regions", state->Num_Mem_Regions); 1982 return; 1983 } 1984 1985 static void debug_print_isys_acquisition_unit_state( 1986 acquisition_unit_state_t *state) 1987 { 1988 assert(state); 1989 1990 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1991 "Received_Short_Packets", 1992 state->Received_Short_Packets); 1993 1994 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1995 "Received_Long_Packets", 1996 state->Received_Long_Packets); 1997 1998 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1999 "Last_Command", state->Last_Command); 2000 2001 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2002 "Next_Command", state->Next_Command); 2003 2004 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2005 "Last_Acknowledge", state->Last_Acknowledge); 2006 2007 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2008 "Next_Acknowledge", state->Next_Acknowledge); 2009 2010 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2011 "FSM_State_Info", state->FSM_State_Info); 2012 2013 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2014 "Int_Cntr_Info", state->Int_Cntr_Info); 2015 2016 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2017 "Start_Addr", state->Start_Addr); 2018 2019 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2020 "Mem_Region_Size", state->Mem_Region_Size); 2021 2022 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2023 "Num_Mem_Regions", state->Num_Mem_Regions); 2024 } 2025 2026 static void debug_print_isys_ctrl_unit_state(ctrl_unit_state_t *state) 2027 { 2028 assert(state); 2029 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_cmd", state->last_cmd); 2030 2031 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_cmd", state->next_cmd); 2032 2033 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_ack", state->last_ack); 2034 2035 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_ack", state->next_ack); 2036 2037 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2038 "top_fsm_state", state->top_fsm_state); 2039 2040 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2041 "captA_fsm_state", state->captA_fsm_state); 2042 2043 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2044 "captB_fsm_state", state->captB_fsm_state); 2045 2046 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2047 "captC_fsm_state", state->captC_fsm_state); 2048 2049 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2050 "acq_fsm_state", state->acq_fsm_state); 2051 2052 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2053 "captA_start_addr", state->captA_start_addr); 2054 2055 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2056 "captB_start_addr", state->captB_start_addr); 2057 2058 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2059 "captC_start_addr", state->captC_start_addr); 2060 2061 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2062 "captA_mem_region_size", 2063 state->captA_mem_region_size); 2064 2065 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2066 "captB_mem_region_size", 2067 state->captB_mem_region_size); 2068 2069 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2070 "captC_mem_region_size", 2071 state->captC_mem_region_size); 2072 2073 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2074 "captA_num_mem_regions", 2075 state->captA_num_mem_regions); 2076 2077 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2078 "captB_num_mem_regions", 2079 state->captB_num_mem_regions); 2080 2081 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2082 "captC_num_mem_regions", 2083 state->captC_num_mem_regions); 2084 2085 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2086 "acq_start_addr", state->acq_start_addr); 2087 2088 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2089 "acq_mem_region_size", state->acq_mem_region_size); 2090 2091 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2092 "acq_num_mem_regions", state->acq_num_mem_regions); 2093 2094 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2095 "capt_reserve_one_mem_region", 2096 state->capt_reserve_one_mem_region); 2097 2098 return; 2099 } 2100 2101 static void debug_print_isys_state(input_system_state_t *state) 2102 { 2103 int i; 2104 2105 assert(state); 2106 ia_css_debug_dtrace(2, "InputSystem State:\n"); 2107 2108 /* configuration */ 2109 ia_css_debug_dtrace(2, "\tConfiguration:\n"); 2110 2111 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2112 "str_multiCastA_sel", state->str_multicastA_sel); 2113 2114 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2115 "str_multicastB_sel", state->str_multicastB_sel); 2116 2117 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2118 "str_multicastC_sel", state->str_multicastC_sel); 2119 2120 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2121 "str_mux_sel", state->str_mux_sel); 2122 2123 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2124 "str_mon_status", state->str_mon_status); 2125 2126 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2127 "str_mon_irq_cond", state->str_mon_irq_cond); 2128 2129 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2130 "str_mon_irq_en", state->str_mon_irq_en); 2131 2132 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2133 "isys_srst", state->isys_srst); 2134 2135 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2136 "isys_slv_reg_srst", state->isys_slv_reg_srst); 2137 2138 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2139 "str_deint_portA_cnt", state->str_deint_portA_cnt); 2140 2141 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2142 "str_deint_portB_cnd", state->str_deint_portB_cnt); 2143 /* end of configuration */ 2144 2145 /* capture unit state */ 2146 for (i = 0; i < N_CAPTURE_UNIT_ID; i++) { 2147 capture_unit_state_t *capture_unit_state; 2148 2149 ia_css_debug_dtrace(2, "\tCaptureUnit %d State:\n", i); 2150 2151 capture_unit_state = &state->capture_unit[i]; 2152 debug_print_isys_capture_unit_state(capture_unit_state); 2153 } 2154 /* end of capture unit state */ 2155 2156 /* acquisition unit state */ 2157 for (i = 0; i < N_ACQUISITION_UNIT_ID; i++) { 2158 acquisition_unit_state_t *acquisition_unit_state; 2159 2160 ia_css_debug_dtrace(2, "\tAcquisitionUnit %d State:\n", i); 2161 2162 acquisition_unit_state = &state->acquisition_unit[i]; 2163 debug_print_isys_acquisition_unit_state(acquisition_unit_state); 2164 } 2165 /* end of acquisition unit state */ 2166 2167 /* control unit state */ 2168 for (i = 0; i < N_CTRL_UNIT_ID; i++) { 2169 ia_css_debug_dtrace(2, "\tControlUnit %d State:\n", i); 2170 2171 debug_print_isys_ctrl_unit_state(&state->ctrl_unit_state[i]); 2172 } 2173 /* end of control unit state */ 2174 } 2175 2176 void ia_css_debug_dump_isys_state(void) 2177 { 2178 input_system_state_t state; 2179 2180 input_system_get_state(INPUT_SYSTEM0_ID, &state); 2181 debug_print_isys_state(&state); 2182 2183 return; 2184 } 2185 #endif 2186 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) 2187 void ia_css_debug_dump_isys_state(void) 2188 { 2189 /* Android compilation fails if made a local variable 2190 stack size on android is limited to 2k and this structure 2191 is around 3.5K, in place of static malloc can be done but 2192 if this call is made too often it will lead to fragment memory 2193 versus a fixed allocation */ 2194 static input_system_state_t state; 2195 2196 input_system_get_state(INPUT_SYSTEM0_ID, &state); 2197 input_system_dump_state(INPUT_SYSTEM0_ID, &state); 2198 } 2199 #endif 2200 2201 void ia_css_debug_dump_debug_info(const char *context) 2202 { 2203 if (!context) 2204 context = "No Context provided"; 2205 2206 ia_css_debug_dtrace(2, "CSS Debug Info dump [Context = %s]\n", context); 2207 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) 2208 ia_css_debug_dump_rx_state(); 2209 #endif 2210 #if !defined(HAS_NO_INPUT_FORMATTER) && defined(USE_INPUT_SYSTEM_VERSION_2) 2211 ia_css_debug_dump_if_state(); 2212 #endif 2213 ia_css_debug_dump_isp_state(); 2214 ia_css_debug_dump_isp_sp_fifo_state(); 2215 ia_css_debug_dump_isp_gdc_fifo_state(); 2216 ia_css_debug_dump_sp_state(); 2217 ia_css_debug_dump_perf_counters(); 2218 2219 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG 2220 sh_css_dump_thread_wait_info(); 2221 sh_css_dump_pipe_stage_info(); 2222 sh_css_dump_pipe_stripe_info(); 2223 #endif 2224 ia_css_debug_dump_dma_isp_fifo_state(); 2225 ia_css_debug_dump_dma_sp_fifo_state(); 2226 ia_css_debug_dump_dma_state(); 2227 #if defined(USE_INPUT_SYSTEM_VERSION_2) 2228 ia_css_debug_dump_isys_state(); 2229 2230 { 2231 irq_controller_state_t state; 2232 2233 irq_controller_get_state(IRQ2_ID, &state); 2234 2235 ia_css_debug_dtrace(2, "\t%-32s:\n", 2236 "Input System IRQ Controller State"); 2237 2238 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2239 "irq_edge", state.irq_edge); 2240 2241 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2242 "irq_mask", state.irq_mask); 2243 2244 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2245 "irq_status", state.irq_status); 2246 2247 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2248 "irq_enable", state.irq_enable); 2249 2250 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2251 "irq_level_not_pulse", 2252 state.irq_level_not_pulse); 2253 } 2254 #endif 2255 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) 2256 ia_css_debug_dump_isys_state(); 2257 #endif 2258 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) 2259 ia_css_debug_tagger_state(); 2260 #endif 2261 return; 2262 } 2263 2264 /* this function is for debug use, it can make SP go to sleep 2265 state after each frame, then user can dump the stable SP dmem. 2266 this function can be called after ia_css_start_sp() 2267 and before sh_css_init_buffer_queues() 2268 */ 2269 void ia_css_debug_enable_sp_sleep_mode(enum ia_css_sp_sleep_mode mode) 2270 { 2271 const struct ia_css_fw_info *fw; 2272 unsigned int HIVE_ADDR_sp_sleep_mode; 2273 2274 fw = &sh_css_sp_fw; 2275 HIVE_ADDR_sp_sleep_mode = fw->info.sp.sleep_mode; 2276 2277 (void)HIVE_ADDR_sp_sleep_mode; /* Suppres warnings in CRUN */ 2278 2279 sp_dmem_store_uint32(SP0_ID, 2280 (unsigned int)sp_address_of(sp_sleep_mode), 2281 (uint32_t)mode); 2282 } 2283 2284 void ia_css_debug_wake_up_sp(void) 2285 { 2286 /*hrt_ctl_start(SP); */ 2287 sp_ctrl_setbit(SP0_ID, SP_SC_REG, SP_START_BIT); 2288 } 2289 2290 #if !defined(IS_ISP_2500_SYSTEM) 2291 #define FIND_DMEM_PARAMS_TYPE(stream, kernel, type) \ 2292 (struct HRTCAT(HRTCAT(sh_css_isp_, type), _params) *) \ 2293 findf_dmem_params(stream, offsetof(struct ia_css_memory_offsets, dmem.kernel)) 2294 2295 #define FIND_DMEM_PARAMS(stream, kernel) FIND_DMEM_PARAMS_TYPE(stream, kernel, kernel) 2296 2297 /* Find a stage that support the kernel and return the parameters for that kernel */ 2298 static char * 2299 findf_dmem_params(struct ia_css_stream *stream, short idx) 2300 { 2301 int i; 2302 2303 for (i = 0; i < stream->num_pipes; i++) { 2304 struct ia_css_pipe *pipe = stream->pipes[i]; 2305 struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe); 2306 struct ia_css_pipeline_stage *stage; 2307 2308 for (stage = pipeline->stages; stage; stage = stage->next) { 2309 struct ia_css_binary *binary = stage->binary; 2310 short *offsets = (short *)&binary->info->mem_offsets.offsets.param->dmem; 2311 short dmem_offset = offsets[idx]; 2312 const struct ia_css_host_data *isp_data = 2313 ia_css_isp_param_get_mem_init(&binary->mem_params, 2314 IA_CSS_PARAM_CLASS_PARAM, IA_CSS_ISP_DMEM0); 2315 if (dmem_offset < 0) 2316 continue; 2317 return &isp_data->address[dmem_offset]; 2318 } 2319 } 2320 return NULL; 2321 } 2322 #endif 2323 2324 void ia_css_debug_dump_isp_params(struct ia_css_stream *stream, 2325 unsigned int enable) 2326 { 2327 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "ISP PARAMETERS:\n"); 2328 #if defined(IS_ISP_2500_SYSTEM) 2329 (void)enable; 2330 (void)stream; 2331 #else 2332 2333 assert(stream); 2334 if ((enable & IA_CSS_DEBUG_DUMP_FPN) 2335 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2336 ia_css_fpn_dump(FIND_DMEM_PARAMS(stream, fpn), IA_CSS_DEBUG_VERBOSE); 2337 } 2338 if ((enable & IA_CSS_DEBUG_DUMP_OB) 2339 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2340 ia_css_ob_dump(FIND_DMEM_PARAMS(stream, ob), IA_CSS_DEBUG_VERBOSE); 2341 } 2342 if ((enable & IA_CSS_DEBUG_DUMP_SC) 2343 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2344 ia_css_sc_dump(FIND_DMEM_PARAMS(stream, sc), IA_CSS_DEBUG_VERBOSE); 2345 } 2346 if ((enable & IA_CSS_DEBUG_DUMP_WB) 2347 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2348 ia_css_wb_dump(FIND_DMEM_PARAMS(stream, wb), IA_CSS_DEBUG_VERBOSE); 2349 } 2350 if ((enable & IA_CSS_DEBUG_DUMP_DP) 2351 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2352 ia_css_dp_dump(FIND_DMEM_PARAMS(stream, dp), IA_CSS_DEBUG_VERBOSE); 2353 } 2354 if ((enable & IA_CSS_DEBUG_DUMP_BNR) 2355 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2356 ia_css_bnr_dump(FIND_DMEM_PARAMS(stream, bnr), IA_CSS_DEBUG_VERBOSE); 2357 } 2358 if ((enable & IA_CSS_DEBUG_DUMP_S3A) 2359 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2360 ia_css_s3a_dump(FIND_DMEM_PARAMS(stream, s3a), IA_CSS_DEBUG_VERBOSE); 2361 } 2362 if ((enable & IA_CSS_DEBUG_DUMP_DE) 2363 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2364 ia_css_de_dump(FIND_DMEM_PARAMS(stream, de), IA_CSS_DEBUG_VERBOSE); 2365 } 2366 if ((enable & IA_CSS_DEBUG_DUMP_YNR) 2367 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2368 ia_css_nr_dump(FIND_DMEM_PARAMS_TYPE(stream, nr, ynr), IA_CSS_DEBUG_VERBOSE); 2369 ia_css_yee_dump(FIND_DMEM_PARAMS(stream, yee), IA_CSS_DEBUG_VERBOSE); 2370 } 2371 if ((enable & IA_CSS_DEBUG_DUMP_CSC) 2372 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2373 ia_css_csc_dump(FIND_DMEM_PARAMS(stream, csc), IA_CSS_DEBUG_VERBOSE); 2374 ia_css_yuv2rgb_dump(FIND_DMEM_PARAMS_TYPE(stream, yuv2rgb, csc), 2375 IA_CSS_DEBUG_VERBOSE); 2376 ia_css_rgb2yuv_dump(FIND_DMEM_PARAMS_TYPE(stream, rgb2yuv, csc), 2377 IA_CSS_DEBUG_VERBOSE); 2378 } 2379 if ((enable & IA_CSS_DEBUG_DUMP_GC) 2380 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2381 ia_css_gc_dump(FIND_DMEM_PARAMS(stream, gc), IA_CSS_DEBUG_VERBOSE); 2382 } 2383 if ((enable & IA_CSS_DEBUG_DUMP_TNR) 2384 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2385 ia_css_tnr_dump(FIND_DMEM_PARAMS(stream, tnr), IA_CSS_DEBUG_VERBOSE); 2386 } 2387 if ((enable & IA_CSS_DEBUG_DUMP_ANR) 2388 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2389 ia_css_anr_dump(FIND_DMEM_PARAMS(stream, anr), IA_CSS_DEBUG_VERBOSE); 2390 } 2391 if ((enable & IA_CSS_DEBUG_DUMP_CE) 2392 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2393 ia_css_ce_dump(FIND_DMEM_PARAMS(stream, ce), IA_CSS_DEBUG_VERBOSE); 2394 } 2395 #endif 2396 } 2397 2398 void sh_css_dump_sp_raw_copy_linecount(bool reduced) 2399 { 2400 const struct ia_css_fw_info *fw; 2401 unsigned int HIVE_ADDR_raw_copy_line_count; 2402 s32 raw_copy_line_count; 2403 static s32 prev_raw_copy_line_count = -1; 2404 2405 fw = &sh_css_sp_fw; 2406 HIVE_ADDR_raw_copy_line_count = 2407 fw->info.sp.raw_copy_line_count; 2408 2409 (void)HIVE_ADDR_raw_copy_line_count; 2410 2411 sp_dmem_load(SP0_ID, 2412 (unsigned int)sp_address_of(raw_copy_line_count), 2413 &raw_copy_line_count, 2414 sizeof(raw_copy_line_count)); 2415 2416 /* only indicate if copy loop is active */ 2417 if (reduced) 2418 raw_copy_line_count = (raw_copy_line_count < 0) ? raw_copy_line_count : 1; 2419 /* do the handling */ 2420 if (prev_raw_copy_line_count != raw_copy_line_count) { 2421 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2422 "sh_css_dump_sp_raw_copy_linecount() line_count=%d\n", 2423 raw_copy_line_count); 2424 prev_raw_copy_line_count = raw_copy_line_count; 2425 } 2426 } 2427 2428 void ia_css_debug_dump_isp_binary(void) 2429 { 2430 const struct ia_css_fw_info *fw; 2431 unsigned int HIVE_ADDR_pipeline_sp_curr_binary_id; 2432 u32 curr_binary_id; 2433 static u32 prev_binary_id = 0xFFFFFFFF; 2434 static u32 sample_count; 2435 2436 fw = &sh_css_sp_fw; 2437 HIVE_ADDR_pipeline_sp_curr_binary_id = fw->info.sp.curr_binary_id; 2438 2439 (void)HIVE_ADDR_pipeline_sp_curr_binary_id; 2440 2441 sp_dmem_load(SP0_ID, 2442 (unsigned int)sp_address_of(pipeline_sp_curr_binary_id), 2443 &curr_binary_id, 2444 sizeof(curr_binary_id)); 2445 2446 /* do the handling */ 2447 sample_count++; 2448 if (prev_binary_id != curr_binary_id) { 2449 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2450 "sh_css_dump_isp_binary() pipe_id=%d, binary_id=%d, sample_count=%d\n", 2451 (curr_binary_id >> 16), 2452 (curr_binary_id & 0x0ffff), 2453 sample_count); 2454 sample_count = 0; 2455 prev_binary_id = curr_binary_id; 2456 } 2457 } 2458 2459 void ia_css_debug_dump_perf_counters(void) 2460 { 2461 #if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) 2462 const struct ia_css_fw_info *fw; 2463 int i; 2464 unsigned int HIVE_ADDR_ia_css_isys_sp_error_cnt; 2465 s32 ia_css_sp_input_system_error_cnt[N_MIPI_PORT_ID + 2466 1]; /* 3 Capture Units and 1 Acquire Unit. */ 2467 2468 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "Input System Error Counters:\n"); 2469 2470 fw = &sh_css_sp_fw; 2471 HIVE_ADDR_ia_css_isys_sp_error_cnt = 2472 fw->info.sp.perf_counter_input_system_error; 2473 2474 (void)HIVE_ADDR_ia_css_isys_sp_error_cnt; 2475 2476 sp_dmem_load(SP0_ID, 2477 (unsigned int)sp_address_of(ia_css_isys_sp_error_cnt), 2478 &ia_css_sp_input_system_error_cnt, 2479 sizeof(ia_css_sp_input_system_error_cnt)); 2480 2481 for (i = 0; i < N_MIPI_PORT_ID + 1; i++) { 2482 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\tport[%d] = %d\n", 2483 i, ia_css_sp_input_system_error_cnt[i]); 2484 } 2485 #endif 2486 } 2487 2488 /* 2489 2490 void sh_css_init_ddr_debug_queue(void) 2491 { 2492 hrt_vaddress ddr_debug_queue_addr = 2493 mmgr_malloc(sizeof(debug_data_ddr_t)); 2494 const struct ia_css_fw_info *fw; 2495 unsigned int HIVE_ADDR_debug_buffer_ddr_address; 2496 2497 fw = &sh_css_sp_fw; 2498 HIVE_ADDR_debug_buffer_ddr_address = 2499 fw->info.sp.debug_buffer_ddr_address; 2500 2501 (void)HIVE_ADDR_debug_buffer_ddr_address; 2502 2503 debug_buffer_ddr_init(ddr_debug_queue_addr); 2504 2505 sp_dmem_store_uint32(SP0_ID, 2506 (unsigned int)sp_address_of(debug_buffer_ddr_address), 2507 (uint32_t)(ddr_debug_queue_addr)); 2508 } 2509 2510 void sh_css_load_ddr_debug_queue(void) 2511 { 2512 debug_synch_queue_ddr(); 2513 } 2514 2515 void ia_css_debug_dump_ddr_debug_queue(void) 2516 { 2517 int i; 2518 sh_css_load_ddr_debug_queue(); 2519 for (i = 0; i < DEBUG_BUF_SIZE; i++) { 2520 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2521 "ddr_debug_queue[%d] = 0x%x\n", 2522 i, debug_data_ptr->buf[i]); 2523 } 2524 } 2525 */ 2526 2527 /* 2528 * @brief Initialize the debug mode. 2529 * Refer to "ia_css_debug.h" for more details. 2530 */ 2531 bool ia_css_debug_mode_init(void) 2532 { 2533 bool rc; 2534 2535 rc = sh_css_sp_init_dma_sw_reg(0); 2536 return rc; 2537 } 2538 2539 /* 2540 * @brief Disable the DMA channel. 2541 * Refer to "ia_css_debug.h" for more details. 2542 */ 2543 bool 2544 ia_css_debug_mode_disable_dma_channel(int dma_id, 2545 int channel_id, int request_type) 2546 { 2547 bool rc; 2548 2549 rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, false); 2550 2551 return rc; 2552 } 2553 2554 /* 2555 * @brief Enable the DMA channel. 2556 * Refer to "ia_css_debug.h" for more details. 2557 */ 2558 bool 2559 ia_css_debug_mode_enable_dma_channel(int dma_id, 2560 int channel_id, int request_type) 2561 { 2562 bool rc; 2563 2564 rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, true); 2565 2566 return rc; 2567 } 2568 2569 static 2570 void dtrace_dot(const char *fmt, ...) 2571 { 2572 va_list ap; 2573 2574 assert(fmt); 2575 va_start(ap, fmt); 2576 2577 ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START); 2578 ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap); 2579 ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END); 2580 va_end(ap); 2581 } 2582 2583 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG 2584 void sh_css_dump_thread_wait_info(void) 2585 { 2586 const struct ia_css_fw_info *fw; 2587 int i; 2588 unsigned int HIVE_ADDR_sp_thread_wait; 2589 s32 sp_thread_wait[MAX_THREAD_NUM]; 2590 2591 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "SEM WAITS:\n"); 2592 2593 fw = &sh_css_sp_fw; 2594 HIVE_ADDR_sp_thread_wait = 2595 fw->info.sp.debug_wait; 2596 2597 (void)HIVE_ADDR_sp_thread_wait; 2598 2599 sp_dmem_load(SP0_ID, 2600 (unsigned int)sp_address_of(sp_thread_wait), 2601 &sp_thread_wait, 2602 sizeof(sp_thread_wait)); 2603 for (i = 0; i < MAX_THREAD_NUM; i++) { 2604 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2605 "\twait[%d] = 0x%X\n", 2606 i, sp_thread_wait[i]); 2607 } 2608 } 2609 2610 void sh_css_dump_pipe_stage_info(void) 2611 { 2612 const struct ia_css_fw_info *fw; 2613 int i; 2614 unsigned int HIVE_ADDR_sp_pipe_stage; 2615 s32 sp_pipe_stage[MAX_THREAD_NUM]; 2616 2617 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STAGE:\n"); 2618 2619 fw = &sh_css_sp_fw; 2620 HIVE_ADDR_sp_pipe_stage = 2621 fw->info.sp.debug_stage; 2622 2623 (void)HIVE_ADDR_sp_pipe_stage; 2624 2625 sp_dmem_load(SP0_ID, 2626 (unsigned int)sp_address_of(sp_pipe_stage), 2627 &sp_pipe_stage, 2628 sizeof(sp_pipe_stage)); 2629 for (i = 0; i < MAX_THREAD_NUM; i++) { 2630 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2631 "\tstage[%d] = %d\n", 2632 i, sp_pipe_stage[i]); 2633 } 2634 } 2635 2636 void sh_css_dump_pipe_stripe_info(void) 2637 { 2638 const struct ia_css_fw_info *fw; 2639 int i; 2640 unsigned int HIVE_ADDR_sp_pipe_stripe; 2641 s32 sp_pipe_stripe[MAX_THREAD_NUM]; 2642 2643 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STRIPE:\n"); 2644 2645 fw = &sh_css_sp_fw; 2646 HIVE_ADDR_sp_pipe_stripe = 2647 fw->info.sp.debug_stripe; 2648 2649 (void)HIVE_ADDR_sp_pipe_stripe; 2650 2651 sp_dmem_load(SP0_ID, 2652 (unsigned int)sp_address_of(sp_pipe_stripe), 2653 &sp_pipe_stripe, 2654 sizeof(sp_pipe_stripe)); 2655 for (i = 0; i < MAX_THREAD_NUM; i++) { 2656 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2657 "\tstripe[%d] = %d\n", 2658 i, sp_pipe_stripe[i]); 2659 } 2660 } 2661 #endif 2662 2663 static void 2664 ia_css_debug_pipe_graph_dump_frame( 2665 struct ia_css_frame *frame, 2666 enum ia_css_pipe_id id, 2667 char const *blob_name, 2668 char const *frame_name, 2669 bool in_frame) 2670 { 2671 char bufinfo[100]; 2672 2673 if (frame->dynamic_queue_id == SH_CSS_INVALID_QUEUE_ID) { 2674 snprintf(bufinfo, sizeof(bufinfo), "Internal"); 2675 } else { 2676 snprintf(bufinfo, sizeof(bufinfo), "Queue: %s %s", 2677 pipe_id_to_str[id], 2678 queue_id_to_str[frame->dynamic_queue_id]); 2679 } 2680 dtrace_dot( 2681 "node [shape = box, fixedsize=true, width=2, height=0.7]; \"%p\" [label = \"%s\\n%d(%d) x %d, %dbpp\\n%s\"];", 2682 frame, 2683 debug_frame_format2str(frame->info.format), 2684 frame->info.res.width, 2685 frame->info.padded_width, 2686 frame->info.res.height, 2687 frame->info.raw_bit_depth, 2688 bufinfo); 2689 2690 if (in_frame) { 2691 dtrace_dot( 2692 "\"%p\"->\"%s(pipe%d)\" [label = %s_frame];", 2693 frame, 2694 blob_name, id, frame_name); 2695 } else { 2696 dtrace_dot( 2697 "\"%s(pipe%d)\"->\"%p\" [label = %s_frame];", 2698 blob_name, id, 2699 frame, 2700 frame_name); 2701 } 2702 } 2703 2704 void 2705 ia_css_debug_pipe_graph_dump_prologue(void) 2706 { 2707 dtrace_dot("digraph sh_css_pipe_graph {"); 2708 dtrace_dot("rankdir=LR;"); 2709 2710 dtrace_dot("fontsize=9;"); 2711 dtrace_dot("label = \"\\nEnable options: rp=reduced pipe, vfve=vf_veceven, dvse=dvs_envelope, dvs6=dvs_6axis, bo=block_out, fbds=fixed_bayer_ds, bf6=bayer_fir_6db, rawb=raw_binning, cont=continuous, disc=dis_crop\\n" 2712 "dp2a=dp_2adjacent, outp=output, outt=out_table, reff=ref_frame, par=params, gam=gamma, cagdc=ca_gdc, ispa=isp_addresses, inf=in_frame, outf=out_frame, hs=high_speed, inpc=input_chunking\""); 2713 } 2714 2715 void ia_css_debug_pipe_graph_dump_epilogue(void) 2716 { 2717 if (strlen(ring_buffer) > 0) { 2718 dtrace_dot(ring_buffer); 2719 } 2720 2721 if (pg_inst.stream_format != N_ATOMISP_INPUT_FORMAT) { 2722 /* An input stream format has been set so assume we have 2723 * an input system and sensor 2724 */ 2725 2726 dtrace_dot( 2727 "node [shape = doublecircle, fixedsize=true, width=2.5]; \"input_system\" [label = \"Input system\"];"); 2728 2729 dtrace_dot( 2730 "\"input_system\"->\"%s\" [label = \"%s\"];", 2731 dot_id_input_bin, debug_stream_format2str(pg_inst.stream_format)); 2732 2733 dtrace_dot( 2734 "node [shape = doublecircle, fixedsize=true, width=2.5]; \"sensor\" [label = \"Sensor\"];"); 2735 2736 dtrace_dot( 2737 "\"sensor\"->\"input_system\" [label = \"%s\\n%d x %d\\n(%d x %d)\"];", 2738 debug_stream_format2str(pg_inst.stream_format), 2739 pg_inst.width, pg_inst.height, 2740 pg_inst.eff_width, pg_inst.eff_height); 2741 } 2742 2743 dtrace_dot("}"); 2744 2745 /* Reset temp strings */ 2746 memset(dot_id_input_bin, 0, sizeof(dot_id_input_bin)); 2747 memset(ring_buffer, 0, sizeof(ring_buffer)); 2748 2749 pg_inst.do_init = true; 2750 pg_inst.width = 0; 2751 pg_inst.height = 0; 2752 pg_inst.eff_width = 0; 2753 pg_inst.eff_height = 0; 2754 pg_inst.stream_format = N_ATOMISP_INPUT_FORMAT; 2755 } 2756 2757 void 2758 ia_css_debug_pipe_graph_dump_stage( 2759 struct ia_css_pipeline_stage *stage, 2760 enum ia_css_pipe_id id) 2761 { 2762 char blob_name[SH_CSS_MAX_BINARY_NAME + 10] = "<unknown type>"; 2763 char const *bin_type = "<unknown type>"; 2764 int i; 2765 2766 assert(stage); 2767 if (stage->sp_func != IA_CSS_PIPELINE_NO_FUNC) 2768 return; 2769 2770 if (pg_inst.do_init) { 2771 ia_css_debug_pipe_graph_dump_prologue(); 2772 pg_inst.do_init = false; 2773 } 2774 2775 if (stage->binary) { 2776 bin_type = "binary"; 2777 if (stage->binary->info->blob) 2778 snprintf(blob_name, sizeof(blob_name), "%s_stage%d", 2779 stage->binary->info->blob->name, stage->stage_num); 2780 } else if (stage->firmware) { 2781 bin_type = "firmware"; 2782 strncpy_s(blob_name, sizeof(blob_name), 2783 IA_CSS_EXT_ISP_PROG_NAME(stage->firmware), sizeof(blob_name)); 2784 } 2785 2786 /* Guard in case of binaries that don't have any binary_info */ 2787 if (stage->binary_info) { 2788 char enable_info1[100]; 2789 char enable_info2[100]; 2790 char enable_info3[100]; 2791 char enable_info[200]; 2792 struct ia_css_binary_info *bi = stage->binary_info; 2793 2794 /* Split it in 2 function-calls to keep the amount of 2795 * parameters per call "reasonable" 2796 */ 2797 snprintf(enable_info1, sizeof(enable_info1), 2798 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 2799 bi->enable.reduced_pipe ? "rp," : "", 2800 bi->enable.vf_veceven ? "vfve," : "", 2801 bi->enable.dis ? "dis," : "", 2802 bi->enable.dvs_envelope ? "dvse," : "", 2803 bi->enable.uds ? "uds," : "", 2804 bi->enable.dvs_6axis ? "dvs6," : "", 2805 bi->enable.block_output ? "bo," : "", 2806 bi->enable.ds ? "ds," : "", 2807 bi->enable.bayer_fir_6db ? "bf6," : "", 2808 bi->enable.raw_binning ? "rawb," : "", 2809 bi->enable.continuous ? "cont," : "", 2810 bi->enable.s3a ? "s3a," : "", 2811 bi->enable.fpnr ? "fpnr," : "", 2812 bi->enable.sc ? "sc," : "" 2813 ); 2814 2815 snprintf(enable_info2, sizeof(enable_info2), 2816 "%s%s%s%s%s%s%s%s%s%s%s", 2817 bi->enable.macc ? "macc," : "", 2818 bi->enable.output ? "outp," : "", 2819 bi->enable.ref_frame ? "reff," : "", 2820 bi->enable.tnr ? "tnr," : "", 2821 bi->enable.xnr ? "xnr," : "", 2822 bi->enable.params ? "par," : "", 2823 bi->enable.ca_gdc ? "cagdc," : "", 2824 bi->enable.isp_addresses ? "ispa," : "", 2825 bi->enable.in_frame ? "inf," : "", 2826 bi->enable.out_frame ? "outf," : "", 2827 bi->enable.high_speed ? "hs," : "" 2828 ); 2829 2830 /* And merge them into one string */ 2831 snprintf(enable_info, sizeof(enable_info), "%s%s", 2832 enable_info1, enable_info2); 2833 { 2834 int l, p; 2835 char *ei = enable_info; 2836 2837 l = strlen(ei); 2838 2839 /* Replace last ',' with \0 if present */ 2840 if (l && enable_info[l - 1] == ',') 2841 enable_info[--l] = '\0'; 2842 2843 if (l > ENABLE_LINE_MAX_LENGTH) { 2844 /* Too big for one line, find last comma */ 2845 p = ENABLE_LINE_MAX_LENGTH; 2846 while (ei[p] != ',') 2847 p--; 2848 /* Last comma found, copy till that comma */ 2849 strncpy_s(enable_info1, 2850 sizeof(enable_info1), 2851 ei, p); 2852 enable_info1[p] = '\0'; 2853 2854 ei += p + 1; 2855 l = strlen(ei); 2856 2857 if (l <= ENABLE_LINE_MAX_LENGTH) { 2858 /* The 2nd line fits */ 2859 /* we cannot use ei as argument because 2860 * it is not guaranteed dword aligned 2861 */ 2862 strncpy_s(enable_info2, 2863 sizeof(enable_info2), 2864 ei, l); 2865 enable_info2[l] = '\0'; 2866 snprintf(enable_info, sizeof(enable_info), "%s\\n%s", 2867 enable_info1, enable_info2); 2868 2869 } else { 2870 /* 2nd line is still too long */ 2871 p = ENABLE_LINE_MAX_LENGTH; 2872 while (ei[p] != ',') 2873 p--; 2874 strncpy_s(enable_info2, 2875 sizeof(enable_info2), 2876 ei, p); 2877 enable_info2[p] = '\0'; 2878 ei += p + 1; 2879 l = strlen(ei); 2880 2881 if (l <= ENABLE_LINE_MAX_LENGTH) { 2882 /* The 3rd line fits */ 2883 /* we cannot use ei as argument because 2884 * it is not guaranteed dword aligned 2885 */ 2886 strcpy_s(enable_info3, 2887 sizeof(enable_info3), ei); 2888 enable_info3[l] = '\0'; 2889 snprintf(enable_info, sizeof(enable_info), 2890 "%s\\n%s\\n%s", 2891 enable_info1, enable_info2, 2892 enable_info3); 2893 } else { 2894 /* 3rd line is still too long */ 2895 p = ENABLE_LINE_MAX_LENGTH; 2896 while (ei[p] != ',') 2897 p--; 2898 strncpy_s(enable_info3, 2899 sizeof(enable_info3), 2900 ei, p); 2901 enable_info3[p] = '\0'; 2902 ei += p + 1; 2903 strcpy_s(enable_info3, 2904 sizeof(enable_info3), ei); 2905 snprintf(enable_info, sizeof(enable_info), 2906 "%s\\n%s\\n%s", 2907 enable_info1, enable_info2, 2908 enable_info3); 2909 } 2910 } 2911 } 2912 } 2913 2914 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\\n\\n%s\"]; \"%s(pipe%d)\"", 2915 bin_type, blob_name, enable_info, blob_name, id); 2916 } else { 2917 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\\n\"]; \"%s(pipe%d)\"", 2918 bin_type, blob_name, blob_name, id); 2919 } 2920 2921 if (stage->stage_num == 0) { 2922 /* 2923 * There are some implicite assumptions about which bin is the 2924 * input binary e.g. which one is connected to the input system 2925 * Priority: 2926 * 1) sp_raw_copy bin has highest priority 2927 * 2) First stage==0 binary of preview, video or capture 2928 */ 2929 if (strlen(dot_id_input_bin) == 0) { 2930 snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), 2931 "%s(pipe%d)", blob_name, id); 2932 } 2933 } 2934 2935 if (stage->args.in_frame) { 2936 ia_css_debug_pipe_graph_dump_frame( 2937 stage->args.in_frame, id, blob_name, 2938 "in", true); 2939 } 2940 2941 for (i = 0; i < NUM_TNR_FRAMES; i++) { 2942 if (stage->args.tnr_frames[i]) { 2943 ia_css_debug_pipe_graph_dump_frame( 2944 stage->args.tnr_frames[i], id, 2945 blob_name, "tnr_frame", true); 2946 } 2947 } 2948 2949 for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) { 2950 if (stage->args.delay_frames[i]) { 2951 ia_css_debug_pipe_graph_dump_frame( 2952 stage->args.delay_frames[i], id, 2953 blob_name, "delay_frame", true); 2954 } 2955 } 2956 2957 for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { 2958 if (stage->args.out_frame[i]) { 2959 ia_css_debug_pipe_graph_dump_frame( 2960 stage->args.out_frame[i], id, blob_name, 2961 "out", false); 2962 } 2963 } 2964 2965 if (stage->args.out_vf_frame) { 2966 ia_css_debug_pipe_graph_dump_frame( 2967 stage->args.out_vf_frame, id, blob_name, 2968 "out_vf", false); 2969 } 2970 } 2971 2972 void 2973 ia_css_debug_pipe_graph_dump_sp_raw_copy( 2974 struct ia_css_frame *out_frame) 2975 { 2976 assert(out_frame); 2977 if (pg_inst.do_init) { 2978 ia_css_debug_pipe_graph_dump_prologue(); 2979 pg_inst.do_init = false; 2980 } 2981 2982 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\"]; \"%s(pipe%d)\"", 2983 "sp-binary", "sp_raw_copy", "sp_raw_copy", 1); 2984 2985 snprintf(ring_buffer, sizeof(ring_buffer), 2986 "node [shape = box, fixedsize=true, width=2, height=0.7]; \"%p\" [label = \"%s\\n%d(%d) x %d\\nRingbuffer\"];", 2987 out_frame, 2988 debug_frame_format2str(out_frame->info.format), 2989 out_frame->info.res.width, 2990 out_frame->info.padded_width, 2991 out_frame->info.res.height); 2992 2993 dtrace_dot(ring_buffer); 2994 2995 dtrace_dot( 2996 "\"%s(pipe%d)\"->\"%p\" [label = out_frame];", 2997 "sp_raw_copy", 1, out_frame); 2998 2999 snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), "%s(pipe%d)", 3000 "sp_raw_copy", 1); 3001 } 3002 3003 void 3004 ia_css_debug_pipe_graph_dump_stream_config( 3005 const struct ia_css_stream_config *stream_config) 3006 { 3007 pg_inst.width = stream_config->input_config.input_res.width; 3008 pg_inst.height = stream_config->input_config.input_res.height; 3009 pg_inst.eff_width = stream_config->input_config.effective_res.width; 3010 pg_inst.eff_height = stream_config->input_config.effective_res.height; 3011 pg_inst.stream_format = stream_config->input_config.format; 3012 } 3013 3014 void 3015 ia_css_debug_dump_resolution( 3016 const struct ia_css_resolution *res, 3017 const char *label) 3018 { 3019 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s: =%d x =%d\n", 3020 label, res->width, res->height); 3021 } 3022 3023 void 3024 ia_css_debug_dump_frame_info( 3025 const struct ia_css_frame_info *info, 3026 const char *label) 3027 { 3028 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", label); 3029 ia_css_debug_dump_resolution(&info->res, "res"); 3030 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "padded_width: %d\n", 3031 info->padded_width); 3032 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", info->format); 3033 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bit_depth: %d\n", 3034 info->raw_bit_depth); 3035 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bayer_order: %d\n", 3036 info->raw_bayer_order); 3037 } 3038 3039 void 3040 ia_css_debug_dump_capture_config( 3041 const struct ia_css_capture_config *config) 3042 { 3043 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__); 3044 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); 3045 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_xnr: %d\n", 3046 config->enable_xnr); 3047 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_raw_output: %d\n", 3048 config->enable_raw_output); 3049 } 3050 3051 void 3052 ia_css_debug_dump_pipe_extra_config( 3053 const struct ia_css_pipe_extra_config *extra_config) 3054 { 3055 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__); 3056 if (extra_config) { 3057 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3058 "enable_raw_binning: %d\n", 3059 extra_config->enable_raw_binning); 3060 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_yuv_ds: %d\n", 3061 extra_config->enable_yuv_ds); 3062 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3063 "enable_high_speed: %d\n", 3064 extra_config->enable_high_speed); 3065 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3066 "enable_dvs_6axis: %d\n", 3067 extra_config->enable_dvs_6axis); 3068 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3069 "enable_reduced_pipe: %d\n", 3070 extra_config->enable_reduced_pipe); 3071 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3072 "enable_fractional_ds: %d\n", 3073 extra_config->enable_fractional_ds); 3074 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "disable_vf_pp: %d\n", 3075 extra_config->disable_vf_pp); 3076 } 3077 } 3078 3079 void 3080 ia_css_debug_dump_pipe_config( 3081 const struct ia_css_pipe_config *config) 3082 { 3083 unsigned int i; 3084 3085 IA_CSS_ENTER_PRIVATE("config = %p", config); 3086 if (!config) { 3087 IA_CSS_ERROR("NULL input parameter"); 3088 IA_CSS_LEAVE_PRIVATE(""); 3089 return; 3090 } 3091 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); 3092 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "isp_pipe_version: %d\n", 3093 config->isp_pipe_version); 3094 ia_css_debug_dump_resolution(&config->bayer_ds_out_res, 3095 "bayer_ds_out_res"); 3096 ia_css_debug_dump_resolution(&config->capt_pp_in_res, 3097 "capt_pp_in_res"); 3098 ia_css_debug_dump_resolution(&config->vf_pp_in_res, "vf_pp_in_res"); 3099 3100 if (atomisp_hw_is_isp2401) { 3101 ia_css_debug_dump_resolution(&config->output_system_in_res, 3102 "output_system_in_res"); 3103 } 3104 ia_css_debug_dump_resolution(&config->dvs_crop_out_res, 3105 "dvs_crop_out_res"); 3106 for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { 3107 ia_css_debug_dump_frame_info(&config->output_info[i], "output_info"); 3108 ia_css_debug_dump_frame_info(&config->vf_output_info[i], 3109 "vf_output_info"); 3110 } 3111 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "acc_extension: %p\n", 3112 config->acc_extension); 3113 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_acc_stages: %d\n", 3114 config->num_acc_stages); 3115 ia_css_debug_dump_capture_config(&config->default_capture_config); 3116 ia_css_debug_dump_resolution(&config->dvs_envelope, "dvs_envelope"); 3117 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "dvs_frame_delay: %d\n", 3118 config->dvs_frame_delay); 3119 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "acc_num_execs: %d\n", 3120 config->acc_num_execs); 3121 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_dz: %d\n", 3122 config->enable_dz); 3123 IA_CSS_LEAVE_PRIVATE(""); 3124 } 3125 3126 void 3127 ia_css_debug_dump_stream_config_source( 3128 const struct ia_css_stream_config *config) 3129 { 3130 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); 3131 switch (config->mode) { 3132 case IA_CSS_INPUT_MODE_SENSOR: 3133 case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: 3134 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.port\n"); 3135 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "port: %d\n", 3136 config->source.port.port); 3137 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_lanes: %d\n", 3138 config->source.port.num_lanes); 3139 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "timeout: %d\n", 3140 config->source.port.timeout); 3141 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "compression: %d\n", 3142 config->source.port.compression.type); 3143 break; 3144 case IA_CSS_INPUT_MODE_TPG: 3145 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.tpg\n"); 3146 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n", 3147 config->source.tpg.id); 3148 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", 3149 config->source.tpg.mode); 3150 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_mask: 0x%x\n", 3151 config->source.tpg.x_mask); 3152 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_delta: %d\n", 3153 config->source.tpg.x_delta); 3154 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_mask: 0x%x\n", 3155 config->source.tpg.y_mask); 3156 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_delta: %d\n", 3157 config->source.tpg.y_delta); 3158 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "xy_mask: 0x%x\n", 3159 config->source.tpg.xy_mask); 3160 break; 3161 case IA_CSS_INPUT_MODE_PRBS: 3162 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.prbs\n"); 3163 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n", 3164 config->source.prbs.id); 3165 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "h_blank: %d\n", 3166 config->source.prbs.h_blank); 3167 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "v_blank: %d\n", 3168 config->source.prbs.v_blank); 3169 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed: 0x%x\n", 3170 config->source.prbs.seed); 3171 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed1: 0x%x\n", 3172 config->source.prbs.seed1); 3173 break; 3174 default: 3175 case IA_CSS_INPUT_MODE_FIFO: 3176 case IA_CSS_INPUT_MODE_MEMORY: 3177 break; 3178 } 3179 } 3180 3181 void 3182 ia_css_debug_dump_mipi_buffer_config( 3183 const struct ia_css_mipi_buffer_config *config) 3184 { 3185 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); 3186 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "size_mem_words: %d\n", 3187 config->size_mem_words); 3188 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "nof_mipi_buffers: %d\n", 3189 config->nof_mipi_buffers); 3190 } 3191 3192 void 3193 ia_css_debug_dump_metadata_config( 3194 const struct ia_css_metadata_config *config) 3195 { 3196 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); 3197 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "data_type: %d\n", 3198 config->data_type); 3199 ia_css_debug_dump_resolution(&config->resolution, "resolution"); 3200 } 3201 3202 void 3203 ia_css_debug_dump_stream_config( 3204 const struct ia_css_stream_config *config, 3205 int num_pipes) 3206 { 3207 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); 3208 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_pipes: %d\n", num_pipes); 3209 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); 3210 ia_css_debug_dump_stream_config_source(config); 3211 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "channel_id: %d\n", 3212 config->channel_id); 3213 ia_css_debug_dump_resolution(&config->input_config.input_res, "input_res"); 3214 ia_css_debug_dump_resolution(&config->input_config.effective_res, 3215 "effective_res"); 3216 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", 3217 config->input_config.format); 3218 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "bayer_order: %d\n", 3219 config->input_config.bayer_order); 3220 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sensor_binning_factor: %d\n", 3221 config->sensor_binning_factor); 3222 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pixels_per_clock: %d\n", 3223 config->pixels_per_clock); 3224 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "online: %d\n", 3225 config->online); 3226 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "init_num_cont_raw_buf: %d\n", 3227 config->init_num_cont_raw_buf); 3228 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3229 "target_num_cont_raw_buf: %d\n", 3230 config->target_num_cont_raw_buf); 3231 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pack_raw_pixels: %d\n", 3232 config->pack_raw_pixels); 3233 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "continuous: %d\n", 3234 config->continuous); 3235 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "flash_gpio_pin: %d\n", 3236 config->flash_gpio_pin); 3237 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "left_padding: %d\n", 3238 config->left_padding); 3239 ia_css_debug_dump_mipi_buffer_config(&config->mipi_buffer_config); 3240 ia_css_debug_dump_metadata_config(&config->metadata_config); 3241 } 3242 3243 /* 3244 Trace support. 3245 3246 This tracer is using a buffer to trace the flow of the FW and dump misc values (see below for details). 3247 Currently, support is only for SKC. 3248 To enable support for other platforms: 3249 - Allocate a buffer for tracing in DMEM. The longer the better. 3250 - Use the DBG_init routine in sp.hive.c to initiatilize the tracer with the address and size selected. 3251 - Add trace points in the SP code wherever needed. 3252 - Enable the dump below with the required address and required adjustments. 3253 Dump is called at the end of ia_css_debug_dump_sp_state(). 3254 */ 3255 3256 /* 3257 dump_trace() : dump the trace points from DMEM2. 3258 for every trace point, the following are printed: index, major:minor and the 16-bit attached value. 3259 The routine looks for the first 0, and then prints from it cyclically. 3260 Data forma in DMEM2: 3261 first 4 DWORDS: header 3262 DWORD 0: data description 3263 byte 0: version 3264 byte 1: number of threads (for future use) 3265 byte 2+3: number ot TPs 3266 DWORD 1: command byte + data (for future use) 3267 byte 0: command 3268 byte 1-3: command signature 3269 DWORD 2-3: additional data (for future use) 3270 Following data is 4-byte oriented: 3271 byte 0: major 3272 byte 1: minor 3273 byte 2-3: data 3274 */ 3275 #if TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP 3276 #ifndef ISP2401 3277 static void debug_dump_one_trace(TRACE_CORE_ID proc_id) 3278 #else 3279 static void debug_dump_one_trace(enum TRACE_CORE_ID proc_id) 3280 #endif 3281 { 3282 #if defined(HAS_TRACER_V2) 3283 u32 start_addr; 3284 u32 start_addr_data; 3285 u32 item_size; 3286 #ifndef ISP2401 3287 u32 tmp; 3288 #else 3289 u8 tid_val; 3290 enum TRACE_DUMP_FORMAT dump_format; 3291 #endif 3292 int i, j, max_trace_points, point_num, limit = -1; 3293 /* using a static buffer here as the driver has issues allocating memory */ 3294 static u32 trace_read_buf[TRACE_BUFF_SIZE] = {0}; 3295 static struct trace_header_t header; 3296 u8 *header_arr; 3297 3298 /* read the header and parse it */ 3299 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "~~~ Tracer "); 3300 switch (proc_id) { 3301 case TRACE_SP0_ID: 3302 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP0"); 3303 start_addr = TRACE_SP0_ADDR; 3304 start_addr_data = TRACE_SP0_DATA_ADDR; 3305 item_size = TRACE_SP0_ITEM_SIZE; 3306 max_trace_points = TRACE_SP0_MAX_POINTS; 3307 break; 3308 case TRACE_SP1_ID: 3309 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP1"); 3310 start_addr = TRACE_SP1_ADDR; 3311 start_addr_data = TRACE_SP1_DATA_ADDR; 3312 item_size = TRACE_SP1_ITEM_SIZE; 3313 max_trace_points = TRACE_SP1_MAX_POINTS; 3314 break; 3315 case TRACE_ISP_ID: 3316 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ISP"); 3317 start_addr = TRACE_ISP_ADDR; 3318 start_addr_data = TRACE_ISP_DATA_ADDR; 3319 item_size = TRACE_ISP_ITEM_SIZE; 3320 max_trace_points = TRACE_ISP_MAX_POINTS; 3321 break; 3322 default: 3323 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3324 "\t\ttraces are not supported for this processor ID - exiting\n"); 3325 return; 3326 } 3327 3328 if (!atomisp_hw_is_isp2401) { 3329 tmp = ia_css_device_load_uint32(start_addr); 3330 point_num = (tmp >> 16) & 0xFFFF; 3331 3332 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", tmp & 0xFF, 3333 point_num); 3334 } else { 3335 /* Loading byte-by-byte as using the master routine had issues */ 3336 header_arr = (uint8_t *)&header; 3337 for (i = 0; i < (int)sizeof(struct trace_header_t); i++) 3338 header_arr[i] = ia_css_device_load_uint8(start_addr + (i)); 3339 3340 point_num = header.max_tracer_points; 3341 3342 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", header.version, 3343 point_num); 3344 3345 tmp = header.version; 3346 } 3347 if ((tmp & 0xFF) != TRACER_VER) { 3348 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tUnknown version - exiting\n"); 3349 return; 3350 } 3351 if (point_num > max_trace_points) { 3352 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tToo many points - exiting\n"); 3353 return; 3354 } 3355 /* copy the TPs and find the first 0 */ 3356 for (i = 0; i < point_num; i++) { 3357 trace_read_buf[i] = ia_css_device_load_uint32(start_addr_data + 3358 (i * item_size)); 3359 if ((limit == (-1)) && (trace_read_buf[i] == 0)) 3360 limit = i; 3361 } 3362 if (atomisp_hw_is_isp2401) { 3363 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Status:\n"); 3364 for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) 3365 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3366 "\tT%d: %3d (%02x) %6d (%04x) %10d (%08x)\n", i, 3367 header.thr_status_byte[i], header.thr_status_byte[i], 3368 header.thr_status_word[i], header.thr_status_word[i], 3369 header.thr_status_dword[i], header.thr_status_dword[i]); 3370 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Scratch:\n"); 3371 for (i = 0; i < MAX_SCRATCH_DATA; i++) 3372 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%10d (%08x) ", 3373 header.scratch_debug[i], header.scratch_debug[i]); 3374 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\n"); 3375 } 3376 /* two 0s in the beginning: empty buffer */ 3377 if ((trace_read_buf[0] == 0) && (trace_read_buf[1] == 0)) { 3378 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tEmpty tracer - exiting\n"); 3379 return; 3380 } 3381 /* no overrun: start from 0 */ 3382 if ((limit == point_num - 1) || 3383 /* first 0 is at the end - border case */ 3384 (trace_read_buf[limit + 1] == 3385 0)) /* did not make a full cycle after the memset */ 3386 limit = 0; 3387 /* overrun: limit is the first non-zero after the first zero */ 3388 else 3389 limit++; 3390 3391 /* print the TPs */ 3392 for (i = 0; i < point_num; i++) { 3393 j = (limit + i) % point_num; 3394 if (trace_read_buf[j]) { 3395 if (!atomisp_hw_is_isp2401) { 3396 TRACE_DUMP_FORMAT dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]); 3397 } else { 3398 tid_val = FIELD_TID_UNPACK(trace_read_buf[j]); 3399 dump_format = TRACE_DUMP_FORMAT_POINT; 3400 3401 /* 3402 * When tid value is 111b, the data will be interpreted differently: 3403 * tid val is ignored, major field contains 2 bits (msb) for format type 3404 */ 3405 if (tid_val == FIELD_TID_SEL_FORMAT_PAT) { 3406 dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]); 3407 } 3408 } 3409 switch (dump_format) { 3410 case TRACE_DUMP_FORMAT_POINT: 3411 ia_css_debug_dtrace( 3412 IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %d\n", 3413 j, FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3414 FIELD_MINOR_UNPACK(trace_read_buf[j]), 3415 FIELD_VALUE_UNPACK(trace_read_buf[j])); 3416 break; 3417 /* ISP2400 */ 3418 case TRACE_DUMP_FORMAT_VALUE24_HEX: 3419 ia_css_debug_dtrace( 3420 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x H\n", 3421 j, 3422 FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3423 FIELD_VALUE_24_UNPACK(trace_read_buf[j])); 3424 break; 3425 /* ISP2400 */ 3426 case TRACE_DUMP_FORMAT_VALUE24_DEC: 3427 ia_css_debug_dtrace( 3428 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %d D\n", 3429 j, 3430 FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3431 FIELD_VALUE_24_UNPACK(trace_read_buf[j])); 3432 break; 3433 /* ISP2401 */ 3434 case TRACE_DUMP_FORMAT_POINT_NO_TID: 3435 ia_css_debug_dtrace( 3436 IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %x (%d)\n", 3437 j, 3438 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]), 3439 FIELD_MINOR_UNPACK(trace_read_buf[j]), 3440 FIELD_VALUE_UNPACK(trace_read_buf[j]), 3441 FIELD_VALUE_UNPACK(trace_read_buf[j])); 3442 break; 3443 /* ISP2401 */ 3444 case TRACE_DUMP_FORMAT_VALUE24: 3445 ia_css_debug_dtrace( 3446 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x (%d)\n", 3447 j, 3448 FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3449 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]), 3450 FIELD_VALUE_24_UNPACK(trace_read_buf[j]), 3451 FIELD_VALUE_24_UNPACK(trace_read_buf[j])); 3452 break; 3453 case TRACE_DUMP_FORMAT_VALUE24_TIMING: 3454 ia_css_debug_dtrace( 3455 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing %x\n", 3456 j, 3457 FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3458 FIELD_VALUE_24_UNPACK(trace_read_buf[j])); 3459 break; 3460 case TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA: 3461 ia_css_debug_dtrace( 3462 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing delta %x\n", 3463 j, 3464 FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3465 FIELD_VALUE_24_UNPACK(trace_read_buf[j])); 3466 break; 3467 default: 3468 ia_css_debug_dtrace( 3469 IA_CSS_DEBUG_TRACE, 3470 "no such trace dump format %d", 3471 dump_format); 3472 break; 3473 } 3474 } 3475 } 3476 #else 3477 (void)proc_id; 3478 #endif /* HAS_TRACER_V2 */ 3479 } 3480 #endif /* TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP */ 3481 3482 void ia_css_debug_dump_trace(void) 3483 { 3484 #if TRACE_ENABLE_SP0 3485 debug_dump_one_trace(TRACE_SP0_ID); 3486 #endif 3487 #if TRACE_ENABLE_SP1 3488 debug_dump_one_trace(TRACE_SP1_ID); 3489 #endif 3490 #if TRACE_ENABLE_ISP 3491 debug_dump_one_trace(TRACE_ISP_ID); 3492 #endif 3493 } 3494 3495 #if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) 3496 /* Tagger state dump function. The tagger is only available when the CSS 3497 * contains an input system (2400 or 2401). */ 3498 void ia_css_debug_tagger_state(void) 3499 { 3500 unsigned int i; 3501 unsigned int HIVE_ADDR_tagger_frames; 3502 ia_css_tagger_buf_sp_elem_t tbuf_frames[MAX_CB_ELEMS_FOR_TAGGER]; 3503 3504 HIVE_ADDR_tagger_frames = sh_css_sp_fw.info.sp.tagger_frames_addr; 3505 3506 /* This variable is not used in crun */ 3507 (void)HIVE_ADDR_tagger_frames; 3508 3509 /* 2400 and 2401 only have 1 SP, so the tagger lives on SP0 */ 3510 sp_dmem_load(SP0_ID, 3511 (unsigned int)sp_address_of(tagger_frames), 3512 tbuf_frames, 3513 sizeof(tbuf_frames)); 3514 3515 ia_css_debug_dtrace(2, "Tagger Info:\n"); 3516 for (i = 0; i < MAX_CB_ELEMS_FOR_TAGGER; i++) { 3517 ia_css_debug_dtrace(2, "\t tagger frame[%d]: exp_id=%d, marked=%d, locked=%d\n", 3518 i, tbuf_frames[i].exp_id, tbuf_frames[i].mark, tbuf_frames[i].lock); 3519 } 3520 } 3521 #endif /* defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) */ 3522 3523 /* ISP2401 */ 3524 void ia_css_debug_pc_dump(sp_ID_t id, unsigned int num_of_dumps) 3525 { 3526 unsigned int pc; 3527 unsigned int i; 3528 hrt_data sc = sp_ctrl_load(id, SP_SC_REG); 3529 3530 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Status reg: 0x%X\n", id, sc); 3531 sc = sp_ctrl_load(id, SP_CTRL_SINK_REG); 3532 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Stall reg: 0x%X\n", id, sc); 3533 for (i = 0; i < num_of_dumps; i++) { 3534 pc = sp_ctrl_load(id, SP_PC_REG); 3535 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d PC: 0x%X\n", id, pc); 3536 } 3537 } 3538