1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #include "debug.h" 17 18 #ifndef __INLINE_INPUT_SYSTEM__ 19 #define __INLINE_INPUT_SYSTEM__ 20 #endif 21 #ifndef __INLINE_IBUF_CTRL__ 22 #define __INLINE_IBUF_CTRL__ 23 #endif 24 #ifndef __INLINE_CSI_RX__ 25 #define __INLINE_CSI_RX__ 26 #endif 27 #ifndef __INLINE_PIXELGEN__ 28 #define __INLINE_PIXELGEN__ 29 #endif 30 #ifndef __INLINE_STREAM2MMIO__ 31 #define __INLINE_STREAM2MMIO__ 32 #endif 33 34 #include <linux/string.h> /* for strscpy() */ 35 36 #include "ia_css_debug.h" 37 #include "ia_css_debug_pipe.h" 38 #include "ia_css_irq.h" 39 #include "ia_css_stream.h" 40 #include "ia_css_pipeline.h" 41 #include "ia_css_isp_param.h" 42 #include "sh_css_params.h" 43 #include "ia_css_bufq.h" 44 /* ISP2401 */ 45 #include "ia_css_queue.h" 46 47 #include "ia_css_isp_params.h" 48 49 #include "system_local.h" 50 #include "assert_support.h" 51 #include "print_support.h" 52 53 #include "fifo_monitor.h" 54 55 #include "input_formatter.h" 56 #include "dma.h" 57 #include "irq.h" 58 #include "gp_device.h" 59 #include "sp.h" 60 #include "isp.h" 61 #include "type_support.h" 62 #include "math_support.h" /* CEIL_DIV */ 63 #include "input_system.h" /* input_formatter_reg_load */ 64 #include "ia_css_tagger_common.h" 65 66 #include "sh_css_internal.h" 67 #include "ia_css_isys.h" 68 #include "sh_css_sp.h" /* sh_css_sp_get_debug_state() */ 69 70 #include "css_trace.h" /* tracer */ 71 72 #include "device_access.h" /* for ia_css_device_load_uint32 */ 73 74 /* Include all kernel host interfaces for ISP1 */ 75 #include "anr/anr_1.0/ia_css_anr.host.h" 76 #include "cnr/cnr_1.0/ia_css_cnr.host.h" 77 #include "csc/csc_1.0/ia_css_csc.host.h" 78 #include "de/de_1.0/ia_css_de.host.h" 79 #include "dp/dp_1.0/ia_css_dp.host.h" 80 #include "bnr/bnr_1.0/ia_css_bnr.host.h" 81 #include "fpn/fpn_1.0/ia_css_fpn.host.h" 82 #include "gc/gc_1.0/ia_css_gc.host.h" 83 #include "ob/ob_1.0/ia_css_ob.host.h" 84 #include "s3a/s3a_1.0/ia_css_s3a.host.h" 85 #include "sc/sc_1.0/ia_css_sc.host.h" 86 #include "tnr/tnr_1.0/ia_css_tnr.host.h" 87 #include "uds/uds_1.0/ia_css_uds_param.h" 88 #include "wb/wb_1.0/ia_css_wb.host.h" 89 #include "ynr/ynr_1.0/ia_css_ynr.host.h" 90 91 /* Include additional kernel host interfaces for ISP2 */ 92 #include "aa/aa_2/ia_css_aa2.host.h" 93 #include "anr/anr_2/ia_css_anr2.host.h" 94 #include "cnr/cnr_2/ia_css_cnr2.host.h" 95 #include "de/de_2/ia_css_de2.host.h" 96 #include "gc/gc_2/ia_css_gc2.host.h" 97 #include "ynr/ynr_2/ia_css_ynr2.host.h" 98 99 #define DPG_START "ia_css_debug_pipe_graph_dump_start " 100 #define DPG_END " ia_css_debug_pipe_graph_dump_end\n" 101 102 #define ENABLE_LINE_MAX_LENGTH (25) 103 104 /* 105 * TODO:SH_CSS_MAX_SP_THREADS is not the max number of sp threads 106 * future rework should fix this and remove the define MAX_THREAD_NUM 107 */ 108 #define MAX_THREAD_NUM (SH_CSS_MAX_SP_THREADS + SH_CSS_MAX_SP_INTERNAL_THREADS) 109 110 static struct pipe_graph_class { 111 bool do_init; 112 int height; 113 int width; 114 int eff_height; 115 int eff_width; 116 enum atomisp_input_format stream_format; 117 } pg_inst = {true, 0, 0, 0, 0, N_ATOMISP_INPUT_FORMAT}; 118 119 static const char *const queue_id_to_str[] = { 120 /* [SH_CSS_QUEUE_A_ID] =*/ "queue_A", 121 /* [SH_CSS_QUEUE_B_ID] =*/ "queue_B", 122 /* [SH_CSS_QUEUE_C_ID] =*/ "queue_C", 123 /* [SH_CSS_QUEUE_D_ID] =*/ "queue_D", 124 /* [SH_CSS_QUEUE_E_ID] =*/ "queue_E", 125 /* [SH_CSS_QUEUE_F_ID] =*/ "queue_F", 126 /* [SH_CSS_QUEUE_G_ID] =*/ "queue_G", 127 /* [SH_CSS_QUEUE_H_ID] =*/ "queue_H" 128 }; 129 130 static const char *const pipe_id_to_str[] = { 131 /* [IA_CSS_PIPE_ID_PREVIEW] =*/ "preview", 132 /* [IA_CSS_PIPE_ID_COPY] =*/ "copy", 133 /* [IA_CSS_PIPE_ID_VIDEO] =*/ "video", 134 /* [IA_CSS_PIPE_ID_CAPTURE] =*/ "capture", 135 /* [IA_CSS_PIPE_ID_YUVPP] =*/ "yuvpp", 136 /* [IA_CSS_PIPE_ID_ACC] =*/ "accelerator" 137 }; 138 139 static char dot_id_input_bin[SH_CSS_MAX_BINARY_NAME + 10]; 140 static char ring_buffer[200]; 141 142 void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...) 143 { 144 va_list ap; 145 146 va_start(ap, fmt); 147 ia_css_debug_vdtrace(level, fmt, ap); 148 va_end(ap); 149 } 150 151 static void debug_dump_long_array_formatted( 152 const sp_ID_t sp_id, 153 hrt_address stack_sp_addr, 154 unsigned int stack_size) 155 { 156 unsigned int i; 157 u32 val; 158 u32 addr = (uint32_t)stack_sp_addr; 159 u32 stack_size_words = CEIL_DIV(stack_size, sizeof(uint32_t)); 160 161 /* When size is not multiple of four, last word is only relevant for 162 * remaining bytes */ 163 for (i = 0; i < stack_size_words; i++) { 164 val = sp_dmem_load_uint32(sp_id, (hrt_address)addr); 165 if ((i % 8) == 0) 166 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n"); 167 168 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "0x%08x ", val); 169 addr += sizeof(uint32_t); 170 } 171 172 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n"); 173 } 174 175 static void debug_dump_sp_stack_info( 176 const sp_ID_t sp_id) 177 { 178 const struct ia_css_fw_info *fw; 179 unsigned int HIVE_ADDR_sp_threads_stack; 180 unsigned int HIVE_ADDR_sp_threads_stack_size; 181 u32 stack_sizes[MAX_THREAD_NUM]; 182 u32 stack_sp_addr[MAX_THREAD_NUM]; 183 unsigned int i; 184 185 fw = &sh_css_sp_fw; 186 187 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "sp_id(%u) stack info\n", sp_id); 188 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 189 "from objects stack_addr_offset:0x%x stack_size_offset:0x%x\n", 190 fw->info.sp.threads_stack, 191 fw->info.sp.threads_stack_size); 192 193 HIVE_ADDR_sp_threads_stack = fw->info.sp.threads_stack; 194 HIVE_ADDR_sp_threads_stack_size = fw->info.sp.threads_stack_size; 195 196 if (fw->info.sp.threads_stack == 0 || 197 fw->info.sp.threads_stack_size == 0) 198 return; 199 200 (void)HIVE_ADDR_sp_threads_stack; 201 (void)HIVE_ADDR_sp_threads_stack_size; 202 203 sp_dmem_load(sp_id, 204 (unsigned int)sp_address_of(sp_threads_stack), 205 &stack_sp_addr, sizeof(stack_sp_addr)); 206 sp_dmem_load(sp_id, 207 (unsigned int)sp_address_of(sp_threads_stack_size), 208 &stack_sizes, sizeof(stack_sizes)); 209 210 for (i = 0 ; i < MAX_THREAD_NUM; i++) { 211 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 212 "thread: %u stack_addr: 0x%08x stack_size: %u\n", 213 i, stack_sp_addr[i], stack_sizes[i]); 214 debug_dump_long_array_formatted(sp_id, (hrt_address)stack_sp_addr[i], 215 stack_sizes[i]); 216 } 217 } 218 219 void ia_css_debug_dump_sp_stack_info(void) 220 { 221 debug_dump_sp_stack_info(SP0_ID); 222 } 223 224 void ia_css_debug_set_dtrace_level(const unsigned int trace_level) 225 { 226 dbg_level = trace_level; 227 return; 228 } 229 230 unsigned int ia_css_debug_get_dtrace_level(void) 231 { 232 return dbg_level; 233 } 234 235 static const char *debug_stream_format2str(const enum atomisp_input_format 236 stream_format) 237 { 238 switch (stream_format) { 239 case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY: 240 return "yuv420-8-legacy"; 241 case ATOMISP_INPUT_FORMAT_YUV420_8: 242 return "yuv420-8"; 243 case ATOMISP_INPUT_FORMAT_YUV420_10: 244 return "yuv420-10"; 245 case ATOMISP_INPUT_FORMAT_YUV420_16: 246 return "yuv420-16"; 247 case ATOMISP_INPUT_FORMAT_YUV422_8: 248 return "yuv422-8"; 249 case ATOMISP_INPUT_FORMAT_YUV422_10: 250 return "yuv422-10"; 251 case ATOMISP_INPUT_FORMAT_YUV422_16: 252 return "yuv422-16"; 253 case ATOMISP_INPUT_FORMAT_RGB_444: 254 return "rgb444"; 255 case ATOMISP_INPUT_FORMAT_RGB_555: 256 return "rgb555"; 257 case ATOMISP_INPUT_FORMAT_RGB_565: 258 return "rgb565"; 259 case ATOMISP_INPUT_FORMAT_RGB_666: 260 return "rgb666"; 261 case ATOMISP_INPUT_FORMAT_RGB_888: 262 return "rgb888"; 263 case ATOMISP_INPUT_FORMAT_RAW_6: 264 return "raw6"; 265 case ATOMISP_INPUT_FORMAT_RAW_7: 266 return "raw7"; 267 case ATOMISP_INPUT_FORMAT_RAW_8: 268 return "raw8"; 269 case ATOMISP_INPUT_FORMAT_RAW_10: 270 return "raw10"; 271 case ATOMISP_INPUT_FORMAT_RAW_12: 272 return "raw12"; 273 case ATOMISP_INPUT_FORMAT_RAW_14: 274 return "raw14"; 275 case ATOMISP_INPUT_FORMAT_RAW_16: 276 return "raw16"; 277 case ATOMISP_INPUT_FORMAT_BINARY_8: 278 return "binary8"; 279 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT1: 280 return "generic-short1"; 281 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT2: 282 return "generic-short2"; 283 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT3: 284 return "generic-short3"; 285 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT4: 286 return "generic-short4"; 287 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT5: 288 return "generic-short5"; 289 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT6: 290 return "generic-short6"; 291 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT7: 292 return "generic-short7"; 293 case ATOMISP_INPUT_FORMAT_GENERIC_SHORT8: 294 return "generic-short8"; 295 case ATOMISP_INPUT_FORMAT_YUV420_8_SHIFT: 296 return "yuv420-8-shift"; 297 case ATOMISP_INPUT_FORMAT_YUV420_10_SHIFT: 298 return "yuv420-10-shift"; 299 case ATOMISP_INPUT_FORMAT_EMBEDDED: 300 return "embedded-8"; 301 case ATOMISP_INPUT_FORMAT_USER_DEF1: 302 return "user-def-8-type-1"; 303 case ATOMISP_INPUT_FORMAT_USER_DEF2: 304 return "user-def-8-type-2"; 305 case ATOMISP_INPUT_FORMAT_USER_DEF3: 306 return "user-def-8-type-3"; 307 case ATOMISP_INPUT_FORMAT_USER_DEF4: 308 return "user-def-8-type-4"; 309 case ATOMISP_INPUT_FORMAT_USER_DEF5: 310 return "user-def-8-type-5"; 311 case ATOMISP_INPUT_FORMAT_USER_DEF6: 312 return "user-def-8-type-6"; 313 case ATOMISP_INPUT_FORMAT_USER_DEF7: 314 return "user-def-8-type-7"; 315 case ATOMISP_INPUT_FORMAT_USER_DEF8: 316 return "user-def-8-type-8"; 317 318 default: 319 assert(!"Unknown stream format"); 320 return "unknown-stream-format"; 321 } 322 }; 323 324 static const char *debug_frame_format2str(const enum ia_css_frame_format 325 frame_format) 326 { 327 switch (frame_format) { 328 case IA_CSS_FRAME_FORMAT_NV11: 329 return "NV11"; 330 case IA_CSS_FRAME_FORMAT_NV12: 331 return "NV12"; 332 case IA_CSS_FRAME_FORMAT_NV12_16: 333 return "NV12_16"; 334 case IA_CSS_FRAME_FORMAT_NV12_TILEY: 335 return "NV12_TILEY"; 336 case IA_CSS_FRAME_FORMAT_NV16: 337 return "NV16"; 338 case IA_CSS_FRAME_FORMAT_NV21: 339 return "NV21"; 340 case IA_CSS_FRAME_FORMAT_NV61: 341 return "NV61"; 342 case IA_CSS_FRAME_FORMAT_YV12: 343 return "YV12"; 344 case IA_CSS_FRAME_FORMAT_YV16: 345 return "YV16"; 346 case IA_CSS_FRAME_FORMAT_YUV420: 347 return "YUV420"; 348 case IA_CSS_FRAME_FORMAT_YUV420_16: 349 return "YUV420_16"; 350 case IA_CSS_FRAME_FORMAT_YUV422: 351 return "YUV422"; 352 case IA_CSS_FRAME_FORMAT_YUV422_16: 353 return "YUV422_16"; 354 case IA_CSS_FRAME_FORMAT_UYVY: 355 return "UYVY"; 356 case IA_CSS_FRAME_FORMAT_YUYV: 357 return "YUYV"; 358 case IA_CSS_FRAME_FORMAT_YUV444: 359 return "YUV444"; 360 case IA_CSS_FRAME_FORMAT_YUV_LINE: 361 return "YUV_LINE"; 362 case IA_CSS_FRAME_FORMAT_RAW: 363 return "RAW"; 364 case IA_CSS_FRAME_FORMAT_RGB565: 365 return "RGB565"; 366 case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: 367 return "PLANAR_RGB888"; 368 case IA_CSS_FRAME_FORMAT_RGBA888: 369 return "RGBA888"; 370 case IA_CSS_FRAME_FORMAT_QPLANE6: 371 return "QPLANE6"; 372 case IA_CSS_FRAME_FORMAT_BINARY_8: 373 return "BINARY_8"; 374 case IA_CSS_FRAME_FORMAT_MIPI: 375 return "MIPI"; 376 case IA_CSS_FRAME_FORMAT_RAW_PACKED: 377 return "RAW_PACKED"; 378 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: 379 return "CSI_MIPI_YUV420_8"; 380 case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: 381 return "CSI_MIPI_LEGACY_YUV420_8"; 382 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10: 383 return "CSI_MIPI_YUV420_10"; 384 385 default: 386 assert(!"Unknown frame format"); 387 return "unknown-frame-format"; 388 } 389 } 390 391 static void debug_print_sp_state(const sp_state_t *state, const char *cell) 392 { 393 assert(cell); 394 assert(state); 395 396 ia_css_debug_dtrace(2, "%s state:\n", cell); 397 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc); 398 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register", 399 state->status_register); 400 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken); 401 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle); 402 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping", 403 state->is_sleeping); 404 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling", 405 state->is_stalling); 406 return; 407 } 408 409 static void debug_print_isp_state(const isp_state_t *state, const char *cell) 410 { 411 assert(state); 412 assert(cell); 413 414 ia_css_debug_dtrace(2, "%s state:\n", cell); 415 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc); 416 ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register", 417 state->status_register); 418 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken); 419 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle); 420 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping", 421 state->is_sleeping); 422 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling", 423 state->is_stalling); 424 return; 425 } 426 427 void ia_css_debug_dump_isp_state(void) 428 { 429 isp_state_t state; 430 isp_stall_t stall; 431 432 isp_get_state(ISP0_ID, &state, &stall); 433 434 debug_print_isp_state(&state, "ISP"); 435 436 if (state.is_stalling) { 437 if (!IS_ISP2401) { 438 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 439 "[0] if_prim_a_FIFO stalled", stall.fifo0); 440 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 441 "[1] if_prim_b_FIFO stalled", stall.fifo1); 442 } 443 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[2] dma_FIFO stalled", 444 stall.fifo2); 445 446 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[3] gdc0_FIFO stalled", 447 stall.fifo3); 448 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[4] gdc1_FIFO stalled", 449 stall.fifo4); 450 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[5] gpio_FIFO stalled", 451 stall.fifo5); 452 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[6] sp_FIFO stalled", 453 stall.fifo6); 454 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 455 "status & control stalled", 456 stall.stat_ctrl); 457 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled", 458 stall.dmem); 459 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vmem stalled", 460 stall.vmem); 461 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem1 stalled", 462 stall.vamem1); 463 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem2 stalled", 464 stall.vamem2); 465 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem3 stalled", 466 stall.vamem3); 467 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "hmem stalled", 468 stall.hmem); 469 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "pmem stalled", 470 stall.pmem); 471 } 472 return; 473 } 474 475 void ia_css_debug_dump_sp_state(void) 476 { 477 sp_state_t state; 478 sp_stall_t stall; 479 480 sp_get_state(SP0_ID, &state, &stall); 481 debug_print_sp_state(&state, "SP"); 482 if (state.is_stalling) { 483 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isys_FIFO stalled", 484 stall.fifo0); 485 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "if_sec_FIFO stalled", 486 stall.fifo1); 487 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 488 "str_to_mem_FIFO stalled", stall.fifo2); 489 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dma_FIFO stalled", 490 stall.fifo3); 491 if (!IS_ISP2401) 492 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 493 "if_prim_a_FIFO stalled", stall.fifo4); 494 495 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isp_FIFO stalled", 496 stall.fifo5); 497 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gp_FIFO stalled", 498 stall.fifo6); 499 if (!IS_ISP2401) 500 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 501 "if_prim_b_FIFO stalled", stall.fifo7); 502 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc0_FIFO stalled", 503 stall.fifo8); 504 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc1_FIFO stalled", 505 stall.fifo9); 506 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "irq FIFO stalled", 507 stall.fifoa); 508 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled", 509 stall.dmem); 510 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 511 "control master stalled", 512 stall.control_master); 513 ia_css_debug_dtrace(2, "\t%-32s: %d\n", 514 "i-cache master stalled", 515 stall.icache_master); 516 } 517 ia_css_debug_dump_trace(); 518 return; 519 } 520 521 static void debug_print_fifo_channel_state(const fifo_channel_state_t *state, 522 const char *descr) 523 { 524 assert(state); 525 assert(descr); 526 527 ia_css_debug_dtrace(2, "FIFO channel: %s\n", descr); 528 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "source valid", 529 state->src_valid); 530 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo accept", 531 state->fifo_accept); 532 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo valid", 533 state->fifo_valid); 534 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "sink accept", 535 state->sink_accept); 536 return; 537 } 538 539 void ia_css_debug_dump_pif_a_isp_fifo_state(void) 540 { 541 fifo_channel_state_t pif_to_isp, isp_to_pif; 542 543 fifo_channel_get_state(FIFO_MONITOR0_ID, 544 FIFO_CHANNEL_IF0_TO_ISP0, &pif_to_isp); 545 fifo_channel_get_state(FIFO_MONITOR0_ID, 546 FIFO_CHANNEL_ISP0_TO_IF0, &isp_to_pif); 547 debug_print_fifo_channel_state(&pif_to_isp, "Primary IF A to ISP"); 548 debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF A"); 549 } 550 551 void ia_css_debug_dump_pif_b_isp_fifo_state(void) 552 { 553 fifo_channel_state_t pif_to_isp, isp_to_pif; 554 555 fifo_channel_get_state(FIFO_MONITOR0_ID, 556 FIFO_CHANNEL_IF1_TO_ISP0, &pif_to_isp); 557 fifo_channel_get_state(FIFO_MONITOR0_ID, 558 FIFO_CHANNEL_ISP0_TO_IF1, &isp_to_pif); 559 debug_print_fifo_channel_state(&pif_to_isp, "Primary IF B to ISP"); 560 debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF B"); 561 } 562 563 void ia_css_debug_dump_str2mem_sp_fifo_state(void) 564 { 565 fifo_channel_state_t s2m_to_sp, sp_to_s2m; 566 567 fifo_channel_get_state(FIFO_MONITOR0_ID, 568 FIFO_CHANNEL_STREAM2MEM0_TO_SP0, &s2m_to_sp); 569 fifo_channel_get_state(FIFO_MONITOR0_ID, 570 FIFO_CHANNEL_SP0_TO_STREAM2MEM0, &sp_to_s2m); 571 debug_print_fifo_channel_state(&s2m_to_sp, "Stream-to-memory to SP"); 572 debug_print_fifo_channel_state(&sp_to_s2m, "SP to stream-to-memory"); 573 } 574 575 #ifndef ISP2401 576 static void debug_print_if_state(input_formatter_state_t *state, const char *id) 577 { 578 unsigned int val; 579 580 const char *st_vsync_active_low = 581 (state->vsync_active_low ? "low" : "high"); 582 const char *st_hsync_active_low = 583 (state->hsync_active_low ? "low" : "high"); 584 585 const char *fsm_sync_status_str = "unknown"; 586 const char *fsm_crop_status_str = "unknown"; 587 const char *fsm_padding_status_str = "unknown"; 588 589 int st_stline = state->start_line; 590 int st_stcol = state->start_column; 591 int st_crpht = state->cropped_height; 592 int st_crpwd = state->cropped_width; 593 int st_verdcm = state->ver_decimation; 594 int st_hordcm = state->hor_decimation; 595 int st_ver_deinterleaving = state->ver_deinterleaving; 596 int st_hor_deinterleaving = state->hor_deinterleaving; 597 int st_leftpd = state->left_padding; 598 int st_eoloff = state->eol_offset; 599 int st_vmstartaddr = state->vmem_start_address; 600 int st_vmendaddr = state->vmem_end_address; 601 int st_vmincr = state->vmem_increment; 602 int st_yuv420 = state->is_yuv420; 603 int st_allow_fifo_overflow = state->allow_fifo_overflow; 604 int st_block_fifo_when_no_req = state->block_fifo_when_no_req; 605 606 assert(state); 607 ia_css_debug_dtrace(2, "InputFormatter State (%s):\n", id); 608 609 ia_css_debug_dtrace(2, "\tConfiguration:\n"); 610 611 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start line", st_stline); 612 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start column", st_stcol); 613 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped height", st_crpht); 614 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped width", st_crpwd); 615 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Ver decimation", st_verdcm); 616 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Hor decimation", st_hordcm); 617 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 618 "Ver deinterleaving", st_ver_deinterleaving); 619 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 620 "Hor deinterleaving", st_hor_deinterleaving); 621 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Left padding", st_leftpd); 622 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 623 "EOL offset (bytes)", st_eoloff); 624 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", 625 "VMEM start address", st_vmstartaddr); 626 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", 627 "VMEM end address", st_vmendaddr); 628 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", 629 "VMEM increment", st_vmincr); 630 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "YUV 420 format", st_yuv420); 631 ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n", 632 "Vsync", st_vsync_active_low); 633 ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n", 634 "Hsync", st_hsync_active_low); 635 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 636 "Allow FIFO overflow", st_allow_fifo_overflow); 637 /* Flag that tells whether the IF gives backpressure on frames */ 638 /* 639 * FYI, this is only on the frame request (indicate), when the IF has 640 * synch'd on a frame it will always give back pressure 641 */ 642 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 643 "Block when no request", st_block_fifo_when_no_req); 644 645 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 646 "IF_BLOCKED_FIFO_NO_REQ_ADDRESS", 647 input_formatter_reg_load(INPUT_FORMATTER0_ID, 648 HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS) 649 ); 650 651 ia_css_debug_dtrace(2, "\t%-32s:\n", "InputSwitch State"); 652 653 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 654 "_REG_GP_IFMT_input_switch_lut_reg0", 655 gp_device_reg_load(GP_DEVICE0_ID, 656 _REG_GP_IFMT_input_switch_lut_reg0)); 657 658 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 659 "_REG_GP_IFMT_input_switch_lut_reg1", 660 gp_device_reg_load(GP_DEVICE0_ID, 661 _REG_GP_IFMT_input_switch_lut_reg1)); 662 663 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 664 "_REG_GP_IFMT_input_switch_lut_reg2", 665 gp_device_reg_load(GP_DEVICE0_ID, 666 _REG_GP_IFMT_input_switch_lut_reg2)); 667 668 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 669 "_REG_GP_IFMT_input_switch_lut_reg3", 670 gp_device_reg_load(GP_DEVICE0_ID, 671 _REG_GP_IFMT_input_switch_lut_reg3)); 672 673 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 674 "_REG_GP_IFMT_input_switch_lut_reg4", 675 gp_device_reg_load(GP_DEVICE0_ID, 676 _REG_GP_IFMT_input_switch_lut_reg4)); 677 678 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 679 "_REG_GP_IFMT_input_switch_lut_reg5", 680 gp_device_reg_load(GP_DEVICE0_ID, 681 _REG_GP_IFMT_input_switch_lut_reg5)); 682 683 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 684 "_REG_GP_IFMT_input_switch_lut_reg6", 685 gp_device_reg_load(GP_DEVICE0_ID, 686 _REG_GP_IFMT_input_switch_lut_reg6)); 687 688 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 689 "_REG_GP_IFMT_input_switch_lut_reg7", 690 gp_device_reg_load(GP_DEVICE0_ID, 691 _REG_GP_IFMT_input_switch_lut_reg7)); 692 693 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 694 "_REG_GP_IFMT_input_switch_fsync_lut", 695 gp_device_reg_load(GP_DEVICE0_ID, 696 _REG_GP_IFMT_input_switch_fsync_lut)); 697 698 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 699 "_REG_GP_IFMT_srst", 700 gp_device_reg_load(GP_DEVICE0_ID, 701 _REG_GP_IFMT_srst)); 702 703 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 704 "_REG_GP_IFMT_slv_reg_srst", 705 gp_device_reg_load(GP_DEVICE0_ID, 706 _REG_GP_IFMT_slv_reg_srst)); 707 708 ia_css_debug_dtrace(2, "\tFSM Status:\n"); 709 710 val = state->fsm_sync_status; 711 712 if (val > 7) 713 fsm_sync_status_str = "ERROR"; 714 715 switch (val & 0x7) { 716 case 0: 717 fsm_sync_status_str = "idle"; 718 break; 719 case 1: 720 fsm_sync_status_str = "request frame"; 721 break; 722 case 2: 723 fsm_sync_status_str = "request lines"; 724 break; 725 case 3: 726 fsm_sync_status_str = "request vectors"; 727 break; 728 case 4: 729 fsm_sync_status_str = "send acknowledge"; 730 break; 731 default: 732 fsm_sync_status_str = "unknown"; 733 break; 734 } 735 736 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", 737 "FSM Synchronization Status", val, 738 fsm_sync_status_str); 739 740 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 741 "FSM Synchronization Counter", 742 state->fsm_sync_counter); 743 744 val = state->fsm_crop_status; 745 746 if (val > 7) 747 fsm_crop_status_str = "ERROR"; 748 749 switch (val & 0x7) { 750 case 0: 751 fsm_crop_status_str = "idle"; 752 break; 753 case 1: 754 fsm_crop_status_str = "wait line"; 755 break; 756 case 2: 757 fsm_crop_status_str = "crop line"; 758 break; 759 case 3: 760 fsm_crop_status_str = "crop pixel"; 761 break; 762 case 4: 763 fsm_crop_status_str = "pass pixel"; 764 break; 765 case 5: 766 fsm_crop_status_str = "pass line"; 767 break; 768 case 6: 769 fsm_crop_status_str = "lost line"; 770 break; 771 default: 772 fsm_crop_status_str = "unknown"; 773 break; 774 } 775 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", 776 "FSM Crop Status", val, fsm_crop_status_str); 777 778 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 779 "FSM Crop Line Counter", 780 state->fsm_crop_line_counter); 781 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 782 "FSM Crop Pixel Counter", 783 state->fsm_crop_pixel_counter); 784 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 785 "FSM Deinterleaving idx buffer", 786 state->fsm_deinterleaving_index); 787 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 788 "FSM H decimation counter", 789 state->fsm_dec_h_counter); 790 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 791 "FSM V decimation counter", 792 state->fsm_dec_v_counter); 793 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 794 "FSM block V decimation counter", 795 state->fsm_dec_block_v_counter); 796 797 val = state->fsm_padding_status; 798 799 if (val > 7) 800 fsm_padding_status_str = "ERROR"; 801 802 switch (val & 0x7) { 803 case 0: 804 fsm_padding_status_str = "idle"; 805 break; 806 case 1: 807 fsm_padding_status_str = "left pad"; 808 break; 809 case 2: 810 fsm_padding_status_str = "write"; 811 break; 812 case 3: 813 fsm_padding_status_str = "right pad"; 814 break; 815 case 4: 816 fsm_padding_status_str = "send end of line"; 817 break; 818 default: 819 fsm_padding_status_str = "unknown"; 820 break; 821 } 822 823 ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", "FSM Padding Status", 824 val, fsm_padding_status_str); 825 826 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 827 "FSM Padding element idx counter", 828 state->fsm_padding_elem_counter); 829 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support error", 830 state->fsm_vector_support_error); 831 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support buf full", 832 state->fsm_vector_buffer_full); 833 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support", 834 state->vector_support); 835 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Fifo sensor data lost", 836 state->sensor_data_lost); 837 } 838 839 static void debug_print_if_bin_state(input_formatter_bin_state_t *state) 840 { 841 ia_css_debug_dtrace(2, "Stream-to-memory state:\n"); 842 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "reset", state->reset); 843 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "input endianness", 844 state->input_endianness); 845 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "output endianness", 846 state->output_endianness); 847 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "bitswap", state->bitswap); 848 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "block_synch", 849 state->block_synch); 850 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "packet_synch", 851 state->packet_synch); 852 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "readpostwrite_sync", 853 state->readpostwrite_synch); 854 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "is_2ppc", state->is_2ppc); 855 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "en_status_update", 856 state->en_status_update); 857 } 858 859 static void ia_css_debug_dump_if_state(void) 860 { 861 input_formatter_state_t if_state; 862 input_formatter_bin_state_t if_bin_state; 863 864 input_formatter_get_state(INPUT_FORMATTER0_ID, &if_state); 865 debug_print_if_state(&if_state, "Primary IF A"); 866 ia_css_debug_dump_pif_a_isp_fifo_state(); 867 868 input_formatter_get_state(INPUT_FORMATTER1_ID, &if_state); 869 debug_print_if_state(&if_state, "Primary IF B"); 870 ia_css_debug_dump_pif_b_isp_fifo_state(); 871 872 input_formatter_bin_get_state(INPUT_FORMATTER3_ID, &if_bin_state); 873 debug_print_if_bin_state(&if_bin_state); 874 ia_css_debug_dump_str2mem_sp_fifo_state(); 875 } 876 #endif 877 878 void ia_css_debug_dump_dma_state(void) 879 { 880 /* note: the var below is made static as it is quite large; 881 if it is not static it ends up on the stack which could 882 cause issues for drivers 883 */ 884 static dma_state_t state; 885 int i, ch_id; 886 887 const char *fsm_cmd_st_lbl = "FSM Command flag state"; 888 const char *fsm_ctl_st_lbl = "FSM Control flag state"; 889 const char *fsm_ctl_state = NULL; 890 const char *fsm_ctl_flag = NULL; 891 const char *fsm_pack_st = NULL; 892 const char *fsm_read_st = NULL; 893 const char *fsm_write_st = NULL; 894 char last_cmd_str[64]; 895 896 dma_get_state(DMA0_ID, &state); 897 /* Print header for DMA dump status */ 898 ia_css_debug_dtrace(2, "DMA dump status:\n"); 899 900 /* Print FSM command flag state */ 901 if (state.fsm_command_idle) 902 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "IDLE"); 903 if (state.fsm_command_run) 904 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "RUN"); 905 if (state.fsm_command_stalling) 906 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, 907 "STALL"); 908 if (state.fsm_command_error) 909 ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, 910 "ERROR"); 911 912 /* Print last command along with the channel */ 913 ch_id = state.last_command_channel; 914 915 switch (state.last_command) { 916 case DMA_COMMAND_READ: 917 snprintf(last_cmd_str, 64, 918 "Read 2D Block [Channel: %d]", ch_id); 919 break; 920 case DMA_COMMAND_WRITE: 921 snprintf(last_cmd_str, 64, 922 "Write 2D Block [Channel: %d]", ch_id); 923 break; 924 case DMA_COMMAND_SET_CHANNEL: 925 snprintf(last_cmd_str, 64, "Set Channel [Channel: %d]", ch_id); 926 break; 927 case DMA_COMMAND_SET_PARAM: 928 snprintf(last_cmd_str, 64, 929 "Set Param: %d [Channel: %d]", 930 state.last_command_param, ch_id); 931 break; 932 case DMA_COMMAND_READ_SPECIFIC: 933 snprintf(last_cmd_str, 64, 934 "Read Specific 2D Block [Channel: %d]", ch_id); 935 break; 936 case DMA_COMMAND_WRITE_SPECIFIC: 937 snprintf(last_cmd_str, 64, 938 "Write Specific 2D Block [Channel: %d]", ch_id); 939 break; 940 case DMA_COMMAND_INIT: 941 snprintf(last_cmd_str, 64, 942 "Init 2D Block on Device A [Channel: %d]", ch_id); 943 break; 944 case DMA_COMMAND_INIT_SPECIFIC: 945 snprintf(last_cmd_str, 64, 946 "Init Specific 2D Block [Channel: %d]", ch_id); 947 break; 948 case DMA_COMMAND_RST: 949 snprintf(last_cmd_str, 64, "DMA SW Reset"); 950 break; 951 case N_DMA_COMMANDS: 952 snprintf(last_cmd_str, 64, "UNKNOWN"); 953 break; 954 default: 955 snprintf(last_cmd_str, 64, 956 "unknown [Channel: %d]", ch_id); 957 break; 958 } 959 ia_css_debug_dtrace(2, "\t%-32s: (0x%X : %s)\n", 960 "last command received", state.last_command, 961 last_cmd_str); 962 963 /* Print DMA registers */ 964 ia_css_debug_dtrace(2, "\t%-32s\n", 965 "DMA registers, connection group 0"); 966 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Command", 967 state.current_command); 968 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address A", 969 state.current_addr_a); 970 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address B", 971 state.current_addr_b); 972 973 if (state.fsm_ctrl_idle) 974 fsm_ctl_flag = "IDLE"; 975 else if (state.fsm_ctrl_run) 976 fsm_ctl_flag = "RUN"; 977 else if (state.fsm_ctrl_stalling) 978 fsm_ctl_flag = "STAL"; 979 else if (state.fsm_ctrl_error) 980 fsm_ctl_flag = "ERROR"; 981 else 982 fsm_ctl_flag = "UNKNOWN"; 983 984 switch (state.fsm_ctrl_state) { 985 case DMA_CTRL_STATE_IDLE: 986 fsm_ctl_state = "Idle state"; 987 break; 988 case DMA_CTRL_STATE_REQ_RCV: 989 fsm_ctl_state = "Req Rcv state"; 990 break; 991 case DMA_CTRL_STATE_RCV: 992 fsm_ctl_state = "Rcv state"; 993 break; 994 case DMA_CTRL_STATE_RCV_REQ: 995 fsm_ctl_state = "Rcv Req state"; 996 break; 997 case DMA_CTRL_STATE_INIT: 998 fsm_ctl_state = "Init state"; 999 break; 1000 case N_DMA_CTRL_STATES: 1001 fsm_ctl_state = "Unknown"; 1002 break; 1003 } 1004 1005 ia_css_debug_dtrace(2, "\t\t%-32s: %s -> %s\n", fsm_ctl_st_lbl, 1006 fsm_ctl_flag, fsm_ctl_state); 1007 1008 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source dev", 1009 state.fsm_ctrl_source_dev); 1010 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source addr", 1011 state.fsm_ctrl_source_addr); 1012 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source stride", 1013 state.fsm_ctrl_source_stride); 1014 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source width", 1015 state.fsm_ctrl_source_width); 1016 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source height", 1017 state.fsm_ctrl_source_height); 1018 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source dev", 1019 state.fsm_ctrl_pack_source_dev); 1020 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest dev", 1021 state.fsm_ctrl_pack_dest_dev); 1022 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest addr", 1023 state.fsm_ctrl_dest_addr); 1024 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest stride", 1025 state.fsm_ctrl_dest_stride); 1026 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source width", 1027 state.fsm_ctrl_pack_source_width); 1028 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest height", 1029 state.fsm_ctrl_pack_dest_height); 1030 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest width", 1031 state.fsm_ctrl_pack_dest_width); 1032 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source elems", 1033 state.fsm_ctrl_pack_source_elems); 1034 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest elems", 1035 state.fsm_ctrl_pack_dest_elems); 1036 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack extension", 1037 state.fsm_ctrl_pack_extension); 1038 1039 if (state.pack_idle) 1040 fsm_pack_st = "IDLE"; 1041 if (state.pack_run) 1042 fsm_pack_st = "RUN"; 1043 if (state.pack_stalling) 1044 fsm_pack_st = "STALL"; 1045 if (state.pack_error) 1046 fsm_pack_st = "ERROR"; 1047 1048 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Pack flag state", 1049 fsm_pack_st); 1050 1051 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack cnt height", 1052 state.pack_cnt_height); 1053 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack src cnt width", 1054 state.pack_src_cnt_width); 1055 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack dest cnt width", 1056 state.pack_dest_cnt_width); 1057 1058 if (state.read_state == DMA_RW_STATE_IDLE) 1059 fsm_read_st = "Idle state"; 1060 if (state.read_state == DMA_RW_STATE_REQ) 1061 fsm_read_st = "Req state"; 1062 if (state.read_state == DMA_RW_STATE_NEXT_LINE) 1063 fsm_read_st = "Next line"; 1064 if (state.read_state == DMA_RW_STATE_UNLOCK_CHANNEL) 1065 fsm_read_st = "Unlock channel"; 1066 1067 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Read state", 1068 fsm_read_st); 1069 1070 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt height", 1071 state.read_cnt_height); 1072 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt width", 1073 state.read_cnt_width); 1074 1075 if (state.write_state == DMA_RW_STATE_IDLE) 1076 fsm_write_st = "Idle state"; 1077 if (state.write_state == DMA_RW_STATE_REQ) 1078 fsm_write_st = "Req state"; 1079 if (state.write_state == DMA_RW_STATE_NEXT_LINE) 1080 fsm_write_st = "Next line"; 1081 if (state.write_state == DMA_RW_STATE_UNLOCK_CHANNEL) 1082 fsm_write_st = "Unlock channel"; 1083 1084 ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Write state", 1085 fsm_write_st); 1086 1087 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write height", 1088 state.write_height); 1089 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write width", 1090 state.write_width); 1091 1092 for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) { 1093 dma_port_state_t *port = &state.port_states[i]; 1094 1095 ia_css_debug_dtrace(2, "\tDMA device interface %d\n", i); 1096 ia_css_debug_dtrace(2, "\t\tDMA internal side state\n"); 1097 ia_css_debug_dtrace(2, 1098 "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n", 1099 port->req_cs, port->req_we_n, port->req_run, 1100 port->req_ack); 1101 ia_css_debug_dtrace(2, "\t\tMaster Output side state\n"); 1102 ia_css_debug_dtrace(2, 1103 "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n", 1104 port->send_cs, port->send_we_n, 1105 port->send_run, port->send_ack); 1106 ia_css_debug_dtrace(2, "\t\tFifo state\n"); 1107 if (port->fifo_state == DMA_FIFO_STATE_WILL_BE_FULL) 1108 ia_css_debug_dtrace(2, "\t\t\tFiFo will be full\n"); 1109 else if (port->fifo_state == DMA_FIFO_STATE_FULL) 1110 ia_css_debug_dtrace(2, "\t\t\tFifo Full\n"); 1111 else if (port->fifo_state == DMA_FIFO_STATE_EMPTY) 1112 ia_css_debug_dtrace(2, "\t\t\tFifo Empty\n"); 1113 else 1114 ia_css_debug_dtrace(2, "\t\t\tFifo state unknown\n"); 1115 1116 ia_css_debug_dtrace(2, "\t\tFifo counter %d\n\n", 1117 port->fifo_counter); 1118 } 1119 1120 for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) { 1121 dma_channel_state_t *ch = &state.channel_states[i]; 1122 1123 ia_css_debug_dtrace(2, "\t%-32s: %d\n", "DMA channel register", 1124 i); 1125 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Connection", 1126 ch->connection); 1127 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Sign extend", 1128 ch->sign_extend); 1129 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev A", 1130 ch->stride_a); 1131 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev A", 1132 ch->elems_a); 1133 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev A", 1134 ch->cropping_a); 1135 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev A", 1136 ch->width_a); 1137 ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev B", 1138 ch->stride_b); 1139 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev B", 1140 ch->elems_b); 1141 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev B", 1142 ch->cropping_b); 1143 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev B", 1144 ch->width_b); 1145 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Height", ch->height); 1146 } 1147 ia_css_debug_dtrace(2, "\n"); 1148 return; 1149 } 1150 1151 void ia_css_debug_dump_dma_sp_fifo_state(void) 1152 { 1153 fifo_channel_state_t dma_to_sp, sp_to_dma; 1154 1155 fifo_channel_get_state(FIFO_MONITOR0_ID, 1156 FIFO_CHANNEL_DMA0_TO_SP0, &dma_to_sp); 1157 fifo_channel_get_state(FIFO_MONITOR0_ID, 1158 FIFO_CHANNEL_SP0_TO_DMA0, &sp_to_dma); 1159 debug_print_fifo_channel_state(&dma_to_sp, "DMA to SP"); 1160 debug_print_fifo_channel_state(&sp_to_dma, "SP to DMA"); 1161 return; 1162 } 1163 1164 void ia_css_debug_dump_dma_isp_fifo_state(void) 1165 { 1166 fifo_channel_state_t dma_to_isp, isp_to_dma; 1167 1168 fifo_channel_get_state(FIFO_MONITOR0_ID, 1169 FIFO_CHANNEL_DMA0_TO_ISP0, &dma_to_isp); 1170 fifo_channel_get_state(FIFO_MONITOR0_ID, 1171 FIFO_CHANNEL_ISP0_TO_DMA0, &isp_to_dma); 1172 debug_print_fifo_channel_state(&dma_to_isp, "DMA to ISP"); 1173 debug_print_fifo_channel_state(&isp_to_dma, "ISP to DMA"); 1174 return; 1175 } 1176 1177 void ia_css_debug_dump_isp_sp_fifo_state(void) 1178 { 1179 fifo_channel_state_t sp_to_isp, isp_to_sp; 1180 1181 fifo_channel_get_state(FIFO_MONITOR0_ID, 1182 FIFO_CHANNEL_SP0_TO_ISP0, &sp_to_isp); 1183 fifo_channel_get_state(FIFO_MONITOR0_ID, 1184 FIFO_CHANNEL_ISP0_TO_SP0, &isp_to_sp); 1185 debug_print_fifo_channel_state(&sp_to_isp, "SP to ISP"); 1186 debug_print_fifo_channel_state(&isp_to_sp, "ISP to SP"); 1187 return; 1188 } 1189 1190 void ia_css_debug_dump_isp_gdc_fifo_state(void) 1191 { 1192 fifo_channel_state_t gdc_to_isp, isp_to_gdc; 1193 1194 fifo_channel_get_state(FIFO_MONITOR0_ID, 1195 FIFO_CHANNEL_GDC0_TO_ISP0, &gdc_to_isp); 1196 fifo_channel_get_state(FIFO_MONITOR0_ID, 1197 FIFO_CHANNEL_ISP0_TO_GDC0, &isp_to_gdc); 1198 debug_print_fifo_channel_state(&gdc_to_isp, "GDC to ISP"); 1199 debug_print_fifo_channel_state(&isp_to_gdc, "ISP to GDC"); 1200 return; 1201 } 1202 1203 void ia_css_debug_dump_all_fifo_state(void) 1204 { 1205 int i; 1206 fifo_monitor_state_t state; 1207 1208 fifo_monitor_get_state(FIFO_MONITOR0_ID, &state); 1209 1210 for (i = 0; i < N_FIFO_CHANNEL; i++) 1211 debug_print_fifo_channel_state(&state.fifo_channels[i], 1212 "squepfstqkt"); 1213 return; 1214 } 1215 1216 static void debug_binary_info_print(const struct ia_css_binary_xinfo *info) 1217 { 1218 assert(info); 1219 ia_css_debug_dtrace(2, "id = %d\n", info->sp.id); 1220 ia_css_debug_dtrace(2, "mode = %d\n", info->sp.pipeline.mode); 1221 ia_css_debug_dtrace(2, "max_input_width = %d\n", info->sp.input.max_width); 1222 ia_css_debug_dtrace(2, "min_output_width = %d\n", 1223 info->sp.output.min_width); 1224 ia_css_debug_dtrace(2, "max_output_width = %d\n", 1225 info->sp.output.max_width); 1226 ia_css_debug_dtrace(2, "top_cropping = %d\n", info->sp.pipeline.top_cropping); 1227 ia_css_debug_dtrace(2, "left_cropping = %d\n", info->sp.pipeline.left_cropping); 1228 ia_css_debug_dtrace(2, "xmem_addr = %d\n", info->xmem_addr); 1229 ia_css_debug_dtrace(2, "enable_vf_veceven = %d\n", 1230 info->sp.enable.vf_veceven); 1231 ia_css_debug_dtrace(2, "enable_dis = %d\n", info->sp.enable.dis); 1232 ia_css_debug_dtrace(2, "enable_uds = %d\n", info->sp.enable.uds); 1233 ia_css_debug_dtrace(2, "enable ds = %d\n", info->sp.enable.ds); 1234 ia_css_debug_dtrace(2, "s3atbl_use_dmem = %d\n", info->sp.s3a.s3atbl_use_dmem); 1235 return; 1236 } 1237 1238 void ia_css_debug_binary_print(const struct ia_css_binary *bi) 1239 { 1240 unsigned int i; 1241 1242 debug_binary_info_print(bi->info); 1243 ia_css_debug_dtrace(2, 1244 "input: %dx%d, format = %d, padded width = %d\n", 1245 bi->in_frame_info.res.width, 1246 bi->in_frame_info.res.height, 1247 bi->in_frame_info.format, 1248 bi->in_frame_info.padded_width); 1249 ia_css_debug_dtrace(2, 1250 "internal :%dx%d, format = %d, padded width = %d\n", 1251 bi->internal_frame_info.res.width, 1252 bi->internal_frame_info.res.height, 1253 bi->internal_frame_info.format, 1254 bi->internal_frame_info.padded_width); 1255 for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { 1256 if (bi->out_frame_info[i].res.width != 0) { 1257 ia_css_debug_dtrace(2, 1258 "out%d: %dx%d, format = %d, padded width = %d\n", 1259 i, 1260 bi->out_frame_info[i].res.width, 1261 bi->out_frame_info[i].res.height, 1262 bi->out_frame_info[i].format, 1263 bi->out_frame_info[i].padded_width); 1264 } 1265 } 1266 ia_css_debug_dtrace(2, 1267 "vf out: %dx%d, format = %d, padded width = %d\n", 1268 bi->vf_frame_info.res.width, 1269 bi->vf_frame_info.res.height, 1270 bi->vf_frame_info.format, 1271 bi->vf_frame_info.padded_width); 1272 ia_css_debug_dtrace(2, "online = %d\n", bi->online); 1273 ia_css_debug_dtrace(2, "input_buf_vectors = %d\n", 1274 bi->input_buf_vectors); 1275 ia_css_debug_dtrace(2, "deci_factor_log2 = %d\n", bi->deci_factor_log2); 1276 ia_css_debug_dtrace(2, "vf_downscale_log2 = %d\n", 1277 bi->vf_downscale_log2); 1278 ia_css_debug_dtrace(2, "dis_deci_factor_log2 = %d\n", 1279 bi->dis.deci_factor_log2); 1280 ia_css_debug_dtrace(2, "dis hor coef num = %d\n", 1281 bi->dis.coef.pad.width); 1282 ia_css_debug_dtrace(2, "dis ver coef num = %d\n", 1283 bi->dis.coef.pad.height); 1284 ia_css_debug_dtrace(2, "dis hor proj num = %d\n", 1285 bi->dis.proj.pad.height); 1286 ia_css_debug_dtrace(2, "sctbl_width_per_color = %d\n", 1287 bi->sctbl_width_per_color); 1288 ia_css_debug_dtrace(2, "s3atbl_width = %d\n", bi->s3atbl_width); 1289 ia_css_debug_dtrace(2, "s3atbl_height = %d\n", bi->s3atbl_height); 1290 return; 1291 } 1292 1293 void ia_css_debug_frame_print(const struct ia_css_frame *frame, 1294 const char *descr) 1295 { 1296 char *data = NULL; 1297 1298 assert(frame); 1299 assert(descr); 1300 1301 data = (char *)HOST_ADDRESS(frame->data); 1302 ia_css_debug_dtrace(2, "frame %s (%p):\n", descr, frame); 1303 ia_css_debug_dtrace(2, " resolution = %dx%d\n", 1304 frame->info.res.width, frame->info.res.height); 1305 ia_css_debug_dtrace(2, " padded width = %d\n", 1306 frame->info.padded_width); 1307 ia_css_debug_dtrace(2, " format = %d\n", frame->info.format); 1308 ia_css_debug_dtrace(2, " is contiguous = %s\n", 1309 frame->contiguous ? "yes" : "no"); 1310 switch (frame->info.format) { 1311 case IA_CSS_FRAME_FORMAT_NV12: 1312 case IA_CSS_FRAME_FORMAT_NV16: 1313 case IA_CSS_FRAME_FORMAT_NV21: 1314 case IA_CSS_FRAME_FORMAT_NV61: 1315 ia_css_debug_dtrace(2, " Y = %p\n", 1316 data + frame->planes.nv.y.offset); 1317 ia_css_debug_dtrace(2, " UV = %p\n", 1318 data + frame->planes.nv.uv.offset); 1319 break; 1320 case IA_CSS_FRAME_FORMAT_YUYV: 1321 case IA_CSS_FRAME_FORMAT_UYVY: 1322 case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: 1323 case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: 1324 case IA_CSS_FRAME_FORMAT_YUV_LINE: 1325 ia_css_debug_dtrace(2, " YUYV = %p\n", 1326 data + frame->planes.yuyv.offset); 1327 break; 1328 case IA_CSS_FRAME_FORMAT_YUV420: 1329 case IA_CSS_FRAME_FORMAT_YUV422: 1330 case IA_CSS_FRAME_FORMAT_YUV444: 1331 case IA_CSS_FRAME_FORMAT_YV12: 1332 case IA_CSS_FRAME_FORMAT_YV16: 1333 case IA_CSS_FRAME_FORMAT_YUV420_16: 1334 case IA_CSS_FRAME_FORMAT_YUV422_16: 1335 ia_css_debug_dtrace(2, " Y = %p\n", 1336 data + frame->planes.yuv.y.offset); 1337 ia_css_debug_dtrace(2, " U = %p\n", 1338 data + frame->planes.yuv.u.offset); 1339 ia_css_debug_dtrace(2, " V = %p\n", 1340 data + frame->planes.yuv.v.offset); 1341 break; 1342 case IA_CSS_FRAME_FORMAT_RAW_PACKED: 1343 ia_css_debug_dtrace(2, " RAW PACKED = %p\n", 1344 data + frame->planes.raw.offset); 1345 break; 1346 case IA_CSS_FRAME_FORMAT_RAW: 1347 ia_css_debug_dtrace(2, " RAW = %p\n", 1348 data + frame->planes.raw.offset); 1349 break; 1350 case IA_CSS_FRAME_FORMAT_RGBA888: 1351 case IA_CSS_FRAME_FORMAT_RGB565: 1352 ia_css_debug_dtrace(2, " RGB = %p\n", 1353 data + frame->planes.rgb.offset); 1354 break; 1355 case IA_CSS_FRAME_FORMAT_QPLANE6: 1356 ia_css_debug_dtrace(2, " R = %p\n", 1357 data + frame->planes.plane6.r.offset); 1358 ia_css_debug_dtrace(2, " RatB = %p\n", 1359 data + frame->planes.plane6.r_at_b.offset); 1360 ia_css_debug_dtrace(2, " Gr = %p\n", 1361 data + frame->planes.plane6.gr.offset); 1362 ia_css_debug_dtrace(2, " Gb = %p\n", 1363 data + frame->planes.plane6.gb.offset); 1364 ia_css_debug_dtrace(2, " B = %p\n", 1365 data + frame->planes.plane6.b.offset); 1366 ia_css_debug_dtrace(2, " BatR = %p\n", 1367 data + frame->planes.plane6.b_at_r.offset); 1368 break; 1369 case IA_CSS_FRAME_FORMAT_BINARY_8: 1370 ia_css_debug_dtrace(2, " Binary data = %p\n", 1371 data + frame->planes.binary.data.offset); 1372 break; 1373 default: 1374 ia_css_debug_dtrace(2, " unknown frame type\n"); 1375 break; 1376 } 1377 return; 1378 } 1379 1380 #if SP_DEBUG != SP_DEBUG_NONE 1381 1382 void ia_css_debug_print_sp_debug_state(const struct sh_css_sp_debug_state 1383 *state) 1384 { 1385 #endif 1386 1387 #if SP_DEBUG == SP_DEBUG_DUMP 1388 1389 assert(state); 1390 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1391 "current SP software counter: %d\n", 1392 state->debug[0]); 1393 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1394 "empty output buffer queue head: 0x%x\n", 1395 state->debug[1]); 1396 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1397 "empty output buffer queue tail: 0x%x\n", 1398 state->debug[2]); 1399 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1400 "empty s3a buffer queue head: 0x%x\n", 1401 state->debug[3]); 1402 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1403 "empty s3a buffer queue tail: 0x%x\n", 1404 state->debug[4]); 1405 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1406 "full output buffer queue head: 0x%x\n", 1407 state->debug[5]); 1408 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1409 "full output buffer queue tail: 0x%x\n", 1410 state->debug[6]); 1411 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1412 "full s3a buffer queue head: 0x%x\n", 1413 state->debug[7]); 1414 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1415 "full s3a buffer queue tail: 0x%x\n", 1416 state->debug[8]); 1417 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue head: 0x%x\n", 1418 state->debug[9]); 1419 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue tail: 0x%x\n", 1420 state->debug[10]); 1421 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1422 "num of stages of current pipeline: 0x%x\n", 1423 state->debug[11]); 1424 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 1: 0x%x\n", 1425 state->debug[12]); 1426 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 2: 0x%x\n", 1427 state->debug[13]); 1428 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1429 "current stage out_vf buffer idx: 0x%x\n", 1430 state->debug[14]); 1431 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1432 "current stage output buffer idx: 0x%x\n", 1433 state->debug[15]); 1434 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1435 "current stage s3a buffer idx: 0x%x\n", 1436 state->debug[16]); 1437 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1438 "first char of current stage name: 0x%x\n", 1439 state->debug[17]); 1440 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "current SP thread id: 0x%x\n", 1441 state->debug[18]); 1442 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1443 "empty output buffer address 1: 0x%x\n", 1444 state->debug[19]); 1445 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1446 "empty output buffer address 2: 0x%x\n", 1447 state->debug[20]); 1448 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1449 "empty out_vf buffer address 1: 0x%x\n", 1450 state->debug[21]); 1451 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1452 "empty out_vf buffer address 2: 0x%x\n", 1453 state->debug[22]); 1454 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1455 "empty s3a_hi buffer address 1: 0x%x\n", 1456 state->debug[23]); 1457 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1458 "empty s3a_hi buffer address 2: 0x%x\n", 1459 state->debug[24]); 1460 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1461 "empty s3a_lo buffer address 1: 0x%x\n", 1462 state->debug[25]); 1463 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1464 "empty s3a_lo buffer address 2: 0x%x\n", 1465 state->debug[26]); 1466 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1467 "empty dis_hor buffer address 1: 0x%x\n", 1468 state->debug[27]); 1469 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1470 "empty dis_hor buffer address 2: 0x%x\n", 1471 state->debug[28]); 1472 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1473 "empty dis_ver buffer address 1: 0x%x\n", 1474 state->debug[29]); 1475 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1476 "empty dis_ver buffer address 2: 0x%x\n", 1477 state->debug[30]); 1478 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1479 "empty param buffer address: 0x%x\n", 1480 state->debug[31]); 1481 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1482 "first incorrect frame address: 0x%x\n", 1483 state->debug[32]); 1484 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1485 "first incorrect frame container address: 0x%x\n", 1486 state->debug[33]); 1487 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1488 "first incorrect frame container payload: 0x%x\n", 1489 state->debug[34]); 1490 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1491 "first incorrect s3a_hi address: 0x%x\n", 1492 state->debug[35]); 1493 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1494 "first incorrect s3a_hi container address: 0x%x\n", 1495 state->debug[36]); 1496 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1497 "first incorrect s3a_hi container payload: 0x%x\n", 1498 state->debug[37]); 1499 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1500 "first incorrect s3a_lo address: 0x%x\n", 1501 state->debug[38]); 1502 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1503 "first incorrect s3a_lo container address: 0x%x\n", 1504 state->debug[39]); 1505 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1506 "first incorrect s3a_lo container payload: 0x%x\n", 1507 state->debug[40]); 1508 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1509 "number of calling flash start function: 0x%x\n", 1510 state->debug[41]); 1511 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1512 "number of calling flash close function: 0x%x\n", 1513 state->debug[42]); 1514 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "number of flashed frame: 0x%x\n", 1515 state->debug[43]); 1516 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "flash in use flag: 0x%x\n", 1517 state->debug[44]); 1518 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1519 "number of update frame flashed flag: 0x%x\n", 1520 state->debug[46]); 1521 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1522 "number of active threads: 0x%x\n", 1523 state->debug[45]); 1524 1525 #elif SP_DEBUG == SP_DEBUG_COPY 1526 1527 /* Remember last_index because we only want to print new entries */ 1528 static int last_index; 1529 int sp_index = state->index; 1530 int n; 1531 1532 assert(state); 1533 if (sp_index < last_index) { 1534 /* SP has been reset */ 1535 last_index = 0; 1536 } 1537 1538 if (last_index == 0) { 1539 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1540 "copy-trace init: sp_dbg_if_start_line=%d, sp_dbg_if_start_column=%d, sp_dbg_if_cropped_height=%d, sp_debg_if_cropped_width=%d\n", 1541 state->if_start_line, 1542 state->if_start_column, 1543 state->if_cropped_height, 1544 state->if_cropped_width); 1545 } 1546 1547 if ((last_index + SH_CSS_SP_DBG_TRACE_DEPTH) < sp_index) { 1548 /* last index can be multiple rounds behind */ 1549 /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */ 1550 last_index = sp_index - SH_CSS_SP_DBG_TRACE_DEPTH; 1551 } 1552 1553 for (n = last_index; n < sp_index; n++) { 1554 int i = n % SH_CSS_SP_DBG_TRACE_DEPTH; 1555 1556 if (state->trace[i].frame != 0) { 1557 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1558 "copy-trace: frame=%d, line=%d, pixel_distance=%d, mipi_used_dword=%d, sp_index=%d\n", 1559 state->trace[i].frame, 1560 state->trace[i].line, 1561 state->trace[i].pixel_distance, 1562 state->trace[i].mipi_used_dword, 1563 state->trace[i].sp_index); 1564 } 1565 } 1566 1567 last_index = sp_index; 1568 1569 #elif SP_DEBUG == SP_DEBUG_TRACE 1570 1571 /* 1572 * This is just an example how TRACE_FILE_ID (see ia_css_debug.sp.h) will 1573 * me mapped on the file name string. 1574 * 1575 * Adjust this to your trace case! 1576 */ 1577 static char const *const id2filename[8] = { 1578 "param_buffer.sp.c | tagger.sp.c | pipe_data.sp.c", 1579 "isp_init.sp.c", 1580 "sp_raw_copy.hive.c", 1581 "dma_configure.sp.c", 1582 "sp.hive.c", 1583 "event_proxy_sp.hive.c", 1584 "circular_buffer.sp.c", 1585 "frame_buffer.sp.c" 1586 }; 1587 1588 /* Example SH_CSS_SP_DBG_NR_OF_TRACES==1 */ 1589 /* Adjust this to your trace case */ 1590 static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = { 1591 "default" 1592 }; 1593 1594 /* Remember host_index_last because we only want to print new entries */ 1595 static int host_index_last[SH_CSS_SP_DBG_NR_OF_TRACES] = { 0 }; 1596 int t, n; 1597 1598 assert(state); 1599 1600 for (t = 0; t < SH_CSS_SP_DBG_NR_OF_TRACES; t++) { 1601 int sp_index_last = state->index_last[t]; 1602 1603 if (sp_index_last < host_index_last[t]) { 1604 /* SP has been reset */ 1605 host_index_last[t] = 0; 1606 } 1607 1608 if ((host_index_last[t] + SH_CSS_SP_DBG_TRACE_DEPTH) < 1609 sp_index_last) { 1610 /* last index can be multiple rounds behind */ 1611 /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */ 1612 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1613 "Warning: trace %s has gap of %d traces\n", 1614 trace_name[t], 1615 (sp_index_last - 1616 (host_index_last[t] + 1617 SH_CSS_SP_DBG_TRACE_DEPTH))); 1618 1619 host_index_last[t] = 1620 sp_index_last - SH_CSS_SP_DBG_TRACE_DEPTH; 1621 } 1622 1623 for (n = host_index_last[t]; n < sp_index_last; n++) { 1624 int i = n % SH_CSS_SP_DBG_TRACE_DEPTH; 1625 int l = state->trace[t][i].location & 1626 ((1 << SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS) - 1); 1627 int fid = state->trace[t][i].location >> 1628 SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS; 1629 int ts = state->trace[t][i].time_stamp; 1630 1631 if (ts) { 1632 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1633 "%05d trace=%s, file=%s:%d, data=0x%08x\n", 1634 ts, 1635 trace_name[t], 1636 id2filename[fid], l, 1637 state->trace[t][i].data); 1638 } 1639 } 1640 host_index_last[t] = sp_index_last; 1641 } 1642 1643 #elif SP_DEBUG == SP_DEBUG_MINIMAL 1644 int i; 1645 int base = 0; 1646 int limit = SH_CSS_NUM_SP_DEBUG; 1647 int step = 1; 1648 1649 assert(state); 1650 1651 for (i = base; i < limit; i += step) { 1652 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 1653 "sp_dbg_trace[%d] = %d\n", 1654 i, state->debug[i]); 1655 } 1656 #endif 1657 1658 #if SP_DEBUG != SP_DEBUG_NONE 1659 1660 return; 1661 } 1662 #endif 1663 1664 #if !defined(ISP2401) 1665 static void debug_print_rx_mipi_port_state(mipi_port_state_t *state) 1666 { 1667 int i; 1668 unsigned int bits, infos; 1669 1670 assert(state); 1671 1672 bits = state->irq_status; 1673 infos = ia_css_isys_rx_translate_irq_infos(bits); 1674 1675 ia_css_debug_dtrace(2, "\t\t%-32s: (irq reg = 0x%X)\n", 1676 "receiver errors", bits); 1677 1678 if (infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN) 1679 ia_css_debug_dtrace(2, "\t\t\tbuffer overrun\n"); 1680 if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT) 1681 ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission error\n"); 1682 if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC) 1683 ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission sync error\n"); 1684 if (infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL) 1685 ia_css_debug_dtrace(2, "\t\t\tcontrol error\n"); 1686 if (infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE) 1687 ia_css_debug_dtrace(2, "\t\t\t2 or more ECC errors\n"); 1688 if (infos & IA_CSS_RX_IRQ_INFO_ERR_CRC) 1689 ia_css_debug_dtrace(2, "\t\t\tCRC mismatch\n"); 1690 if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID) 1691 ia_css_debug_dtrace(2, "\t\t\tunknown error\n"); 1692 if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC) 1693 ia_css_debug_dtrace(2, "\t\t\tframe sync error\n"); 1694 if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA) 1695 ia_css_debug_dtrace(2, "\t\t\tframe data error\n"); 1696 if (infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT) 1697 ia_css_debug_dtrace(2, "\t\t\tdata timeout\n"); 1698 if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC) 1699 ia_css_debug_dtrace(2, "\t\t\tunknown escape command entry\n"); 1700 if (infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC) 1701 ia_css_debug_dtrace(2, "\t\t\tline sync error\n"); 1702 1703 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1704 "device_ready", state->device_ready); 1705 1706 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1707 "irq_status", state->irq_status); 1708 1709 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1710 "irq_enable", state->irq_enable); 1711 1712 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1713 "timeout_count", state->timeout_count); 1714 1715 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1716 "init_count", state->init_count); 1717 1718 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16_18", state->raw16_18); 1719 1720 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1721 "sync_count", state->sync_count); 1722 1723 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "rx_count", state->rx_count); 1724 1725 for (i = 0; i < MIPI_4LANE_CFG; i++) { 1726 ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n", 1727 "lane_sync_count[", i, "]", 1728 state->lane_sync_count[i]); 1729 } 1730 1731 for (i = 0; i < MIPI_4LANE_CFG; i++) { 1732 ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n", 1733 "lane_rx_count[", i, "]", 1734 state->lane_rx_count[i]); 1735 } 1736 1737 return; 1738 } 1739 1740 static void debug_print_rx_channel_state(rx_channel_state_t *state) 1741 { 1742 int i; 1743 1744 assert(state); 1745 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1746 "compression_scheme0", state->comp_scheme0); 1747 1748 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1749 "compression_scheme1", state->comp_scheme1); 1750 1751 for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) { 1752 ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n", 1753 "MIPI Predictor ", i, state->pred[i]); 1754 } 1755 1756 for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) { 1757 ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n", 1758 "MIPI Compressor ", i, state->comp[i]); 1759 } 1760 1761 return; 1762 } 1763 1764 static void debug_print_rx_state(receiver_state_t *state) 1765 { 1766 int i; 1767 1768 assert(state); 1769 ia_css_debug_dtrace(2, "CSI Receiver State:\n"); 1770 1771 ia_css_debug_dtrace(2, "\tConfiguration:\n"); 1772 1773 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1774 "fs_to_ls_delay", state->fs_to_ls_delay); 1775 1776 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1777 "ls_to_data_delay", state->ls_to_data_delay); 1778 1779 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1780 "data_to_le_delay", state->data_to_le_delay); 1781 1782 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1783 "le_to_fe_delay", state->le_to_fe_delay); 1784 1785 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1786 "fe_to_fs_delay", state->fe_to_fs_delay); 1787 1788 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1789 "le_to_fs_delay", state->le_to_fs_delay); 1790 1791 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1792 "is_two_ppc", state->is_two_ppc); 1793 1794 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1795 "backend_rst", state->backend_rst); 1796 1797 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw18", state->raw18); 1798 1799 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1800 "force_raw8", state->force_raw8); 1801 1802 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16", state->raw16); 1803 1804 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1805 "be_gsp_acc_ovl", state->be_gsp_acc_ovl); 1806 1807 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_srst", state->be_srst); 1808 1809 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1810 "be_is_two_ppc", state->be_is_two_ppc); 1811 1812 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1813 "be_comp_format0", state->be_comp_format0); 1814 1815 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1816 "be_comp_format1", state->be_comp_format1); 1817 1818 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1819 "be_comp_format2", state->be_comp_format2); 1820 1821 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1822 "be_comp_format3", state->be_comp_format3); 1823 1824 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_sel", state->be_sel); 1825 1826 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1827 "be_raw16_config", state->be_raw16_config); 1828 1829 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1830 "be_raw18_config", state->be_raw18_config); 1831 1832 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1833 "be_force_raw8", state->be_force_raw8); 1834 1835 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1836 "be_irq_status", state->be_irq_status); 1837 1838 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1839 "be_irq_clear", state->be_irq_clear); 1840 1841 /* mipi port state */ 1842 for (i = 0; i < N_MIPI_PORT_ID; i++) { 1843 ia_css_debug_dtrace(2, "\tMIPI Port %d State:\n", i); 1844 1845 debug_print_rx_mipi_port_state(&state->mipi_port_state[i]); 1846 } 1847 /* end of mipi port state */ 1848 1849 /* rx channel state */ 1850 for (i = 0; i < N_RX_CHANNEL_ID; i++) { 1851 ia_css_debug_dtrace(2, "\tRX Channel %d State:\n", i); 1852 1853 debug_print_rx_channel_state(&state->rx_channel_state[i]); 1854 } 1855 /* end of rx channel state */ 1856 1857 return; 1858 } 1859 #endif 1860 1861 void ia_css_debug_dump_rx_state(void) 1862 { 1863 #if !defined(ISP2401) 1864 receiver_state_t state; 1865 1866 receiver_get_state(RX0_ID, &state); 1867 debug_print_rx_state(&state); 1868 #endif 1869 } 1870 1871 void ia_css_debug_dump_sp_sw_debug_info(void) 1872 { 1873 #if SP_DEBUG != SP_DEBUG_NONE 1874 struct sh_css_sp_debug_state state; 1875 1876 sh_css_sp_get_debug_state(&state); 1877 ia_css_debug_print_sp_debug_state(&state); 1878 #endif 1879 ia_css_bufq_dump_queue_info(); 1880 ia_css_pipeline_dump_thread_map_info(); 1881 return; 1882 } 1883 1884 #if !defined(ISP2401) 1885 static void debug_print_isys_capture_unit_state(capture_unit_state_t *state) 1886 { 1887 assert(state); 1888 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1889 "Packet_Length", state->Packet_Length); 1890 1891 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1892 "Received_Length", state->Received_Length); 1893 1894 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1895 "Received_Short_Packets", 1896 state->Received_Short_Packets); 1897 1898 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1899 "Received_Long_Packets", 1900 state->Received_Long_Packets); 1901 1902 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1903 "Last_Command", state->Last_Command); 1904 1905 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1906 "Next_Command", state->Next_Command); 1907 1908 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1909 "Last_Acknowledge", state->Last_Acknowledge); 1910 1911 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1912 "Next_Acknowledge", state->Next_Acknowledge); 1913 1914 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1915 "FSM_State_Info", state->FSM_State_Info); 1916 1917 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1918 "StartMode", state->StartMode); 1919 1920 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1921 "Start_Addr", state->Start_Addr); 1922 1923 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1924 "Mem_Region_Size", state->Mem_Region_Size); 1925 1926 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1927 "Num_Mem_Regions", state->Num_Mem_Regions); 1928 return; 1929 } 1930 1931 static void debug_print_isys_acquisition_unit_state( 1932 acquisition_unit_state_t *state) 1933 { 1934 assert(state); 1935 1936 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1937 "Received_Short_Packets", 1938 state->Received_Short_Packets); 1939 1940 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1941 "Received_Long_Packets", 1942 state->Received_Long_Packets); 1943 1944 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1945 "Last_Command", state->Last_Command); 1946 1947 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1948 "Next_Command", state->Next_Command); 1949 1950 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1951 "Last_Acknowledge", state->Last_Acknowledge); 1952 1953 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1954 "Next_Acknowledge", state->Next_Acknowledge); 1955 1956 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1957 "FSM_State_Info", state->FSM_State_Info); 1958 1959 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1960 "Int_Cntr_Info", state->Int_Cntr_Info); 1961 1962 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1963 "Start_Addr", state->Start_Addr); 1964 1965 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1966 "Mem_Region_Size", state->Mem_Region_Size); 1967 1968 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1969 "Num_Mem_Regions", state->Num_Mem_Regions); 1970 } 1971 1972 static void debug_print_isys_ctrl_unit_state(ctrl_unit_state_t *state) 1973 { 1974 assert(state); 1975 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_cmd", state->last_cmd); 1976 1977 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_cmd", state->next_cmd); 1978 1979 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_ack", state->last_ack); 1980 1981 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_ack", state->next_ack); 1982 1983 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1984 "top_fsm_state", state->top_fsm_state); 1985 1986 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1987 "captA_fsm_state", state->captA_fsm_state); 1988 1989 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1990 "captB_fsm_state", state->captB_fsm_state); 1991 1992 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1993 "captC_fsm_state", state->captC_fsm_state); 1994 1995 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1996 "acq_fsm_state", state->acq_fsm_state); 1997 1998 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 1999 "captA_start_addr", state->captA_start_addr); 2000 2001 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2002 "captB_start_addr", state->captB_start_addr); 2003 2004 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2005 "captC_start_addr", state->captC_start_addr); 2006 2007 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2008 "captA_mem_region_size", 2009 state->captA_mem_region_size); 2010 2011 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2012 "captB_mem_region_size", 2013 state->captB_mem_region_size); 2014 2015 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2016 "captC_mem_region_size", 2017 state->captC_mem_region_size); 2018 2019 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2020 "captA_num_mem_regions", 2021 state->captA_num_mem_regions); 2022 2023 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2024 "captB_num_mem_regions", 2025 state->captB_num_mem_regions); 2026 2027 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2028 "captC_num_mem_regions", 2029 state->captC_num_mem_regions); 2030 2031 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2032 "acq_start_addr", state->acq_start_addr); 2033 2034 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2035 "acq_mem_region_size", state->acq_mem_region_size); 2036 2037 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2038 "acq_num_mem_regions", state->acq_num_mem_regions); 2039 2040 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2041 "capt_reserve_one_mem_region", 2042 state->capt_reserve_one_mem_region); 2043 2044 return; 2045 } 2046 2047 static void debug_print_isys_state(input_system_state_t *state) 2048 { 2049 int i; 2050 2051 assert(state); 2052 ia_css_debug_dtrace(2, "InputSystem State:\n"); 2053 2054 /* configuration */ 2055 ia_css_debug_dtrace(2, "\tConfiguration:\n"); 2056 2057 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2058 "str_multiCastA_sel", state->str_multicastA_sel); 2059 2060 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2061 "str_multicastB_sel", state->str_multicastB_sel); 2062 2063 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2064 "str_multicastC_sel", state->str_multicastC_sel); 2065 2066 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2067 "str_mux_sel", state->str_mux_sel); 2068 2069 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2070 "str_mon_status", state->str_mon_status); 2071 2072 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2073 "str_mon_irq_cond", state->str_mon_irq_cond); 2074 2075 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2076 "str_mon_irq_en", state->str_mon_irq_en); 2077 2078 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2079 "isys_srst", state->isys_srst); 2080 2081 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2082 "isys_slv_reg_srst", state->isys_slv_reg_srst); 2083 2084 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2085 "str_deint_portA_cnt", state->str_deint_portA_cnt); 2086 2087 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2088 "str_deint_portB_cnd", state->str_deint_portB_cnt); 2089 /* end of configuration */ 2090 2091 /* capture unit state */ 2092 for (i = 0; i < N_CAPTURE_UNIT_ID; i++) { 2093 capture_unit_state_t *capture_unit_state; 2094 2095 ia_css_debug_dtrace(2, "\tCaptureUnit %d State:\n", i); 2096 2097 capture_unit_state = &state->capture_unit[i]; 2098 debug_print_isys_capture_unit_state(capture_unit_state); 2099 } 2100 /* end of capture unit state */ 2101 2102 /* acquisition unit state */ 2103 for (i = 0; i < N_ACQUISITION_UNIT_ID; i++) { 2104 acquisition_unit_state_t *acquisition_unit_state; 2105 2106 ia_css_debug_dtrace(2, "\tAcquisitionUnit %d State:\n", i); 2107 2108 acquisition_unit_state = &state->acquisition_unit[i]; 2109 debug_print_isys_acquisition_unit_state(acquisition_unit_state); 2110 } 2111 /* end of acquisition unit state */ 2112 2113 /* control unit state */ 2114 for (i = 0; i < N_CTRL_UNIT_ID; i++) { 2115 ia_css_debug_dtrace(2, "\tControlUnit %d State:\n", i); 2116 2117 debug_print_isys_ctrl_unit_state(&state->ctrl_unit_state[i]); 2118 } 2119 /* end of control unit state */ 2120 } 2121 #endif 2122 2123 void ia_css_debug_dump_isys_state(void) 2124 { 2125 static input_system_state_t state; 2126 2127 input_system_get_state(INPUT_SYSTEM0_ID, &state); 2128 2129 #ifndef ISP2401 2130 debug_print_isys_state(&state); 2131 #else 2132 input_system_dump_state(INPUT_SYSTEM0_ID, &state); 2133 #endif 2134 } 2135 2136 void ia_css_debug_dump_debug_info(const char *context) 2137 { 2138 if (!context) 2139 context = "No Context provided"; 2140 2141 ia_css_debug_dtrace(2, "CSS Debug Info dump [Context = %s]\n", context); 2142 if (!IS_ISP2401) 2143 ia_css_debug_dump_rx_state(); 2144 2145 #ifndef ISP2401 2146 ia_css_debug_dump_if_state(); 2147 #endif 2148 ia_css_debug_dump_isp_state(); 2149 ia_css_debug_dump_isp_sp_fifo_state(); 2150 ia_css_debug_dump_isp_gdc_fifo_state(); 2151 ia_css_debug_dump_sp_state(); 2152 ia_css_debug_dump_perf_counters(); 2153 2154 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG 2155 sh_css_dump_thread_wait_info(); 2156 sh_css_dump_pipe_stage_info(); 2157 sh_css_dump_pipe_stripe_info(); 2158 #endif 2159 ia_css_debug_dump_dma_isp_fifo_state(); 2160 ia_css_debug_dump_dma_sp_fifo_state(); 2161 ia_css_debug_dump_dma_state(); 2162 2163 if (!IS_ISP2401) { 2164 struct irq_controller_state state; 2165 2166 ia_css_debug_dump_isys_state(); 2167 2168 irq_controller_get_state(IRQ2_ID, &state); 2169 2170 ia_css_debug_dtrace(2, "\t%-32s:\n", 2171 "Input System IRQ Controller State"); 2172 2173 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2174 "irq_edge", state.irq_edge); 2175 2176 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2177 "irq_mask", state.irq_mask); 2178 2179 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2180 "irq_status", state.irq_status); 2181 2182 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2183 "irq_enable", state.irq_enable); 2184 2185 ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", 2186 "irq_level_not_pulse", 2187 state.irq_level_not_pulse); 2188 } else { 2189 ia_css_debug_dump_isys_state(); 2190 } 2191 2192 ia_css_debug_tagger_state(); 2193 2194 return; 2195 } 2196 2197 /* this function is for debug use, it can make SP go to sleep 2198 state after each frame, then user can dump the stable SP dmem. 2199 this function can be called after ia_css_start_sp() 2200 and before sh_css_init_buffer_queues() 2201 */ 2202 void ia_css_debug_enable_sp_sleep_mode(enum ia_css_sp_sleep_mode mode) 2203 { 2204 const struct ia_css_fw_info *fw; 2205 unsigned int HIVE_ADDR_sp_sleep_mode; 2206 2207 fw = &sh_css_sp_fw; 2208 HIVE_ADDR_sp_sleep_mode = fw->info.sp.sleep_mode; 2209 2210 (void)HIVE_ADDR_sp_sleep_mode; /* Suppres warnings in CRUN */ 2211 2212 sp_dmem_store_uint32(SP0_ID, 2213 (unsigned int)sp_address_of(sp_sleep_mode), 2214 (uint32_t)mode); 2215 } 2216 2217 void ia_css_debug_wake_up_sp(void) 2218 { 2219 /*hrt_ctl_start(SP); */ 2220 sp_ctrl_setbit(SP0_ID, SP_SC_REG, SP_START_BIT); 2221 } 2222 2223 #define FIND_DMEM_PARAMS_TYPE(stream, kernel, type) \ 2224 (struct HRTCAT(HRTCAT(sh_css_isp_, type), _params) *) \ 2225 findf_dmem_params(stream, offsetof(struct ia_css_memory_offsets, dmem.kernel)) 2226 2227 #define FIND_DMEM_PARAMS(stream, kernel) FIND_DMEM_PARAMS_TYPE(stream, kernel, kernel) 2228 2229 /* Find a stage that support the kernel and return the parameters for that kernel */ 2230 static char * 2231 findf_dmem_params(struct ia_css_stream *stream, short idx) 2232 { 2233 int i; 2234 2235 for (i = 0; i < stream->num_pipes; i++) { 2236 struct ia_css_pipe *pipe = stream->pipes[i]; 2237 struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe); 2238 struct ia_css_pipeline_stage *stage; 2239 2240 for (stage = pipeline->stages; stage; stage = stage->next) { 2241 struct ia_css_binary *binary = stage->binary; 2242 short *offsets = (short *)&binary->info->mem_offsets.offsets.param->dmem; 2243 short dmem_offset = offsets[idx]; 2244 const struct ia_css_host_data *isp_data = 2245 ia_css_isp_param_get_mem_init(&binary->mem_params, 2246 IA_CSS_PARAM_CLASS_PARAM, IA_CSS_ISP_DMEM0); 2247 if (dmem_offset < 0) 2248 continue; 2249 return &isp_data->address[dmem_offset]; 2250 } 2251 } 2252 return NULL; 2253 } 2254 2255 void ia_css_debug_dump_isp_params(struct ia_css_stream *stream, 2256 unsigned int enable) 2257 { 2258 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "ISP PARAMETERS:\n"); 2259 2260 assert(stream); 2261 if ((enable & IA_CSS_DEBUG_DUMP_FPN) 2262 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2263 ia_css_fpn_dump(FIND_DMEM_PARAMS(stream, fpn), IA_CSS_DEBUG_VERBOSE); 2264 } 2265 if ((enable & IA_CSS_DEBUG_DUMP_OB) 2266 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2267 ia_css_ob_dump(FIND_DMEM_PARAMS(stream, ob), IA_CSS_DEBUG_VERBOSE); 2268 } 2269 if ((enable & IA_CSS_DEBUG_DUMP_SC) 2270 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2271 ia_css_sc_dump(FIND_DMEM_PARAMS(stream, sc), IA_CSS_DEBUG_VERBOSE); 2272 } 2273 if ((enable & IA_CSS_DEBUG_DUMP_WB) 2274 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2275 ia_css_wb_dump(FIND_DMEM_PARAMS(stream, wb), IA_CSS_DEBUG_VERBOSE); 2276 } 2277 if ((enable & IA_CSS_DEBUG_DUMP_DP) 2278 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2279 ia_css_dp_dump(FIND_DMEM_PARAMS(stream, dp), IA_CSS_DEBUG_VERBOSE); 2280 } 2281 if ((enable & IA_CSS_DEBUG_DUMP_BNR) 2282 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2283 ia_css_bnr_dump(FIND_DMEM_PARAMS(stream, bnr), IA_CSS_DEBUG_VERBOSE); 2284 } 2285 if ((enable & IA_CSS_DEBUG_DUMP_S3A) 2286 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2287 ia_css_s3a_dump(FIND_DMEM_PARAMS(stream, s3a), IA_CSS_DEBUG_VERBOSE); 2288 } 2289 if ((enable & IA_CSS_DEBUG_DUMP_DE) 2290 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2291 ia_css_de_dump(FIND_DMEM_PARAMS(stream, de), IA_CSS_DEBUG_VERBOSE); 2292 } 2293 if ((enable & IA_CSS_DEBUG_DUMP_YNR) 2294 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2295 ia_css_nr_dump(FIND_DMEM_PARAMS_TYPE(stream, nr, ynr), IA_CSS_DEBUG_VERBOSE); 2296 ia_css_yee_dump(FIND_DMEM_PARAMS(stream, yee), IA_CSS_DEBUG_VERBOSE); 2297 } 2298 if ((enable & IA_CSS_DEBUG_DUMP_CSC) 2299 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2300 ia_css_csc_dump(FIND_DMEM_PARAMS(stream, csc), IA_CSS_DEBUG_VERBOSE); 2301 ia_css_yuv2rgb_dump(FIND_DMEM_PARAMS_TYPE(stream, yuv2rgb, csc), 2302 IA_CSS_DEBUG_VERBOSE); 2303 ia_css_rgb2yuv_dump(FIND_DMEM_PARAMS_TYPE(stream, rgb2yuv, csc), 2304 IA_CSS_DEBUG_VERBOSE); 2305 } 2306 if ((enable & IA_CSS_DEBUG_DUMP_GC) 2307 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2308 ia_css_gc_dump(FIND_DMEM_PARAMS(stream, gc), IA_CSS_DEBUG_VERBOSE); 2309 } 2310 if ((enable & IA_CSS_DEBUG_DUMP_TNR) 2311 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2312 ia_css_tnr_dump(FIND_DMEM_PARAMS(stream, tnr), IA_CSS_DEBUG_VERBOSE); 2313 } 2314 if ((enable & IA_CSS_DEBUG_DUMP_ANR) 2315 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2316 ia_css_anr_dump(FIND_DMEM_PARAMS(stream, anr), IA_CSS_DEBUG_VERBOSE); 2317 } 2318 if ((enable & IA_CSS_DEBUG_DUMP_CE) 2319 || (enable & IA_CSS_DEBUG_DUMP_ALL)) { 2320 ia_css_ce_dump(FIND_DMEM_PARAMS(stream, ce), IA_CSS_DEBUG_VERBOSE); 2321 } 2322 } 2323 2324 void sh_css_dump_sp_raw_copy_linecount(bool reduced) 2325 { 2326 const struct ia_css_fw_info *fw; 2327 unsigned int HIVE_ADDR_raw_copy_line_count; 2328 s32 raw_copy_line_count; 2329 static s32 prev_raw_copy_line_count = -1; 2330 2331 fw = &sh_css_sp_fw; 2332 HIVE_ADDR_raw_copy_line_count = 2333 fw->info.sp.raw_copy_line_count; 2334 2335 (void)HIVE_ADDR_raw_copy_line_count; 2336 2337 sp_dmem_load(SP0_ID, 2338 (unsigned int)sp_address_of(raw_copy_line_count), 2339 &raw_copy_line_count, 2340 sizeof(raw_copy_line_count)); 2341 2342 /* only indicate if copy loop is active */ 2343 if (reduced) 2344 raw_copy_line_count = (raw_copy_line_count < 0) ? raw_copy_line_count : 1; 2345 /* do the handling */ 2346 if (prev_raw_copy_line_count != raw_copy_line_count) { 2347 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2348 "sh_css_dump_sp_raw_copy_linecount() line_count=%d\n", 2349 raw_copy_line_count); 2350 prev_raw_copy_line_count = raw_copy_line_count; 2351 } 2352 } 2353 2354 void ia_css_debug_dump_isp_binary(void) 2355 { 2356 const struct ia_css_fw_info *fw; 2357 unsigned int HIVE_ADDR_pipeline_sp_curr_binary_id; 2358 u32 curr_binary_id; 2359 static u32 prev_binary_id = 0xFFFFFFFF; 2360 static u32 sample_count; 2361 2362 fw = &sh_css_sp_fw; 2363 HIVE_ADDR_pipeline_sp_curr_binary_id = fw->info.sp.curr_binary_id; 2364 2365 (void)HIVE_ADDR_pipeline_sp_curr_binary_id; 2366 2367 sp_dmem_load(SP0_ID, 2368 (unsigned int)sp_address_of(pipeline_sp_curr_binary_id), 2369 &curr_binary_id, 2370 sizeof(curr_binary_id)); 2371 2372 /* do the handling */ 2373 sample_count++; 2374 if (prev_binary_id != curr_binary_id) { 2375 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2376 "sh_css_dump_isp_binary() pipe_id=%d, binary_id=%d, sample_count=%d\n", 2377 (curr_binary_id >> 16), 2378 (curr_binary_id & 0x0ffff), 2379 sample_count); 2380 sample_count = 0; 2381 prev_binary_id = curr_binary_id; 2382 } 2383 } 2384 2385 void ia_css_debug_dump_perf_counters(void) 2386 { 2387 const struct ia_css_fw_info *fw; 2388 int i; 2389 unsigned int HIVE_ADDR_ia_css_isys_sp_error_cnt; 2390 /* N_MIPI_PORT_ID + 1: 3 Capture Units and 1 Acquire Unit. */ 2391 s32 ia_css_sp_input_system_error_cnt[N_MIPI_PORT_ID + 1]; 2392 2393 if (IS_ISP2401) 2394 return; 2395 2396 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "Input System Error Counters:\n"); 2397 2398 fw = &sh_css_sp_fw; 2399 HIVE_ADDR_ia_css_isys_sp_error_cnt = 2400 fw->info.sp.perf_counter_input_system_error; 2401 2402 (void)HIVE_ADDR_ia_css_isys_sp_error_cnt; 2403 2404 sp_dmem_load(SP0_ID, 2405 (unsigned int)sp_address_of(ia_css_isys_sp_error_cnt), 2406 &ia_css_sp_input_system_error_cnt, 2407 sizeof(ia_css_sp_input_system_error_cnt)); 2408 2409 for (i = 0; i < N_MIPI_PORT_ID + 1; i++) { 2410 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\tport[%d] = %d\n", 2411 i, ia_css_sp_input_system_error_cnt[i]); 2412 } 2413 } 2414 2415 /* 2416 * @brief Initialize the debug mode. 2417 * Refer to "ia_css_debug.h" for more details. 2418 */ 2419 bool ia_css_debug_mode_init(void) 2420 { 2421 bool rc; 2422 2423 rc = sh_css_sp_init_dma_sw_reg(0); 2424 return rc; 2425 } 2426 2427 /* 2428 * @brief Disable the DMA channel. 2429 * Refer to "ia_css_debug.h" for more details. 2430 */ 2431 bool 2432 ia_css_debug_mode_disable_dma_channel(int dma_id, 2433 int channel_id, int request_type) 2434 { 2435 bool rc; 2436 2437 rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, false); 2438 2439 return rc; 2440 } 2441 2442 /* 2443 * @brief Enable the DMA channel. 2444 * Refer to "ia_css_debug.h" for more details. 2445 */ 2446 bool 2447 ia_css_debug_mode_enable_dma_channel(int dma_id, 2448 int channel_id, int request_type) 2449 { 2450 bool rc; 2451 2452 rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, true); 2453 2454 return rc; 2455 } 2456 2457 static void __printf(1, 2) dtrace_dot(const char *fmt, ...) 2458 { 2459 va_list ap; 2460 2461 assert(fmt); 2462 va_start(ap, fmt); 2463 2464 ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START); 2465 ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap); 2466 ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END); 2467 va_end(ap); 2468 } 2469 2470 #ifdef HAS_WATCHDOG_SP_THREAD_DEBUG 2471 void sh_css_dump_thread_wait_info(void) 2472 { 2473 const struct ia_css_fw_info *fw; 2474 int i; 2475 unsigned int HIVE_ADDR_sp_thread_wait; 2476 s32 sp_thread_wait[MAX_THREAD_NUM]; 2477 2478 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "SEM WAITS:\n"); 2479 2480 fw = &sh_css_sp_fw; 2481 HIVE_ADDR_sp_thread_wait = 2482 fw->info.sp.debug_wait; 2483 2484 (void)HIVE_ADDR_sp_thread_wait; 2485 2486 sp_dmem_load(SP0_ID, 2487 (unsigned int)sp_address_of(sp_thread_wait), 2488 &sp_thread_wait, 2489 sizeof(sp_thread_wait)); 2490 for (i = 0; i < MAX_THREAD_NUM; i++) { 2491 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2492 "\twait[%d] = 0x%X\n", 2493 i, sp_thread_wait[i]); 2494 } 2495 } 2496 2497 void sh_css_dump_pipe_stage_info(void) 2498 { 2499 const struct ia_css_fw_info *fw; 2500 int i; 2501 unsigned int HIVE_ADDR_sp_pipe_stage; 2502 s32 sp_pipe_stage[MAX_THREAD_NUM]; 2503 2504 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STAGE:\n"); 2505 2506 fw = &sh_css_sp_fw; 2507 HIVE_ADDR_sp_pipe_stage = 2508 fw->info.sp.debug_stage; 2509 2510 (void)HIVE_ADDR_sp_pipe_stage; 2511 2512 sp_dmem_load(SP0_ID, 2513 (unsigned int)sp_address_of(sp_pipe_stage), 2514 &sp_pipe_stage, 2515 sizeof(sp_pipe_stage)); 2516 for (i = 0; i < MAX_THREAD_NUM; i++) { 2517 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2518 "\tstage[%d] = %d\n", 2519 i, sp_pipe_stage[i]); 2520 } 2521 } 2522 2523 void sh_css_dump_pipe_stripe_info(void) 2524 { 2525 const struct ia_css_fw_info *fw; 2526 int i; 2527 unsigned int HIVE_ADDR_sp_pipe_stripe; 2528 s32 sp_pipe_stripe[MAX_THREAD_NUM]; 2529 2530 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STRIPE:\n"); 2531 2532 fw = &sh_css_sp_fw; 2533 HIVE_ADDR_sp_pipe_stripe = 2534 fw->info.sp.debug_stripe; 2535 2536 (void)HIVE_ADDR_sp_pipe_stripe; 2537 2538 sp_dmem_load(SP0_ID, 2539 (unsigned int)sp_address_of(sp_pipe_stripe), 2540 &sp_pipe_stripe, 2541 sizeof(sp_pipe_stripe)); 2542 for (i = 0; i < MAX_THREAD_NUM; i++) { 2543 ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, 2544 "\tstripe[%d] = %d\n", 2545 i, sp_pipe_stripe[i]); 2546 } 2547 } 2548 #endif 2549 2550 static void 2551 ia_css_debug_pipe_graph_dump_frame( 2552 const struct ia_css_frame *frame, 2553 enum ia_css_pipe_id id, 2554 char const *blob_name, 2555 char const *frame_name, 2556 bool in_frame) 2557 { 2558 char bufinfo[100]; 2559 2560 if (frame->dynamic_queue_id == SH_CSS_INVALID_QUEUE_ID) { 2561 snprintf(bufinfo, sizeof(bufinfo), "Internal"); 2562 } else { 2563 snprintf(bufinfo, sizeof(bufinfo), "Queue: %s %s", 2564 pipe_id_to_str[id], 2565 queue_id_to_str[frame->dynamic_queue_id]); 2566 } 2567 dtrace_dot( 2568 "node [shape = box, fixedsize=true, width=2, height=0.7]; \"%p\" [label = \"%s\\n%d(%d) x %d, %dbpp\\n%s\"];", 2569 frame, 2570 debug_frame_format2str(frame->info.format), 2571 frame->info.res.width, 2572 frame->info.padded_width, 2573 frame->info.res.height, 2574 frame->info.raw_bit_depth, 2575 bufinfo); 2576 2577 if (in_frame) { 2578 dtrace_dot( 2579 "\"%p\"->\"%s(pipe%d)\" [label = %s_frame];", 2580 frame, 2581 blob_name, id, frame_name); 2582 } else { 2583 dtrace_dot( 2584 "\"%s(pipe%d)\"->\"%p\" [label = %s_frame];", 2585 blob_name, id, 2586 frame, 2587 frame_name); 2588 } 2589 } 2590 2591 void 2592 ia_css_debug_pipe_graph_dump_prologue(void) 2593 { 2594 dtrace_dot("digraph sh_css_pipe_graph {"); 2595 dtrace_dot("rankdir=LR;"); 2596 2597 dtrace_dot("fontsize=9;"); 2598 dtrace_dot("label = \"\\nEnable options: rp=reduced pipe, vfve=vf_veceven, dvse=dvs_envelope, dvs6=dvs_6axis, bo=block_out, fbds=fixed_bayer_ds, bf6=bayer_fir_6db, rawb=raw_binning, cont=continuous, disc=dis_crop\\n" 2599 "dp2a=dp_2adjacent, outp=output, outt=out_table, reff=ref_frame, par=params, gam=gamma, cagdc=ca_gdc, ispa=isp_addresses, inf=in_frame, outf=out_frame, hs=high_speed, inpc=input_chunking\""); 2600 } 2601 2602 void ia_css_debug_pipe_graph_dump_epilogue(void) 2603 { 2604 if (strlen(ring_buffer) > 0) { 2605 dtrace_dot(ring_buffer); 2606 } 2607 2608 if (pg_inst.stream_format != N_ATOMISP_INPUT_FORMAT) { 2609 /* An input stream format has been set so assume we have 2610 * an input system and sensor 2611 */ 2612 2613 dtrace_dot( 2614 "node [shape = doublecircle, fixedsize=true, width=2.5]; \"input_system\" [label = \"Input system\"];"); 2615 2616 dtrace_dot( 2617 "\"input_system\"->\"%s\" [label = \"%s\"];", 2618 dot_id_input_bin, debug_stream_format2str(pg_inst.stream_format)); 2619 2620 dtrace_dot( 2621 "node [shape = doublecircle, fixedsize=true, width=2.5]; \"sensor\" [label = \"Sensor\"];"); 2622 2623 dtrace_dot( 2624 "\"sensor\"->\"input_system\" [label = \"%s\\n%d x %d\\n(%d x %d)\"];", 2625 debug_stream_format2str(pg_inst.stream_format), 2626 pg_inst.width, pg_inst.height, 2627 pg_inst.eff_width, pg_inst.eff_height); 2628 } 2629 2630 dtrace_dot("}"); 2631 2632 /* Reset temp strings */ 2633 memset(dot_id_input_bin, 0, sizeof(dot_id_input_bin)); 2634 memset(ring_buffer, 0, sizeof(ring_buffer)); 2635 2636 pg_inst.do_init = true; 2637 pg_inst.width = 0; 2638 pg_inst.height = 0; 2639 pg_inst.eff_width = 0; 2640 pg_inst.eff_height = 0; 2641 pg_inst.stream_format = N_ATOMISP_INPUT_FORMAT; 2642 } 2643 2644 void 2645 ia_css_debug_pipe_graph_dump_stage( 2646 struct ia_css_pipeline_stage *stage, 2647 enum ia_css_pipe_id id) 2648 { 2649 char blob_name[SH_CSS_MAX_BINARY_NAME + 10] = "<unknown type>"; 2650 char const *bin_type = "<unknown type>"; 2651 int i; 2652 2653 assert(stage); 2654 if (stage->sp_func != IA_CSS_PIPELINE_NO_FUNC) 2655 return; 2656 2657 if (pg_inst.do_init) { 2658 ia_css_debug_pipe_graph_dump_prologue(); 2659 pg_inst.do_init = false; 2660 } 2661 2662 if (stage->binary) { 2663 bin_type = "binary"; 2664 if (stage->binary->info->blob) 2665 snprintf(blob_name, sizeof(blob_name), "%s_stage%d", 2666 stage->binary->info->blob->name, stage->stage_num); 2667 } else if (stage->firmware) { 2668 bin_type = "firmware"; 2669 2670 strscpy(blob_name, IA_CSS_EXT_ISP_PROG_NAME(stage->firmware), 2671 sizeof(blob_name)); 2672 } 2673 2674 /* Guard in case of binaries that don't have any binary_info */ 2675 if (stage->binary_info) { 2676 char enable_info1[100]; 2677 char enable_info2[100]; 2678 char enable_info3[100]; 2679 char enable_info[200]; 2680 struct ia_css_binary_info *bi = stage->binary_info; 2681 2682 /* Split it in 2 function-calls to keep the amount of 2683 * parameters per call "reasonable" 2684 */ 2685 snprintf(enable_info1, sizeof(enable_info1), 2686 "%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 2687 bi->enable.reduced_pipe ? "rp," : "", 2688 bi->enable.vf_veceven ? "vfve," : "", 2689 bi->enable.dis ? "dis," : "", 2690 bi->enable.dvs_envelope ? "dvse," : "", 2691 bi->enable.uds ? "uds," : "", 2692 bi->enable.dvs_6axis ? "dvs6," : "", 2693 bi->enable.block_output ? "bo," : "", 2694 bi->enable.ds ? "ds," : "", 2695 bi->enable.bayer_fir_6db ? "bf6," : "", 2696 bi->enable.raw_binning ? "rawb," : "", 2697 bi->enable.continuous ? "cont," : "", 2698 bi->enable.s3a ? "s3a," : "", 2699 bi->enable.fpnr ? "fpnr," : "", 2700 bi->enable.sc ? "sc," : "" 2701 ); 2702 2703 snprintf(enable_info2, sizeof(enable_info2), 2704 "%s%s%s%s%s%s%s%s%s%s%s", 2705 bi->enable.macc ? "macc," : "", 2706 bi->enable.output ? "outp," : "", 2707 bi->enable.ref_frame ? "reff," : "", 2708 bi->enable.tnr ? "tnr," : "", 2709 bi->enable.xnr ? "xnr," : "", 2710 bi->enable.params ? "par," : "", 2711 bi->enable.ca_gdc ? "cagdc," : "", 2712 bi->enable.isp_addresses ? "ispa," : "", 2713 bi->enable.in_frame ? "inf," : "", 2714 bi->enable.out_frame ? "outf," : "", 2715 bi->enable.high_speed ? "hs," : "" 2716 ); 2717 2718 /* And merge them into one string */ 2719 snprintf(enable_info, sizeof(enable_info), "%s%s", 2720 enable_info1, enable_info2); 2721 { 2722 int l, p; 2723 char *ei = enable_info; 2724 2725 l = strlen(ei); 2726 2727 /* Replace last ',' with \0 if present */ 2728 if (l && enable_info[l - 1] == ',') 2729 enable_info[--l] = '\0'; 2730 2731 if (l > ENABLE_LINE_MAX_LENGTH) { 2732 /* Too big for one line, find last comma */ 2733 p = ENABLE_LINE_MAX_LENGTH; 2734 while (ei[p] != ',') 2735 p--; 2736 /* Last comma found, copy till that comma */ 2737 strscpy(enable_info1, ei, 2738 p > sizeof(enable_info1) ? sizeof(enable_info1) : p); 2739 2740 ei += p + 1; 2741 l = strlen(ei); 2742 2743 if (l <= ENABLE_LINE_MAX_LENGTH) { 2744 /* The 2nd line fits */ 2745 /* we cannot use ei as argument because 2746 * it is not guaranteed dword aligned 2747 */ 2748 2749 strscpy(enable_info2, ei, 2750 l > sizeof(enable_info2) ? sizeof(enable_info2) : l); 2751 2752 snprintf(enable_info, sizeof(enable_info), "%s\\n%s", 2753 enable_info1, enable_info2); 2754 2755 } else { 2756 /* 2nd line is still too long */ 2757 p = ENABLE_LINE_MAX_LENGTH; 2758 while (ei[p] != ',') 2759 p--; 2760 2761 strscpy(enable_info2, ei, 2762 p > sizeof(enable_info2) ? sizeof(enable_info2) : p); 2763 2764 ei += p + 1; 2765 l = strlen(ei); 2766 2767 if (l <= ENABLE_LINE_MAX_LENGTH) { 2768 /* The 3rd line fits */ 2769 /* we cannot use ei as argument because 2770 * it is not guaranteed dword aligned 2771 */ 2772 strscpy(enable_info3, ei, 2773 sizeof(enable_info3)); 2774 snprintf(enable_info, sizeof(enable_info), 2775 "%s\\n%s\\n%s", 2776 enable_info1, enable_info2, 2777 enable_info3); 2778 } else { 2779 /* 3rd line is still too long */ 2780 p = ENABLE_LINE_MAX_LENGTH; 2781 while (ei[p] != ',') 2782 p--; 2783 strscpy(enable_info3, ei, 2784 p > sizeof(enable_info3) ? sizeof(enable_info3) : p); 2785 ei += p + 1; 2786 strscpy(enable_info3, ei, 2787 sizeof(enable_info3)); 2788 snprintf(enable_info, sizeof(enable_info), 2789 "%s\\n%s\\n%s", 2790 enable_info1, enable_info2, 2791 enable_info3); 2792 } 2793 } 2794 } 2795 } 2796 2797 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\\n\\n%s\"]; \"%s(pipe%d)\"", 2798 bin_type, blob_name, enable_info, blob_name, id); 2799 } else { 2800 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\\n\"]; \"%s(pipe%d)\"", 2801 bin_type, blob_name, blob_name, id); 2802 } 2803 2804 if (stage->stage_num == 0) { 2805 /* 2806 * There are some implicite assumptions about which bin is the 2807 * input binary e.g. which one is connected to the input system 2808 * Priority: 2809 * 1) sp_raw_copy bin has highest priority 2810 * 2) First stage==0 binary of preview, video or capture 2811 */ 2812 if (strlen(dot_id_input_bin) == 0) { 2813 snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), 2814 "%s(pipe%d)", blob_name, id); 2815 } 2816 } 2817 2818 if (stage->args.in_frame) { 2819 ia_css_debug_pipe_graph_dump_frame( 2820 stage->args.in_frame, id, blob_name, 2821 "in", true); 2822 } 2823 2824 for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) { 2825 if (stage->args.tnr_frames[i]) { 2826 ia_css_debug_pipe_graph_dump_frame( 2827 stage->args.tnr_frames[i], id, 2828 blob_name, "tnr_frame", true); 2829 } 2830 } 2831 2832 for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) { 2833 if (stage->args.delay_frames[i]) { 2834 ia_css_debug_pipe_graph_dump_frame( 2835 stage->args.delay_frames[i], id, 2836 blob_name, "delay_frame", true); 2837 } 2838 } 2839 2840 for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { 2841 if (stage->args.out_frame[i]) { 2842 ia_css_debug_pipe_graph_dump_frame( 2843 stage->args.out_frame[i], id, blob_name, 2844 "out", false); 2845 } 2846 } 2847 2848 if (stage->args.out_vf_frame) { 2849 ia_css_debug_pipe_graph_dump_frame( 2850 stage->args.out_vf_frame, id, blob_name, 2851 "out_vf", false); 2852 } 2853 } 2854 2855 void 2856 ia_css_debug_pipe_graph_dump_sp_raw_copy( 2857 struct ia_css_frame *out_frame) 2858 { 2859 assert(out_frame); 2860 if (pg_inst.do_init) { 2861 ia_css_debug_pipe_graph_dump_prologue(); 2862 pg_inst.do_init = false; 2863 } 2864 2865 dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, label=\"%s\\n%s\"]; \"%s(pipe%d)\"", 2866 "sp-binary", "sp_raw_copy", "sp_raw_copy", 1); 2867 2868 snprintf(ring_buffer, sizeof(ring_buffer), 2869 "node [shape = box, fixedsize=true, width=2, height=0.7]; \"%p\" [label = \"%s\\n%d(%d) x %d\\nRingbuffer\"];", 2870 out_frame, 2871 debug_frame_format2str(out_frame->info.format), 2872 out_frame->info.res.width, 2873 out_frame->info.padded_width, 2874 out_frame->info.res.height); 2875 2876 dtrace_dot(ring_buffer); 2877 2878 dtrace_dot( 2879 "\"%s(pipe%d)\"->\"%p\" [label = out_frame];", 2880 "sp_raw_copy", 1, out_frame); 2881 2882 snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), "%s(pipe%d)", 2883 "sp_raw_copy", 1); 2884 } 2885 2886 void 2887 ia_css_debug_pipe_graph_dump_stream_config( 2888 const struct ia_css_stream_config *stream_config) 2889 { 2890 pg_inst.width = stream_config->input_config.input_res.width; 2891 pg_inst.height = stream_config->input_config.input_res.height; 2892 pg_inst.eff_width = stream_config->input_config.effective_res.width; 2893 pg_inst.eff_height = stream_config->input_config.effective_res.height; 2894 pg_inst.stream_format = stream_config->input_config.format; 2895 } 2896 2897 void 2898 ia_css_debug_dump_resolution( 2899 const struct ia_css_resolution *res, 2900 const char *label) 2901 { 2902 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s: =%d x =%d\n", 2903 label, res->width, res->height); 2904 } 2905 2906 void 2907 ia_css_debug_dump_frame_info( 2908 const struct ia_css_frame_info *info, 2909 const char *label) 2910 { 2911 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", label); 2912 ia_css_debug_dump_resolution(&info->res, "res"); 2913 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "padded_width: %d\n", 2914 info->padded_width); 2915 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", info->format); 2916 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bit_depth: %d\n", 2917 info->raw_bit_depth); 2918 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bayer_order: %d\n", 2919 info->raw_bayer_order); 2920 } 2921 2922 void 2923 ia_css_debug_dump_capture_config( 2924 const struct ia_css_capture_config *config) 2925 { 2926 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__); 2927 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); 2928 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_xnr: %d\n", 2929 config->enable_xnr); 2930 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_raw_output: %d\n", 2931 config->enable_raw_output); 2932 } 2933 2934 void 2935 ia_css_debug_dump_pipe_extra_config( 2936 const struct ia_css_pipe_extra_config *extra_config) 2937 { 2938 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__); 2939 if (extra_config) { 2940 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 2941 "enable_raw_binning: %d\n", 2942 extra_config->enable_raw_binning); 2943 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_yuv_ds: %d\n", 2944 extra_config->enable_yuv_ds); 2945 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 2946 "enable_high_speed: %d\n", 2947 extra_config->enable_high_speed); 2948 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 2949 "enable_dvs_6axis: %d\n", 2950 extra_config->enable_dvs_6axis); 2951 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 2952 "enable_reduced_pipe: %d\n", 2953 extra_config->enable_reduced_pipe); 2954 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 2955 "enable_fractional_ds: %d\n", 2956 extra_config->enable_fractional_ds); 2957 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "disable_vf_pp: %d\n", 2958 extra_config->disable_vf_pp); 2959 } 2960 } 2961 2962 void 2963 ia_css_debug_dump_pipe_config( 2964 const struct ia_css_pipe_config *config) 2965 { 2966 unsigned int i; 2967 2968 IA_CSS_ENTER_PRIVATE("config = %p", config); 2969 if (!config) { 2970 IA_CSS_ERROR("NULL input parameter"); 2971 IA_CSS_LEAVE_PRIVATE(""); 2972 return; 2973 } 2974 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); 2975 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "isp_pipe_version: %d\n", 2976 config->isp_pipe_version); 2977 ia_css_debug_dump_resolution(&config->bayer_ds_out_res, 2978 "bayer_ds_out_res"); 2979 ia_css_debug_dump_resolution(&config->capt_pp_in_res, 2980 "capt_pp_in_res"); 2981 ia_css_debug_dump_resolution(&config->vf_pp_in_res, "vf_pp_in_res"); 2982 2983 if (IS_ISP2401) { 2984 ia_css_debug_dump_resolution(&config->output_system_in_res, 2985 "output_system_in_res"); 2986 } 2987 ia_css_debug_dump_resolution(&config->dvs_crop_out_res, 2988 "dvs_crop_out_res"); 2989 for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { 2990 ia_css_debug_dump_frame_info(&config->output_info[i], "output_info"); 2991 ia_css_debug_dump_frame_info(&config->vf_output_info[i], 2992 "vf_output_info"); 2993 } 2994 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "acc_extension: %p\n", 2995 config->acc_extension); 2996 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_acc_stages: %d\n", 2997 config->num_acc_stages); 2998 ia_css_debug_dump_capture_config(&config->default_capture_config); 2999 ia_css_debug_dump_resolution(&config->dvs_envelope, "dvs_envelope"); 3000 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "dvs_frame_delay: %d\n", 3001 config->dvs_frame_delay); 3002 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "acc_num_execs: %d\n", 3003 config->acc_num_execs); 3004 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_dz: %d\n", 3005 config->enable_dz); 3006 IA_CSS_LEAVE_PRIVATE(""); 3007 } 3008 3009 void 3010 ia_css_debug_dump_stream_config_source( 3011 const struct ia_css_stream_config *config) 3012 { 3013 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); 3014 switch (config->mode) { 3015 case IA_CSS_INPUT_MODE_SENSOR: 3016 case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: 3017 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.port\n"); 3018 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "port: %d\n", 3019 config->source.port.port); 3020 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_lanes: %d\n", 3021 config->source.port.num_lanes); 3022 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "timeout: %d\n", 3023 config->source.port.timeout); 3024 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "compression: %d\n", 3025 config->source.port.compression.type); 3026 break; 3027 case IA_CSS_INPUT_MODE_TPG: 3028 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.tpg\n"); 3029 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n", 3030 config->source.tpg.id); 3031 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", 3032 config->source.tpg.mode); 3033 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_mask: 0x%x\n", 3034 config->source.tpg.x_mask); 3035 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_delta: %d\n", 3036 config->source.tpg.x_delta); 3037 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_mask: 0x%x\n", 3038 config->source.tpg.y_mask); 3039 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_delta: %d\n", 3040 config->source.tpg.y_delta); 3041 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "xy_mask: 0x%x\n", 3042 config->source.tpg.xy_mask); 3043 break; 3044 case IA_CSS_INPUT_MODE_PRBS: 3045 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.prbs\n"); 3046 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n", 3047 config->source.prbs.id); 3048 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "h_blank: %d\n", 3049 config->source.prbs.h_blank); 3050 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "v_blank: %d\n", 3051 config->source.prbs.v_blank); 3052 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed: 0x%x\n", 3053 config->source.prbs.seed); 3054 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed1: 0x%x\n", 3055 config->source.prbs.seed1); 3056 break; 3057 default: 3058 case IA_CSS_INPUT_MODE_FIFO: 3059 case IA_CSS_INPUT_MODE_MEMORY: 3060 break; 3061 } 3062 } 3063 3064 void 3065 ia_css_debug_dump_mipi_buffer_config( 3066 const struct ia_css_mipi_buffer_config *config) 3067 { 3068 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); 3069 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "size_mem_words: %d\n", 3070 config->size_mem_words); 3071 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "nof_mipi_buffers: %d\n", 3072 config->nof_mipi_buffers); 3073 } 3074 3075 void 3076 ia_css_debug_dump_metadata_config( 3077 const struct ia_css_metadata_config *config) 3078 { 3079 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); 3080 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "data_type: %d\n", 3081 config->data_type); 3082 ia_css_debug_dump_resolution(&config->resolution, "resolution"); 3083 } 3084 3085 void 3086 ia_css_debug_dump_stream_config( 3087 const struct ia_css_stream_config *config, 3088 int num_pipes) 3089 { 3090 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); 3091 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_pipes: %d\n", num_pipes); 3092 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); 3093 ia_css_debug_dump_stream_config_source(config); 3094 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "channel_id: %d\n", 3095 config->channel_id); 3096 ia_css_debug_dump_resolution(&config->input_config.input_res, "input_res"); 3097 ia_css_debug_dump_resolution(&config->input_config.effective_res, 3098 "effective_res"); 3099 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", 3100 config->input_config.format); 3101 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "bayer_order: %d\n", 3102 config->input_config.bayer_order); 3103 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sensor_binning_factor: %d\n", 3104 config->sensor_binning_factor); 3105 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pixels_per_clock: %d\n", 3106 config->pixels_per_clock); 3107 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "online: %d\n", 3108 config->online); 3109 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "init_num_cont_raw_buf: %d\n", 3110 config->init_num_cont_raw_buf); 3111 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3112 "target_num_cont_raw_buf: %d\n", 3113 config->target_num_cont_raw_buf); 3114 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pack_raw_pixels: %d\n", 3115 config->pack_raw_pixels); 3116 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "continuous: %d\n", 3117 config->continuous); 3118 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "flash_gpio_pin: %d\n", 3119 config->flash_gpio_pin); 3120 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "left_padding: %d\n", 3121 config->left_padding); 3122 ia_css_debug_dump_mipi_buffer_config(&config->mipi_buffer_config); 3123 ia_css_debug_dump_metadata_config(&config->metadata_config); 3124 } 3125 3126 /* 3127 Trace support. 3128 3129 This tracer is using a buffer to trace the flow of the FW and dump misc values (see below for details). 3130 Currently, support is only for SKC. 3131 To enable support for other platforms: 3132 - Allocate a buffer for tracing in DMEM. The longer the better. 3133 - Use the DBG_init routine in sp.hive.c to initiatilize the tracer with the address and size selected. 3134 - Add trace points in the SP code wherever needed. 3135 - Enable the dump below with the required address and required adjustments. 3136 Dump is called at the end of ia_css_debug_dump_sp_state(). 3137 */ 3138 3139 /* 3140 dump_trace() : dump the trace points from DMEM2. 3141 for every trace point, the following are printed: index, major:minor and the 16-bit attached value. 3142 The routine looks for the first 0, and then prints from it cyclically. 3143 Data forma in DMEM2: 3144 first 4 DWORDS: header 3145 DWORD 0: data description 3146 byte 0: version 3147 byte 1: number of threads (for future use) 3148 byte 2+3: number ot TPs 3149 DWORD 1: command byte + data (for future use) 3150 byte 0: command 3151 byte 1-3: command signature 3152 DWORD 2-3: additional data (for future use) 3153 Following data is 4-byte oriented: 3154 byte 0: major 3155 byte 1: minor 3156 byte 2-3: data 3157 */ 3158 #if TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP 3159 static void debug_dump_one_trace(enum TRACE_CORE_ID proc_id) 3160 { 3161 #if defined(HAS_TRACER_V2) 3162 u32 start_addr; 3163 u32 start_addr_data; 3164 u32 item_size; 3165 u32 tmp; 3166 u8 tid_val; 3167 enum TRACE_DUMP_FORMAT dump_format; 3168 3169 int i, j, max_trace_points, point_num, limit = -1; 3170 /* using a static buffer here as the driver has issues allocating memory */ 3171 static u32 trace_read_buf[TRACE_BUFF_SIZE] = {0}; 3172 static struct trace_header_t header; 3173 u8 *header_arr; 3174 3175 /* read the header and parse it */ 3176 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "~~~ Tracer "); 3177 switch (proc_id) { 3178 case TRACE_SP0_ID: 3179 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP0"); 3180 start_addr = TRACE_SP0_ADDR; 3181 start_addr_data = TRACE_SP0_DATA_ADDR; 3182 item_size = TRACE_SP0_ITEM_SIZE; 3183 max_trace_points = TRACE_SP0_MAX_POINTS; 3184 break; 3185 case TRACE_SP1_ID: 3186 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP1"); 3187 start_addr = TRACE_SP1_ADDR; 3188 start_addr_data = TRACE_SP1_DATA_ADDR; 3189 item_size = TRACE_SP1_ITEM_SIZE; 3190 max_trace_points = TRACE_SP1_MAX_POINTS; 3191 break; 3192 case TRACE_ISP_ID: 3193 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ISP"); 3194 start_addr = TRACE_ISP_ADDR; 3195 start_addr_data = TRACE_ISP_DATA_ADDR; 3196 item_size = TRACE_ISP_ITEM_SIZE; 3197 max_trace_points = TRACE_ISP_MAX_POINTS; 3198 break; 3199 default: 3200 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3201 "\t\ttraces are not supported for this processor ID - exiting\n"); 3202 return; 3203 } 3204 3205 if (!IS_ISP2401) { 3206 tmp = ia_css_device_load_uint32(start_addr); 3207 point_num = (tmp >> 16) & 0xFFFF; 3208 3209 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", tmp & 0xFF, 3210 point_num); 3211 } else { 3212 /* Loading byte-by-byte as using the master routine had issues */ 3213 header_arr = (uint8_t *)&header; 3214 for (i = 0; i < (int)sizeof(struct trace_header_t); i++) 3215 header_arr[i] = ia_css_device_load_uint8(start_addr + (i)); 3216 3217 point_num = header.max_tracer_points; 3218 3219 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", header.version, 3220 point_num); 3221 3222 tmp = header.version; 3223 } 3224 if ((tmp & 0xFF) != TRACER_VER) { 3225 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tUnknown version - exiting\n"); 3226 return; 3227 } 3228 if (point_num > max_trace_points) { 3229 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tToo many points - exiting\n"); 3230 return; 3231 } 3232 /* copy the TPs and find the first 0 */ 3233 for (i = 0; i < point_num; i++) { 3234 trace_read_buf[i] = ia_css_device_load_uint32(start_addr_data + 3235 (i * item_size)); 3236 if ((limit == (-1)) && (trace_read_buf[i] == 0)) 3237 limit = i; 3238 } 3239 if (IS_ISP2401) { 3240 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Status:\n"); 3241 for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) 3242 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, 3243 "\tT%d: %3d (%02x) %6d (%04x) %10d (%08x)\n", i, 3244 header.thr_status_byte[i], header.thr_status_byte[i], 3245 header.thr_status_word[i], header.thr_status_word[i], 3246 header.thr_status_dword[i], header.thr_status_dword[i]); 3247 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Scratch:\n"); 3248 for (i = 0; i < MAX_SCRATCH_DATA; i++) 3249 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%10d (%08x) ", 3250 header.scratch_debug[i], header.scratch_debug[i]); 3251 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\n"); 3252 } 3253 /* two 0s in the beginning: empty buffer */ 3254 if ((trace_read_buf[0] == 0) && (trace_read_buf[1] == 0)) { 3255 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tEmpty tracer - exiting\n"); 3256 return; 3257 } 3258 /* no overrun: start from 0 */ 3259 if ((limit == point_num - 1) || 3260 /* first 0 is at the end - border case */ 3261 (trace_read_buf[limit + 1] == 3262 0)) /* did not make a full cycle after the memset */ 3263 limit = 0; 3264 /* overrun: limit is the first non-zero after the first zero */ 3265 else 3266 limit++; 3267 3268 /* print the TPs */ 3269 for (i = 0; i < point_num; i++) { 3270 j = (limit + i) % point_num; 3271 if (trace_read_buf[j]) { 3272 if (!IS_ISP2401) { 3273 TRACE_DUMP_FORMAT dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]); 3274 } else { 3275 tid_val = FIELD_TID_UNPACK(trace_read_buf[j]); 3276 dump_format = TRACE_DUMP_FORMAT_POINT; 3277 3278 /* 3279 * When tid value is 111b, the data will be interpreted differently: 3280 * tid val is ignored, major field contains 2 bits (msb) for format type 3281 */ 3282 if (tid_val == FIELD_TID_SEL_FORMAT_PAT) { 3283 dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]); 3284 } 3285 } 3286 switch (dump_format) { 3287 case TRACE_DUMP_FORMAT_POINT: 3288 ia_css_debug_dtrace( 3289 IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %d\n", 3290 j, FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3291 FIELD_MINOR_UNPACK(trace_read_buf[j]), 3292 FIELD_VALUE_UNPACK(trace_read_buf[j])); 3293 break; 3294 /* ISP2400 */ 3295 case TRACE_DUMP_FORMAT_VALUE24_HEX: 3296 ia_css_debug_dtrace( 3297 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x H\n", 3298 j, 3299 FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3300 FIELD_VALUE_24_UNPACK(trace_read_buf[j])); 3301 break; 3302 /* ISP2400 */ 3303 case TRACE_DUMP_FORMAT_VALUE24_DEC: 3304 ia_css_debug_dtrace( 3305 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %d D\n", 3306 j, 3307 FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3308 FIELD_VALUE_24_UNPACK(trace_read_buf[j])); 3309 break; 3310 /* ISP2401 */ 3311 case TRACE_DUMP_FORMAT_POINT_NO_TID: 3312 ia_css_debug_dtrace( 3313 IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %x (%d)\n", 3314 j, 3315 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]), 3316 FIELD_MINOR_UNPACK(trace_read_buf[j]), 3317 FIELD_VALUE_UNPACK(trace_read_buf[j]), 3318 FIELD_VALUE_UNPACK(trace_read_buf[j])); 3319 break; 3320 /* ISP2401 */ 3321 case TRACE_DUMP_FORMAT_VALUE24: 3322 ia_css_debug_dtrace( 3323 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x (%d)\n", 3324 j, 3325 FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3326 FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]), 3327 FIELD_VALUE_24_UNPACK(trace_read_buf[j]), 3328 FIELD_VALUE_24_UNPACK(trace_read_buf[j])); 3329 break; 3330 case TRACE_DUMP_FORMAT_VALUE24_TIMING: 3331 ia_css_debug_dtrace( 3332 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing %x\n", 3333 j, 3334 FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3335 FIELD_VALUE_24_UNPACK(trace_read_buf[j])); 3336 break; 3337 case TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA: 3338 ia_css_debug_dtrace( 3339 IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing delta %x\n", 3340 j, 3341 FIELD_MAJOR_UNPACK(trace_read_buf[j]), 3342 FIELD_VALUE_24_UNPACK(trace_read_buf[j])); 3343 break; 3344 default: 3345 ia_css_debug_dtrace( 3346 IA_CSS_DEBUG_TRACE, 3347 "no such trace dump format %d", 3348 dump_format); 3349 break; 3350 } 3351 } 3352 } 3353 #else 3354 (void)proc_id; 3355 #endif /* HAS_TRACER_V2 */ 3356 } 3357 #endif /* TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP */ 3358 3359 void ia_css_debug_dump_trace(void) 3360 { 3361 #if TRACE_ENABLE_SP0 3362 debug_dump_one_trace(TRACE_SP0_ID); 3363 #endif 3364 #if TRACE_ENABLE_SP1 3365 debug_dump_one_trace(TRACE_SP1_ID); 3366 #endif 3367 #if TRACE_ENABLE_ISP 3368 debug_dump_one_trace(TRACE_ISP_ID); 3369 #endif 3370 } 3371 3372 /* Tagger state dump function. The tagger is only available when the CSS 3373 * contains an input system (2400 or 2401). */ 3374 void ia_css_debug_tagger_state(void) 3375 { 3376 unsigned int i; 3377 unsigned int HIVE_ADDR_tagger_frames; 3378 ia_css_tagger_buf_sp_elem_t tbuf_frames[MAX_CB_ELEMS_FOR_TAGGER]; 3379 3380 HIVE_ADDR_tagger_frames = sh_css_sp_fw.info.sp.tagger_frames_addr; 3381 3382 /* This variable is not used in crun */ 3383 (void)HIVE_ADDR_tagger_frames; 3384 3385 /* 2400 and 2401 only have 1 SP, so the tagger lives on SP0 */ 3386 sp_dmem_load(SP0_ID, 3387 (unsigned int)sp_address_of(tagger_frames), 3388 tbuf_frames, 3389 sizeof(tbuf_frames)); 3390 3391 ia_css_debug_dtrace(2, "Tagger Info:\n"); 3392 for (i = 0; i < MAX_CB_ELEMS_FOR_TAGGER; i++) { 3393 ia_css_debug_dtrace(2, "\t tagger frame[%d]: exp_id=%d, marked=%d, locked=%d\n", 3394 i, tbuf_frames[i].exp_id, tbuf_frames[i].mark, tbuf_frames[i].lock); 3395 } 3396 } 3397 3398 /* ISP2401 */ 3399 void ia_css_debug_pc_dump(sp_ID_t id, unsigned int num_of_dumps) 3400 { 3401 unsigned int pc; 3402 unsigned int i; 3403 hrt_data sc = sp_ctrl_load(id, SP_SC_REG); 3404 3405 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Status reg: 0x%X\n", id, sc); 3406 sc = sp_ctrl_load(id, SP_CTRL_SINK_REG); 3407 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Stall reg: 0x%X\n", id, sc); 3408 for (i = 0; i < num_of_dumps; i++) { 3409 pc = sp_ctrl_load(id, SP_PC_REG); 3410 ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d PC: 0x%X\n", id, pc); 3411 } 3412 } 3413