1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ 17 #define __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ 18 19 #define IS_INPUT_SYSTEM_VERSION_VERSION_2401 20 21 /* CSI reveiver has 3 ports. */ 22 #define N_CSI_PORTS (3) 23 24 #include "isys_dma.h" /* isys2401_dma_channel, 25 * isys2401_dma_cfg_t 26 */ 27 28 #include "ibuf_ctrl.h" /* ibuf_cfg_t, 29 * ibuf_ctrl_cfg_t 30 */ 31 32 #include "isys_stream2mmio.h" /* stream2mmio_cfg_t */ 33 34 #include "csi_rx.h" /* csi_rx_frontend_cfg_t, 35 * csi_rx_backend_cfg_t, 36 * csi_rx_backend_lut_entry_t 37 */ 38 #include "pixelgen.h" 39 40 #define INPUT_SYSTEM_N_STREAM_ID 6 /* maximum number of simultaneous 41 virtual channels supported*/ 42 43 typedef enum { 44 INPUT_SYSTEM_ERR_NO_ERROR = 0, 45 INPUT_SYSTEM_ERR_CREATE_CHANNEL_FAIL, 46 INPUT_SYSTEM_ERR_CONFIGURE_CHANNEL_FAIL, 47 INPUT_SYSTEM_ERR_OPEN_CHANNEL_FAIL, 48 INPUT_SYSTEM_ERR_TRANSFER_FAIL, 49 INPUT_SYSTEM_ERR_CREATE_INPUT_PORT_FAIL, 50 INPUT_SYSTEM_ERR_CONFIGURE_INPUT_PORT_FAIL, 51 INPUT_SYSTEM_ERR_OPEN_INPUT_PORT_FAIL, 52 N_INPUT_SYSTEM_ERR 53 } input_system_err_t; 54 55 typedef enum { 56 INPUT_SYSTEM_SOURCE_TYPE_UNDEFINED = 0, 57 INPUT_SYSTEM_SOURCE_TYPE_SENSOR, 58 INPUT_SYSTEM_SOURCE_TYPE_TPG, 59 INPUT_SYSTEM_SOURCE_TYPE_PRBS, 60 N_INPUT_SYSTEM_SOURCE_TYPE 61 } input_system_source_type_t; 62 63 typedef enum { 64 INPUT_SYSTEM_POLL_ON_WAIT_FOR_FRAME, 65 INPUT_SYSTEM_POLL_ON_CAPTURE_REQUEST, 66 } input_system_polling_mode_t; 67 68 typedef struct input_system_channel_s input_system_channel_t; 69 struct input_system_channel_s { 70 stream2mmio_ID_t stream2mmio_id; 71 stream2mmio_sid_ID_t stream2mmio_sid_id; 72 73 ibuf_ctrl_ID_t ibuf_ctrl_id; 74 ib_buffer_t ib_buffer; 75 76 isys2401_dma_ID_t dma_id; 77 isys2401_dma_channel dma_channel; 78 }; 79 80 typedef struct input_system_channel_cfg_s input_system_channel_cfg_t; 81 struct input_system_channel_cfg_s { 82 stream2mmio_cfg_t stream2mmio_cfg; 83 ibuf_ctrl_cfg_t ibuf_ctrl_cfg; 84 isys2401_dma_cfg_t dma_cfg; 85 isys2401_dma_port_cfg_t dma_src_port_cfg; 86 isys2401_dma_port_cfg_t dma_dest_port_cfg; 87 }; 88 89 typedef struct input_system_input_port_s input_system_input_port_t; 90 struct input_system_input_port_s { 91 input_system_source_type_t source_type; 92 93 struct { 94 csi_rx_frontend_ID_t frontend_id; 95 csi_rx_backend_ID_t backend_id; 96 csi_mipi_packet_type_t packet_type; 97 csi_rx_backend_lut_entry_t backend_lut_entry; 98 } csi_rx; 99 100 struct { 101 csi_mipi_packet_type_t packet_type; 102 csi_rx_backend_lut_entry_t backend_lut_entry; 103 } metadata; 104 105 struct { 106 pixelgen_ID_t pixelgen_id; 107 } pixelgen; 108 }; 109 110 typedef struct input_system_input_port_cfg_s input_system_input_port_cfg_t; 111 struct input_system_input_port_cfg_s { 112 struct { 113 csi_rx_frontend_cfg_t frontend_cfg; 114 csi_rx_backend_cfg_t backend_cfg; 115 csi_rx_backend_cfg_t md_backend_cfg; 116 } csi_rx_cfg; 117 118 struct { 119 pixelgen_tpg_cfg_t tpg_cfg; 120 pixelgen_prbs_cfg_t prbs_cfg; 121 } pixelgen_cfg; 122 }; 123 124 typedef struct input_system_cfg_s input_system_cfg_t; 125 struct input_system_cfg_s { 126 input_system_input_port_ID_t input_port_id; 127 128 input_system_source_type_t mode; 129 130 /* ISP2401 */ 131 input_system_polling_mode_t polling_mode; 132 133 bool online; 134 bool raw_packed; 135 s8 linked_isys_stream_id; 136 137 struct { 138 bool comp_enable; 139 s32 active_lanes; 140 s32 fmt_type; 141 s32 ch_id; 142 s32 comp_predictor; 143 s32 comp_scheme; 144 } csi_port_attr; 145 146 pixelgen_tpg_cfg_t tpg_port_attr; 147 148 pixelgen_prbs_cfg_t prbs_port_attr; 149 150 struct { 151 s32 align_req_in_bytes; 152 s32 bits_per_pixel; 153 s32 pixels_per_line; 154 s32 lines_per_frame; 155 } input_port_resolution; 156 157 struct { 158 s32 left_padding; 159 s32 max_isp_input_width; 160 } output_port_attr; 161 162 struct { 163 bool enable; 164 s32 fmt_type; 165 s32 align_req_in_bytes; 166 s32 bits_per_pixel; 167 s32 pixels_per_line; 168 s32 lines_per_frame; 169 } metadata; 170 }; 171 172 typedef struct virtual_input_system_stream_s virtual_input_system_stream_t; 173 struct virtual_input_system_stream_s { 174 u32 id; /*Used when multiple MIPI data types and/or virtual channels are used. 175 Must be unique within one CSI RX 176 and lower than SH_CSS_MAX_ISYS_CHANNEL_NODES */ 177 u8 enable_metadata; 178 input_system_input_port_t input_port; 179 input_system_channel_t channel; 180 input_system_channel_t md_channel; /* metadata channel */ 181 u8 online; 182 s8 linked_isys_stream_id; 183 u8 valid; 184 185 /* ISP2401 */ 186 input_system_polling_mode_t polling_mode; 187 s32 subscr_index; 188 }; 189 190 typedef struct virtual_input_system_stream_cfg_s 191 virtual_input_system_stream_cfg_t; 192 struct virtual_input_system_stream_cfg_s { 193 u8 enable_metadata; 194 input_system_input_port_cfg_t input_port_cfg; 195 input_system_channel_cfg_t channel_cfg; 196 input_system_channel_cfg_t md_channel_cfg; 197 u8 valid; 198 }; 199 200 #define ISP_INPUT_BUF_START_ADDR 0 201 #define NUM_OF_INPUT_BUF 2 202 #define NUM_OF_LINES_PER_BUF 2 203 #define LINES_OF_ISP_INPUT_BUF (NUM_OF_INPUT_BUF * NUM_OF_LINES_PER_BUF) 204 #define ISP_INPUT_BUF_STRIDE SH_CSS_MAX_SENSOR_WIDTH 205 206 #endif /* __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ */ 207