19d4fa1a1SMauro Carvalho Chehab /* 29d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 39d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 49d4fa1a1SMauro Carvalho Chehab * 59d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 69d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 79d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 89d4fa1a1SMauro Carvalho Chehab * 99d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 109d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 119d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 129d4fa1a1SMauro Carvalho Chehab * more details. 139d4fa1a1SMauro Carvalho Chehab */ 149d4fa1a1SMauro Carvalho Chehab 159d4fa1a1SMauro Carvalho Chehab #ifndef __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ 169d4fa1a1SMauro Carvalho Chehab #define __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ 179d4fa1a1SMauro Carvalho Chehab 189d4fa1a1SMauro Carvalho Chehab #include <type_support.h> 199d4fa1a1SMauro Carvalho Chehab #ifdef USE_INPUT_SYSTEM_VERSION_2401 209d4fa1a1SMauro Carvalho Chehab #include "isys_public.h" 219d4fa1a1SMauro Carvalho Chehab #else 229d4fa1a1SMauro Carvalho Chehab 239d4fa1a1SMauro Carvalho Chehab typedef struct input_system_state_s input_system_state_t; 249d4fa1a1SMauro Carvalho Chehab typedef struct receiver_state_s receiver_state_t; 259d4fa1a1SMauro Carvalho Chehab 269d4fa1a1SMauro Carvalho Chehab /*! Read the state of INPUT_SYSTEM[ID] 279d4fa1a1SMauro Carvalho Chehab 289d4fa1a1SMauro Carvalho Chehab \param ID[in] INPUT_SYSTEM identifier 299d4fa1a1SMauro Carvalho Chehab \param state[out] input system state structure 309d4fa1a1SMauro Carvalho Chehab 319d4fa1a1SMauro Carvalho Chehab \return none, state = INPUT_SYSTEM[ID].state 329d4fa1a1SMauro Carvalho Chehab */ 339d4fa1a1SMauro Carvalho Chehab void input_system_get_state( 349d4fa1a1SMauro Carvalho Chehab const input_system_ID_t ID, 359d4fa1a1SMauro Carvalho Chehab input_system_state_t *state); 369d4fa1a1SMauro Carvalho Chehab 379d4fa1a1SMauro Carvalho Chehab /*! Read the state of RECEIVER[ID] 389d4fa1a1SMauro Carvalho Chehab 399d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 409d4fa1a1SMauro Carvalho Chehab \param state[out] receiver state structure 419d4fa1a1SMauro Carvalho Chehab 429d4fa1a1SMauro Carvalho Chehab \return none, state = RECEIVER[ID].state 439d4fa1a1SMauro Carvalho Chehab */ 449d4fa1a1SMauro Carvalho Chehab void receiver_get_state( 459d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 469d4fa1a1SMauro Carvalho Chehab receiver_state_t *state); 479d4fa1a1SMauro Carvalho Chehab 489d4fa1a1SMauro Carvalho Chehab /*! Flag whether a MIPI format is YUV420 499d4fa1a1SMauro Carvalho Chehab 509d4fa1a1SMauro Carvalho Chehab \param mipi_format[in] MIPI format 519d4fa1a1SMauro Carvalho Chehab 529d4fa1a1SMauro Carvalho Chehab \return mipi_format == YUV420 539d4fa1a1SMauro Carvalho Chehab */ 549d4fa1a1SMauro Carvalho Chehab bool is_mipi_format_yuv420( 559d4fa1a1SMauro Carvalho Chehab const mipi_format_t mipi_format); 569d4fa1a1SMauro Carvalho Chehab 579d4fa1a1SMauro Carvalho Chehab /*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID] 589d4fa1a1SMauro Carvalho Chehab 599d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 609d4fa1a1SMauro Carvalho Chehab \param cfg_ID[in] Configuration identifier 619d4fa1a1SMauro Carvalho Chehab \param comp[in] Compression method 629d4fa1a1SMauro Carvalho Chehab \param pred[in] Predictor method 639d4fa1a1SMauro Carvalho Chehab 649d4fa1a1SMauro Carvalho Chehab \NOTE: the storage of compression configuration is 659d4fa1a1SMauro Carvalho Chehab implementation specific. The config can be 669d4fa1a1SMauro Carvalho Chehab carried either on MIPI ports or on MIPI channels 679d4fa1a1SMauro Carvalho Chehab 689d4fa1a1SMauro Carvalho Chehab \return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred} 699d4fa1a1SMauro Carvalho Chehab */ 709d4fa1a1SMauro Carvalho Chehab void receiver_set_compression( 719d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 729d4fa1a1SMauro Carvalho Chehab const unsigned int cfg_ID, 739d4fa1a1SMauro Carvalho Chehab const mipi_compressor_t comp, 749d4fa1a1SMauro Carvalho Chehab const mipi_predictor_t pred); 759d4fa1a1SMauro Carvalho Chehab 769d4fa1a1SMauro Carvalho Chehab /*! Enable PORT[port_ID] of RECEIVER[ID] 779d4fa1a1SMauro Carvalho Chehab 789d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 799d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 809d4fa1a1SMauro Carvalho Chehab \param cnd[in] irq predicate 819d4fa1a1SMauro Carvalho Chehab 829d4fa1a1SMauro Carvalho Chehab \return None, enable(RECEIVER[ID].PORT[port_ID]) 839d4fa1a1SMauro Carvalho Chehab */ 849d4fa1a1SMauro Carvalho Chehab void receiver_port_enable( 859d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 869d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID, 879d4fa1a1SMauro Carvalho Chehab const bool cnd); 889d4fa1a1SMauro Carvalho Chehab 899d4fa1a1SMauro Carvalho Chehab /*! Flag if PORT[port_ID] of RECEIVER[ID] is enabled 909d4fa1a1SMauro Carvalho Chehab 919d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 929d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 939d4fa1a1SMauro Carvalho Chehab 949d4fa1a1SMauro Carvalho Chehab \return enable(RECEIVER[ID].PORT[port_ID]) == true 959d4fa1a1SMauro Carvalho Chehab */ 969d4fa1a1SMauro Carvalho Chehab bool is_receiver_port_enabled( 979d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 989d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID); 999d4fa1a1SMauro Carvalho Chehab 1009d4fa1a1SMauro Carvalho Chehab /*! Enable the IRQ channels of PORT[port_ID] of RECEIVER[ID] 1019d4fa1a1SMauro Carvalho Chehab 1029d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1039d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 1049d4fa1a1SMauro Carvalho Chehab \param irq_info[in] irq channels 1059d4fa1a1SMauro Carvalho Chehab 1069d4fa1a1SMauro Carvalho Chehab \return None, enable(RECEIVER[ID].PORT[port_ID].irq_info) 1079d4fa1a1SMauro Carvalho Chehab */ 1089d4fa1a1SMauro Carvalho Chehab void receiver_irq_enable( 1099d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1109d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID, 1119d4fa1a1SMauro Carvalho Chehab const rx_irq_info_t irq_info); 1129d4fa1a1SMauro Carvalho Chehab 1139d4fa1a1SMauro Carvalho Chehab /*! Return the IRQ status of PORT[port_ID] of RECEIVER[ID] 1149d4fa1a1SMauro Carvalho Chehab 1159d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1169d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 1179d4fa1a1SMauro Carvalho Chehab 1189d4fa1a1SMauro Carvalho Chehab \return RECEIVER[ID].PORT[port_ID].irq_info 1199d4fa1a1SMauro Carvalho Chehab */ 1209d4fa1a1SMauro Carvalho Chehab rx_irq_info_t receiver_get_irq_info( 1219d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1229d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID); 1239d4fa1a1SMauro Carvalho Chehab 1249d4fa1a1SMauro Carvalho Chehab /*! Clear the IRQ status of PORT[port_ID] of RECEIVER[ID] 1259d4fa1a1SMauro Carvalho Chehab 1269d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1279d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 1289d4fa1a1SMauro Carvalho Chehab \param irq_info[in] irq status 1299d4fa1a1SMauro Carvalho Chehab 1309d4fa1a1SMauro Carvalho Chehab \return None, clear(RECEIVER[ID].PORT[port_ID].irq_info) 1319d4fa1a1SMauro Carvalho Chehab */ 1329d4fa1a1SMauro Carvalho Chehab void receiver_irq_clear( 1339d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1349d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID, 1359d4fa1a1SMauro Carvalho Chehab const rx_irq_info_t irq_info); 1369d4fa1a1SMauro Carvalho Chehab 1379d4fa1a1SMauro Carvalho Chehab /*! Write to a control register of INPUT_SYSTEM[ID] 1389d4fa1a1SMauro Carvalho Chehab 1399d4fa1a1SMauro Carvalho Chehab \param ID[in] INPUT_SYSTEM identifier 1409d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 1419d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 1429d4fa1a1SMauro Carvalho Chehab 1439d4fa1a1SMauro Carvalho Chehab \return none, INPUT_SYSTEM[ID].ctrl[reg] = value 1449d4fa1a1SMauro Carvalho Chehab */ 1459d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H void input_system_reg_store( 1469d4fa1a1SMauro Carvalho Chehab const input_system_ID_t ID, 1479d4fa1a1SMauro Carvalho Chehab const hrt_address reg, 1489d4fa1a1SMauro Carvalho Chehab const hrt_data value); 1499d4fa1a1SMauro Carvalho Chehab 1509d4fa1a1SMauro Carvalho Chehab /*! Read from a control register of INPUT_SYSTEM[ID] 1519d4fa1a1SMauro Carvalho Chehab 1529d4fa1a1SMauro Carvalho Chehab \param ID[in] INPUT_SYSTEM identifier 1539d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 1549d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 1559d4fa1a1SMauro Carvalho Chehab 1569d4fa1a1SMauro Carvalho Chehab \return INPUT_SYSTEM[ID].ctrl[reg] 1579d4fa1a1SMauro Carvalho Chehab */ 1589d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_reg_load( 1599d4fa1a1SMauro Carvalho Chehab const input_system_ID_t ID, 1609d4fa1a1SMauro Carvalho Chehab const hrt_address reg); 1619d4fa1a1SMauro Carvalho Chehab 1629d4fa1a1SMauro Carvalho Chehab /*! Write to a control register of RECEIVER[ID] 1639d4fa1a1SMauro Carvalho Chehab 1649d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1659d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 1669d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 1679d4fa1a1SMauro Carvalho Chehab 1689d4fa1a1SMauro Carvalho Chehab \return none, RECEIVER[ID].ctrl[reg] = value 1699d4fa1a1SMauro Carvalho Chehab */ 1709d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H void receiver_reg_store( 1719d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1729d4fa1a1SMauro Carvalho Chehab const hrt_address reg, 1739d4fa1a1SMauro Carvalho Chehab const hrt_data value); 1749d4fa1a1SMauro Carvalho Chehab 1759d4fa1a1SMauro Carvalho Chehab /*! Read from a control register of RECEIVER[ID] 1769d4fa1a1SMauro Carvalho Chehab 1779d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1789d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 1799d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 1809d4fa1a1SMauro Carvalho Chehab 1819d4fa1a1SMauro Carvalho Chehab \return RECEIVER[ID].ctrl[reg] 1829d4fa1a1SMauro Carvalho Chehab */ 1839d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_reg_load( 1849d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1859d4fa1a1SMauro Carvalho Chehab const hrt_address reg); 1869d4fa1a1SMauro Carvalho Chehab 1879d4fa1a1SMauro Carvalho Chehab /*! Write to a control register of PORT[port_ID] of RECEIVER[ID] 1889d4fa1a1SMauro Carvalho Chehab 1899d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1909d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 1919d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 1929d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 1939d4fa1a1SMauro Carvalho Chehab 1949d4fa1a1SMauro Carvalho Chehab \return none, RECEIVER[ID].PORT[port_ID].ctrl[reg] = value 1959d4fa1a1SMauro Carvalho Chehab */ 1969d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H void receiver_port_reg_store( 1979d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1989d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID, 1999d4fa1a1SMauro Carvalho Chehab const hrt_address reg, 2009d4fa1a1SMauro Carvalho Chehab const hrt_data value); 2019d4fa1a1SMauro Carvalho Chehab 2029d4fa1a1SMauro Carvalho Chehab /*! Read from a control register PORT[port_ID] of of RECEIVER[ID] 2039d4fa1a1SMauro Carvalho Chehab 2049d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 2059d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 2069d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 2079d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 2089d4fa1a1SMauro Carvalho Chehab 2099d4fa1a1SMauro Carvalho Chehab \return RECEIVER[ID].PORT[port_ID].ctrl[reg] 2109d4fa1a1SMauro Carvalho Chehab */ 2119d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_port_reg_load( 2129d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 2139d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID, 2149d4fa1a1SMauro Carvalho Chehab const hrt_address reg); 2159d4fa1a1SMauro Carvalho Chehab 2169d4fa1a1SMauro Carvalho Chehab /*! Write to a control register of SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID] 2179d4fa1a1SMauro Carvalho Chehab 2189d4fa1a1SMauro Carvalho Chehab \param ID[in] INPUT_SYSTEM identifier 2199d4fa1a1SMauro Carvalho Chehab \param port_ID[in] sub system identifier 2209d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 2219d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 2229d4fa1a1SMauro Carvalho Chehab 2239d4fa1a1SMauro Carvalho Chehab \return none, INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] = value 2249d4fa1a1SMauro Carvalho Chehab */ 2259d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H void input_system_sub_system_reg_store( 2269d4fa1a1SMauro Carvalho Chehab const input_system_ID_t ID, 2279d4fa1a1SMauro Carvalho Chehab const sub_system_ID_t sub_ID, 2289d4fa1a1SMauro Carvalho Chehab const hrt_address reg, 2299d4fa1a1SMauro Carvalho Chehab const hrt_data value); 2309d4fa1a1SMauro Carvalho Chehab 2319d4fa1a1SMauro Carvalho Chehab /*! Read from a control register SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID] 2329d4fa1a1SMauro Carvalho Chehab 2339d4fa1a1SMauro Carvalho Chehab \param ID[in] INPUT_SYSTEM identifier 2349d4fa1a1SMauro Carvalho Chehab \param port_ID[in] sub system identifier 2359d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 2369d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 2379d4fa1a1SMauro Carvalho Chehab 2389d4fa1a1SMauro Carvalho Chehab \return INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] 2399d4fa1a1SMauro Carvalho Chehab */ 2409d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_sub_system_reg_load( 2419d4fa1a1SMauro Carvalho Chehab const input_system_ID_t ID, 2429d4fa1a1SMauro Carvalho Chehab const sub_system_ID_t sub_ID, 2439d4fa1a1SMauro Carvalho Chehab const hrt_address reg); 2449d4fa1a1SMauro Carvalho Chehab 2459d4fa1a1SMauro Carvalho Chehab /////////////////////////////////////////////////////////////////////////// 2469d4fa1a1SMauro Carvalho Chehab // 2479d4fa1a1SMauro Carvalho Chehab // Functions for configuration phase on input system. 2489d4fa1a1SMauro Carvalho Chehab // 2499d4fa1a1SMauro Carvalho Chehab /////////////////////////////////////////////////////////////////////////// 2509d4fa1a1SMauro Carvalho Chehab 2519d4fa1a1SMauro Carvalho Chehab // Function that resets current configuration. 2529d4fa1a1SMauro Carvalho Chehab // remove the argument since it should be private. 2539d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_configuration_reset(void); 2549d4fa1a1SMauro Carvalho Chehab 2559d4fa1a1SMauro Carvalho Chehab // Function that commits current configuration. 2569d4fa1a1SMauro Carvalho Chehab // remove the argument since it should be private. 2579d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_configuration_commit(void); 2589d4fa1a1SMauro Carvalho Chehab 2599d4fa1a1SMauro Carvalho Chehab /////////////////////////////////////////////////////////////////////////// 2609d4fa1a1SMauro Carvalho Chehab // 2619d4fa1a1SMauro Carvalho Chehab // User functions: 2629d4fa1a1SMauro Carvalho Chehab // (encoded generic function) 2639d4fa1a1SMauro Carvalho Chehab // - no checking 2649d4fa1a1SMauro Carvalho Chehab // - decoding name and agruments into the generic (channel) configuration 2659d4fa1a1SMauro Carvalho Chehab // function. 2669d4fa1a1SMauro Carvalho Chehab // 2679d4fa1a1SMauro Carvalho Chehab /////////////////////////////////////////////////////////////////////////// 2689d4fa1a1SMauro Carvalho Chehab 2699d4fa1a1SMauro Carvalho Chehab // FIFO channel config function user 2709d4fa1a1SMauro Carvalho Chehab 2719d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_csi_fifo_channel_cfg( 2729d4fa1a1SMauro Carvalho Chehab u32 ch_id, 2739d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 2749d4fa1a1SMauro Carvalho Chehab backend_channel_cfg_t backend_ch, 2759d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 2769d4fa1a1SMauro Carvalho Chehab ); 2779d4fa1a1SMauro Carvalho Chehab 2789d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_csi_fifo_channel_with_counting_cfg( 2799d4fa1a1SMauro Carvalho Chehab u32 ch_id, 2809d4fa1a1SMauro Carvalho Chehab u32 nof_frame, 2819d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 2829d4fa1a1SMauro Carvalho Chehab backend_channel_cfg_t backend_ch, 2839d4fa1a1SMauro Carvalho Chehab u32 mem_region_size, 2849d4fa1a1SMauro Carvalho Chehab u32 nof_mem_regions, 2859d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 2869d4fa1a1SMauro Carvalho Chehab ); 2879d4fa1a1SMauro Carvalho Chehab 2889d4fa1a1SMauro Carvalho Chehab // SRAM channel config function user 2899d4fa1a1SMauro Carvalho Chehab 2909d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_csi_sram_channel_cfg( 2919d4fa1a1SMauro Carvalho Chehab u32 ch_id, 2929d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 2939d4fa1a1SMauro Carvalho Chehab backend_channel_cfg_t backend_ch, 2949d4fa1a1SMauro Carvalho Chehab u32 csi_mem_region_size, 2959d4fa1a1SMauro Carvalho Chehab u32 csi_nof_mem_regions, 2969d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 2979d4fa1a1SMauro Carvalho Chehab ); 2989d4fa1a1SMauro Carvalho Chehab 2999d4fa1a1SMauro Carvalho Chehab //XMEM channel config function user 3009d4fa1a1SMauro Carvalho Chehab 3019d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_csi_xmem_channel_cfg( 3029d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3039d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 3049d4fa1a1SMauro Carvalho Chehab backend_channel_cfg_t backend_ch, 3059d4fa1a1SMauro Carvalho Chehab u32 mem_region_size, 3069d4fa1a1SMauro Carvalho Chehab u32 nof_mem_regions, 3079d4fa1a1SMauro Carvalho Chehab u32 acq_mem_region_size, 3089d4fa1a1SMauro Carvalho Chehab u32 acq_nof_mem_regions, 3099d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target, 3109d4fa1a1SMauro Carvalho Chehab uint32_t nof_xmem_buffers 3119d4fa1a1SMauro Carvalho Chehab ); 3129d4fa1a1SMauro Carvalho Chehab 3139d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_csi_xmem_capture_only_channel_cfg( 3149d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3159d4fa1a1SMauro Carvalho Chehab u32 nof_frames, 3169d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 3179d4fa1a1SMauro Carvalho Chehab u32 csi_mem_region_size, 3189d4fa1a1SMauro Carvalho Chehab u32 csi_nof_mem_regions, 3199d4fa1a1SMauro Carvalho Chehab u32 acq_mem_region_size, 3209d4fa1a1SMauro Carvalho Chehab u32 acq_nof_mem_regions, 3219d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 3229d4fa1a1SMauro Carvalho Chehab ); 3239d4fa1a1SMauro Carvalho Chehab 3249d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_csi_xmem_acquire_only_channel_cfg( 3259d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3269d4fa1a1SMauro Carvalho Chehab u32 nof_frames, 3279d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 3289d4fa1a1SMauro Carvalho Chehab backend_channel_cfg_t backend_ch, 3299d4fa1a1SMauro Carvalho Chehab u32 acq_mem_region_size, 3309d4fa1a1SMauro Carvalho Chehab u32 acq_nof_mem_regions, 3319d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 3329d4fa1a1SMauro Carvalho Chehab ); 3339d4fa1a1SMauro Carvalho Chehab 3349d4fa1a1SMauro Carvalho Chehab // Non - CSI channel config function user 3359d4fa1a1SMauro Carvalho Chehab 3369d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_prbs_channel_cfg( 3379d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3389d4fa1a1SMauro Carvalho Chehab u32 nof_frames, 3399d4fa1a1SMauro Carvalho Chehab u32 seed, 3409d4fa1a1SMauro Carvalho Chehab u32 sync_gen_width, 3419d4fa1a1SMauro Carvalho Chehab u32 sync_gen_height, 3429d4fa1a1SMauro Carvalho Chehab u32 sync_gen_hblank_cycles, 3439d4fa1a1SMauro Carvalho Chehab u32 sync_gen_vblank_cycles, 3449d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 3459d4fa1a1SMauro Carvalho Chehab ); 3469d4fa1a1SMauro Carvalho Chehab 3479d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_tpg_channel_cfg( 3489d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3499d4fa1a1SMauro Carvalho Chehab u32 nof_frames,//not used yet 3509d4fa1a1SMauro Carvalho Chehab u32 x_mask, 3519d4fa1a1SMauro Carvalho Chehab u32 y_mask, 3529d4fa1a1SMauro Carvalho Chehab u32 x_delta, 3539d4fa1a1SMauro Carvalho Chehab u32 y_delta, 3549d4fa1a1SMauro Carvalho Chehab u32 xy_mask, 3559d4fa1a1SMauro Carvalho Chehab u32 sync_gen_width, 3569d4fa1a1SMauro Carvalho Chehab u32 sync_gen_height, 3579d4fa1a1SMauro Carvalho Chehab u32 sync_gen_hblank_cycles, 3589d4fa1a1SMauro Carvalho Chehab u32 sync_gen_vblank_cycles, 3599d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 3609d4fa1a1SMauro Carvalho Chehab ); 3619d4fa1a1SMauro Carvalho Chehab 3629d4fa1a1SMauro Carvalho Chehab input_system_error_t input_system_gpfifo_channel_cfg( 3639d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3649d4fa1a1SMauro Carvalho Chehab u32 nof_frames, 3659d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 3669d4fa1a1SMauro Carvalho Chehab ); 3679d4fa1a1SMauro Carvalho Chehab #endif /* #ifdef USE_INPUT_SYSTEM_VERSION_2401 */ 3689d4fa1a1SMauro Carvalho Chehab 3699d4fa1a1SMauro Carvalho Chehab #endif /* __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ */ 370