1f5fbb83fSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */ 29d4fa1a1SMauro Carvalho Chehab /* 39d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 49d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 59d4fa1a1SMauro Carvalho Chehab * 69d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 79d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 89d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 99d4fa1a1SMauro Carvalho Chehab * 109d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 119d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 129d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 139d4fa1a1SMauro Carvalho Chehab * more details. 149d4fa1a1SMauro Carvalho Chehab */ 159d4fa1a1SMauro Carvalho Chehab 169d4fa1a1SMauro Carvalho Chehab #ifndef __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ 179d4fa1a1SMauro Carvalho Chehab #define __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ 189d4fa1a1SMauro Carvalho Chehab 199d4fa1a1SMauro Carvalho Chehab #include <type_support.h> 20641c2292SMauro Carvalho Chehab #ifdef ISP2401 219d4fa1a1SMauro Carvalho Chehab #include "isys_public.h" 229d4fa1a1SMauro Carvalho Chehab #else 239d4fa1a1SMauro Carvalho Chehab 249d4fa1a1SMauro Carvalho Chehab typedef struct input_system_state_s input_system_state_t; 259d4fa1a1SMauro Carvalho Chehab typedef struct receiver_state_s receiver_state_t; 269d4fa1a1SMauro Carvalho Chehab 279d4fa1a1SMauro Carvalho Chehab /*! Read the state of INPUT_SYSTEM[ID] 289d4fa1a1SMauro Carvalho Chehab 299d4fa1a1SMauro Carvalho Chehab \param ID[in] INPUT_SYSTEM identifier 309d4fa1a1SMauro Carvalho Chehab \param state[out] input system state structure 319d4fa1a1SMauro Carvalho Chehab 329d4fa1a1SMauro Carvalho Chehab \return none, state = INPUT_SYSTEM[ID].state 339d4fa1a1SMauro Carvalho Chehab */ 349d4fa1a1SMauro Carvalho Chehab void input_system_get_state( 359d4fa1a1SMauro Carvalho Chehab const input_system_ID_t ID, 369d4fa1a1SMauro Carvalho Chehab input_system_state_t *state); 379d4fa1a1SMauro Carvalho Chehab 389d4fa1a1SMauro Carvalho Chehab /*! Read the state of RECEIVER[ID] 399d4fa1a1SMauro Carvalho Chehab 409d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 419d4fa1a1SMauro Carvalho Chehab \param state[out] receiver state structure 429d4fa1a1SMauro Carvalho Chehab 439d4fa1a1SMauro Carvalho Chehab \return none, state = RECEIVER[ID].state 449d4fa1a1SMauro Carvalho Chehab */ 459d4fa1a1SMauro Carvalho Chehab void receiver_get_state( 469d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 479d4fa1a1SMauro Carvalho Chehab receiver_state_t *state); 489d4fa1a1SMauro Carvalho Chehab 499d4fa1a1SMauro Carvalho Chehab /*! Flag whether a MIPI format is YUV420 509d4fa1a1SMauro Carvalho Chehab 519d4fa1a1SMauro Carvalho Chehab \param mipi_format[in] MIPI format 529d4fa1a1SMauro Carvalho Chehab 539d4fa1a1SMauro Carvalho Chehab \return mipi_format == YUV420 549d4fa1a1SMauro Carvalho Chehab */ 559d4fa1a1SMauro Carvalho Chehab bool is_mipi_format_yuv420( 569d4fa1a1SMauro Carvalho Chehab const mipi_format_t mipi_format); 579d4fa1a1SMauro Carvalho Chehab 589d4fa1a1SMauro Carvalho Chehab /*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID] 599d4fa1a1SMauro Carvalho Chehab 609d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 619d4fa1a1SMauro Carvalho Chehab \param cfg_ID[in] Configuration identifier 629d4fa1a1SMauro Carvalho Chehab \param comp[in] Compression method 639d4fa1a1SMauro Carvalho Chehab \param pred[in] Predictor method 649d4fa1a1SMauro Carvalho Chehab 659d4fa1a1SMauro Carvalho Chehab \NOTE: the storage of compression configuration is 669d4fa1a1SMauro Carvalho Chehab implementation specific. The config can be 679d4fa1a1SMauro Carvalho Chehab carried either on MIPI ports or on MIPI channels 689d4fa1a1SMauro Carvalho Chehab 699d4fa1a1SMauro Carvalho Chehab \return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred} 709d4fa1a1SMauro Carvalho Chehab */ 719d4fa1a1SMauro Carvalho Chehab void receiver_set_compression( 729d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 739d4fa1a1SMauro Carvalho Chehab const unsigned int cfg_ID, 749d4fa1a1SMauro Carvalho Chehab const mipi_compressor_t comp, 759d4fa1a1SMauro Carvalho Chehab const mipi_predictor_t pred); 769d4fa1a1SMauro Carvalho Chehab 779d4fa1a1SMauro Carvalho Chehab /*! Enable PORT[port_ID] of RECEIVER[ID] 789d4fa1a1SMauro Carvalho Chehab 799d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 809d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 819d4fa1a1SMauro Carvalho Chehab \param cnd[in] irq predicate 829d4fa1a1SMauro Carvalho Chehab 839d4fa1a1SMauro Carvalho Chehab \return None, enable(RECEIVER[ID].PORT[port_ID]) 849d4fa1a1SMauro Carvalho Chehab */ 859d4fa1a1SMauro Carvalho Chehab void receiver_port_enable( 869d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 879d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID, 889d4fa1a1SMauro Carvalho Chehab const bool cnd); 899d4fa1a1SMauro Carvalho Chehab 909d4fa1a1SMauro Carvalho Chehab /*! Flag if PORT[port_ID] of RECEIVER[ID] is enabled 919d4fa1a1SMauro Carvalho Chehab 929d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 939d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 949d4fa1a1SMauro Carvalho Chehab 959d4fa1a1SMauro Carvalho Chehab \return enable(RECEIVER[ID].PORT[port_ID]) == true 969d4fa1a1SMauro Carvalho Chehab */ 979d4fa1a1SMauro Carvalho Chehab bool is_receiver_port_enabled( 989d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 999d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID); 1009d4fa1a1SMauro Carvalho Chehab 1019d4fa1a1SMauro Carvalho Chehab /*! Enable the IRQ channels of PORT[port_ID] of RECEIVER[ID] 1029d4fa1a1SMauro Carvalho Chehab 1039d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1049d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 1059d4fa1a1SMauro Carvalho Chehab \param irq_info[in] irq channels 1069d4fa1a1SMauro Carvalho Chehab 1079d4fa1a1SMauro Carvalho Chehab \return None, enable(RECEIVER[ID].PORT[port_ID].irq_info) 1089d4fa1a1SMauro Carvalho Chehab */ 1099d4fa1a1SMauro Carvalho Chehab void receiver_irq_enable( 1109d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1119d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID, 1129d4fa1a1SMauro Carvalho Chehab const rx_irq_info_t irq_info); 1139d4fa1a1SMauro Carvalho Chehab 1149d4fa1a1SMauro Carvalho Chehab /*! Return the IRQ status of PORT[port_ID] of RECEIVER[ID] 1159d4fa1a1SMauro Carvalho Chehab 1169d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1179d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 1189d4fa1a1SMauro Carvalho Chehab 1199d4fa1a1SMauro Carvalho Chehab \return RECEIVER[ID].PORT[port_ID].irq_info 1209d4fa1a1SMauro Carvalho Chehab */ 1219d4fa1a1SMauro Carvalho Chehab rx_irq_info_t receiver_get_irq_info( 1229d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1239d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID); 1249d4fa1a1SMauro Carvalho Chehab 1259d4fa1a1SMauro Carvalho Chehab /*! Clear the IRQ status of PORT[port_ID] of RECEIVER[ID] 1269d4fa1a1SMauro Carvalho Chehab 1279d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1289d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 1299d4fa1a1SMauro Carvalho Chehab \param irq_info[in] irq status 1309d4fa1a1SMauro Carvalho Chehab 1319d4fa1a1SMauro Carvalho Chehab \return None, clear(RECEIVER[ID].PORT[port_ID].irq_info) 1329d4fa1a1SMauro Carvalho Chehab */ 1339d4fa1a1SMauro Carvalho Chehab void receiver_irq_clear( 1349d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1359d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID, 1369d4fa1a1SMauro Carvalho Chehab const rx_irq_info_t irq_info); 1379d4fa1a1SMauro Carvalho Chehab 1389d4fa1a1SMauro Carvalho Chehab /*! Write to a control register of INPUT_SYSTEM[ID] 1399d4fa1a1SMauro Carvalho Chehab 1409d4fa1a1SMauro Carvalho Chehab \param ID[in] INPUT_SYSTEM identifier 1419d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 1429d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 1439d4fa1a1SMauro Carvalho Chehab 1449d4fa1a1SMauro Carvalho Chehab \return none, INPUT_SYSTEM[ID].ctrl[reg] = value 1459d4fa1a1SMauro Carvalho Chehab */ 1469d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H void input_system_reg_store( 1479d4fa1a1SMauro Carvalho Chehab const input_system_ID_t ID, 1489d4fa1a1SMauro Carvalho Chehab const hrt_address reg, 1499d4fa1a1SMauro Carvalho Chehab const hrt_data value); 1509d4fa1a1SMauro Carvalho Chehab 1519d4fa1a1SMauro Carvalho Chehab /*! Read from a control register of INPUT_SYSTEM[ID] 1529d4fa1a1SMauro Carvalho Chehab 1539d4fa1a1SMauro Carvalho Chehab \param ID[in] INPUT_SYSTEM identifier 1549d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 1559d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 1569d4fa1a1SMauro Carvalho Chehab 1579d4fa1a1SMauro Carvalho Chehab \return INPUT_SYSTEM[ID].ctrl[reg] 1589d4fa1a1SMauro Carvalho Chehab */ 1599d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_reg_load( 1609d4fa1a1SMauro Carvalho Chehab const input_system_ID_t ID, 1619d4fa1a1SMauro Carvalho Chehab const hrt_address reg); 1629d4fa1a1SMauro Carvalho Chehab 1639d4fa1a1SMauro Carvalho Chehab /*! Write to a control register of RECEIVER[ID] 1649d4fa1a1SMauro Carvalho Chehab 1659d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1669d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 1679d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 1689d4fa1a1SMauro Carvalho Chehab 1699d4fa1a1SMauro Carvalho Chehab \return none, RECEIVER[ID].ctrl[reg] = value 1709d4fa1a1SMauro Carvalho Chehab */ 1719d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H void receiver_reg_store( 1729d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1739d4fa1a1SMauro Carvalho Chehab const hrt_address reg, 1749d4fa1a1SMauro Carvalho Chehab const hrt_data value); 1759d4fa1a1SMauro Carvalho Chehab 1769d4fa1a1SMauro Carvalho Chehab /*! Read from a control register of RECEIVER[ID] 1779d4fa1a1SMauro Carvalho Chehab 1789d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1799d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 1809d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 1819d4fa1a1SMauro Carvalho Chehab 1829d4fa1a1SMauro Carvalho Chehab \return RECEIVER[ID].ctrl[reg] 1839d4fa1a1SMauro Carvalho Chehab */ 1849d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_reg_load( 1859d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1869d4fa1a1SMauro Carvalho Chehab const hrt_address reg); 1879d4fa1a1SMauro Carvalho Chehab 1889d4fa1a1SMauro Carvalho Chehab /*! Write to a control register of PORT[port_ID] of RECEIVER[ID] 1899d4fa1a1SMauro Carvalho Chehab 1909d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 1919d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 1929d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 1939d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 1949d4fa1a1SMauro Carvalho Chehab 1959d4fa1a1SMauro Carvalho Chehab \return none, RECEIVER[ID].PORT[port_ID].ctrl[reg] = value 1969d4fa1a1SMauro Carvalho Chehab */ 1979d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H void receiver_port_reg_store( 1989d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 1999d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID, 2009d4fa1a1SMauro Carvalho Chehab const hrt_address reg, 2019d4fa1a1SMauro Carvalho Chehab const hrt_data value); 2029d4fa1a1SMauro Carvalho Chehab 2039d4fa1a1SMauro Carvalho Chehab /*! Read from a control register PORT[port_ID] of of RECEIVER[ID] 2049d4fa1a1SMauro Carvalho Chehab 2059d4fa1a1SMauro Carvalho Chehab \param ID[in] RECEIVER identifier 2069d4fa1a1SMauro Carvalho Chehab \param port_ID[in] mipi PORT identifier 2079d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 2089d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 2099d4fa1a1SMauro Carvalho Chehab 2109d4fa1a1SMauro Carvalho Chehab \return RECEIVER[ID].PORT[port_ID].ctrl[reg] 2119d4fa1a1SMauro Carvalho Chehab */ 2129d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_port_reg_load( 2139d4fa1a1SMauro Carvalho Chehab const rx_ID_t ID, 2149d4fa1a1SMauro Carvalho Chehab const enum mipi_port_id port_ID, 2159d4fa1a1SMauro Carvalho Chehab const hrt_address reg); 2169d4fa1a1SMauro Carvalho Chehab 2179d4fa1a1SMauro Carvalho Chehab /*! Write to a control register of SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID] 2189d4fa1a1SMauro Carvalho Chehab 2199d4fa1a1SMauro Carvalho Chehab \param ID[in] INPUT_SYSTEM identifier 2209d4fa1a1SMauro Carvalho Chehab \param port_ID[in] sub system identifier 2219d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 2229d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 2239d4fa1a1SMauro Carvalho Chehab 2249d4fa1a1SMauro Carvalho Chehab \return none, INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] = value 2259d4fa1a1SMauro Carvalho Chehab */ 2269d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H void input_system_sub_system_reg_store( 2279d4fa1a1SMauro Carvalho Chehab const input_system_ID_t ID, 2289d4fa1a1SMauro Carvalho Chehab const sub_system_ID_t sub_ID, 2299d4fa1a1SMauro Carvalho Chehab const hrt_address reg, 2309d4fa1a1SMauro Carvalho Chehab const hrt_data value); 2319d4fa1a1SMauro Carvalho Chehab 2329d4fa1a1SMauro Carvalho Chehab /*! Read from a control register SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID] 2339d4fa1a1SMauro Carvalho Chehab 2349d4fa1a1SMauro Carvalho Chehab \param ID[in] INPUT_SYSTEM identifier 2359d4fa1a1SMauro Carvalho Chehab \param port_ID[in] sub system identifier 2369d4fa1a1SMauro Carvalho Chehab \param reg[in] register index 2379d4fa1a1SMauro Carvalho Chehab \param value[in] The data to be written 2389d4fa1a1SMauro Carvalho Chehab 2399d4fa1a1SMauro Carvalho Chehab \return INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] 2409d4fa1a1SMauro Carvalho Chehab */ 2419d4fa1a1SMauro Carvalho Chehab STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_sub_system_reg_load( 2429d4fa1a1SMauro Carvalho Chehab const input_system_ID_t ID, 2439d4fa1a1SMauro Carvalho Chehab const sub_system_ID_t sub_ID, 2449d4fa1a1SMauro Carvalho Chehab const hrt_address reg); 2459d4fa1a1SMauro Carvalho Chehab 2469d4fa1a1SMauro Carvalho Chehab /////////////////////////////////////////////////////////////////////////// 2479d4fa1a1SMauro Carvalho Chehab // 2489d4fa1a1SMauro Carvalho Chehab // Functions for configuration phase on input system. 2499d4fa1a1SMauro Carvalho Chehab // 2509d4fa1a1SMauro Carvalho Chehab /////////////////////////////////////////////////////////////////////////// 2519d4fa1a1SMauro Carvalho Chehab 2529d4fa1a1SMauro Carvalho Chehab // Function that resets current configuration. 2539d4fa1a1SMauro Carvalho Chehab // remove the argument since it should be private. 25439bc26e4SMauro Carvalho Chehab input_system_err_t input_system_configuration_reset(void); 2559d4fa1a1SMauro Carvalho Chehab 2569d4fa1a1SMauro Carvalho Chehab // Function that commits current configuration. 2579d4fa1a1SMauro Carvalho Chehab // remove the argument since it should be private. 25839bc26e4SMauro Carvalho Chehab input_system_err_t input_system_configuration_commit(void); 2599d4fa1a1SMauro Carvalho Chehab 2609d4fa1a1SMauro Carvalho Chehab /////////////////////////////////////////////////////////////////////////// 2619d4fa1a1SMauro Carvalho Chehab // 2629d4fa1a1SMauro Carvalho Chehab // User functions: 2639d4fa1a1SMauro Carvalho Chehab // (encoded generic function) 2649d4fa1a1SMauro Carvalho Chehab // - no checking 2659d4fa1a1SMauro Carvalho Chehab // - decoding name and agruments into the generic (channel) configuration 2669d4fa1a1SMauro Carvalho Chehab // function. 2679d4fa1a1SMauro Carvalho Chehab // 2689d4fa1a1SMauro Carvalho Chehab /////////////////////////////////////////////////////////////////////////// 2699d4fa1a1SMauro Carvalho Chehab 2709d4fa1a1SMauro Carvalho Chehab // FIFO channel config function user 2719d4fa1a1SMauro Carvalho Chehab 27239bc26e4SMauro Carvalho Chehab input_system_err_t input_system_csi_fifo_channel_cfg( 2739d4fa1a1SMauro Carvalho Chehab u32 ch_id, 2749d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 2759d4fa1a1SMauro Carvalho Chehab backend_channel_cfg_t backend_ch, 2769d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 2779d4fa1a1SMauro Carvalho Chehab ); 2789d4fa1a1SMauro Carvalho Chehab 27939bc26e4SMauro Carvalho Chehab input_system_err_t input_system_csi_fifo_channel_with_counting_cfg( 2809d4fa1a1SMauro Carvalho Chehab u32 ch_id, 2819d4fa1a1SMauro Carvalho Chehab u32 nof_frame, 2829d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 2839d4fa1a1SMauro Carvalho Chehab backend_channel_cfg_t backend_ch, 2849d4fa1a1SMauro Carvalho Chehab u32 mem_region_size, 2859d4fa1a1SMauro Carvalho Chehab u32 nof_mem_regions, 2869d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 2879d4fa1a1SMauro Carvalho Chehab ); 2889d4fa1a1SMauro Carvalho Chehab 2899d4fa1a1SMauro Carvalho Chehab // SRAM channel config function user 2909d4fa1a1SMauro Carvalho Chehab 29139bc26e4SMauro Carvalho Chehab input_system_err_t input_system_csi_sram_channel_cfg( 2929d4fa1a1SMauro Carvalho Chehab u32 ch_id, 2939d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 2949d4fa1a1SMauro Carvalho Chehab backend_channel_cfg_t backend_ch, 2959d4fa1a1SMauro Carvalho Chehab u32 csi_mem_region_size, 2969d4fa1a1SMauro Carvalho Chehab u32 csi_nof_mem_regions, 2979d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 2989d4fa1a1SMauro Carvalho Chehab ); 2999d4fa1a1SMauro Carvalho Chehab 3009d4fa1a1SMauro Carvalho Chehab //XMEM channel config function user 3019d4fa1a1SMauro Carvalho Chehab 30239bc26e4SMauro Carvalho Chehab input_system_err_t input_system_csi_xmem_channel_cfg( 3039d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3049d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 3059d4fa1a1SMauro Carvalho Chehab backend_channel_cfg_t backend_ch, 3069d4fa1a1SMauro Carvalho Chehab u32 mem_region_size, 3079d4fa1a1SMauro Carvalho Chehab u32 nof_mem_regions, 3089d4fa1a1SMauro Carvalho Chehab u32 acq_mem_region_size, 3099d4fa1a1SMauro Carvalho Chehab u32 acq_nof_mem_regions, 3109d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target, 3119d4fa1a1SMauro Carvalho Chehab uint32_t nof_xmem_buffers 3129d4fa1a1SMauro Carvalho Chehab ); 3139d4fa1a1SMauro Carvalho Chehab 31439bc26e4SMauro Carvalho Chehab input_system_err_t input_system_csi_xmem_capture_only_channel_cfg( 3159d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3169d4fa1a1SMauro Carvalho Chehab u32 nof_frames, 3179d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 3189d4fa1a1SMauro Carvalho Chehab u32 csi_mem_region_size, 3199d4fa1a1SMauro Carvalho Chehab u32 csi_nof_mem_regions, 3209d4fa1a1SMauro Carvalho Chehab u32 acq_mem_region_size, 3219d4fa1a1SMauro Carvalho Chehab u32 acq_nof_mem_regions, 3229d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 3239d4fa1a1SMauro Carvalho Chehab ); 3249d4fa1a1SMauro Carvalho Chehab 32539bc26e4SMauro Carvalho Chehab input_system_err_t input_system_csi_xmem_acquire_only_channel_cfg( 3269d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3279d4fa1a1SMauro Carvalho Chehab u32 nof_frames, 3289d4fa1a1SMauro Carvalho Chehab input_system_csi_port_t port, 3299d4fa1a1SMauro Carvalho Chehab backend_channel_cfg_t backend_ch, 3309d4fa1a1SMauro Carvalho Chehab u32 acq_mem_region_size, 3319d4fa1a1SMauro Carvalho Chehab u32 acq_nof_mem_regions, 3329d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 3339d4fa1a1SMauro Carvalho Chehab ); 3349d4fa1a1SMauro Carvalho Chehab 3359d4fa1a1SMauro Carvalho Chehab // Non - CSI channel config function user 3369d4fa1a1SMauro Carvalho Chehab 33739bc26e4SMauro Carvalho Chehab input_system_err_t input_system_prbs_channel_cfg( 3389d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3399d4fa1a1SMauro Carvalho Chehab u32 nof_frames, 3409d4fa1a1SMauro Carvalho Chehab u32 seed, 3419d4fa1a1SMauro Carvalho Chehab u32 sync_gen_width, 3429d4fa1a1SMauro Carvalho Chehab u32 sync_gen_height, 3439d4fa1a1SMauro Carvalho Chehab u32 sync_gen_hblank_cycles, 3449d4fa1a1SMauro Carvalho Chehab u32 sync_gen_vblank_cycles, 3459d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 3469d4fa1a1SMauro Carvalho Chehab ); 3479d4fa1a1SMauro Carvalho Chehab 34839bc26e4SMauro Carvalho Chehab input_system_err_t input_system_tpg_channel_cfg( 3499d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3509d4fa1a1SMauro Carvalho Chehab u32 nof_frames,//not used yet 3519d4fa1a1SMauro Carvalho Chehab u32 x_mask, 3529d4fa1a1SMauro Carvalho Chehab u32 y_mask, 3539d4fa1a1SMauro Carvalho Chehab u32 x_delta, 3549d4fa1a1SMauro Carvalho Chehab u32 y_delta, 3559d4fa1a1SMauro Carvalho Chehab u32 xy_mask, 3569d4fa1a1SMauro Carvalho Chehab u32 sync_gen_width, 3579d4fa1a1SMauro Carvalho Chehab u32 sync_gen_height, 3589d4fa1a1SMauro Carvalho Chehab u32 sync_gen_hblank_cycles, 3599d4fa1a1SMauro Carvalho Chehab u32 sync_gen_vblank_cycles, 3609d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 3619d4fa1a1SMauro Carvalho Chehab ); 3629d4fa1a1SMauro Carvalho Chehab 36339bc26e4SMauro Carvalho Chehab input_system_err_t input_system_gpfifo_channel_cfg( 3649d4fa1a1SMauro Carvalho Chehab u32 ch_id, 3659d4fa1a1SMauro Carvalho Chehab u32 nof_frames, 3669d4fa1a1SMauro Carvalho Chehab target_cfg2400_t target 3679d4fa1a1SMauro Carvalho Chehab ); 368641c2292SMauro Carvalho Chehab #endif /* #ifdef ISP2401 */ 3699d4fa1a1SMauro Carvalho Chehab 3709d4fa1a1SMauro Carvalho Chehab #endif /* __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ */ 371