1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2010-2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef __INPUT_SYSTEM_LOCAL_H_INCLUDED__ 17 #define __INPUT_SYSTEM_LOCAL_H_INCLUDED__ 18 19 #include <type_support.h> 20 21 #include "input_system_global.h" 22 23 #include "input_system_defs.h" /* HIVE_ISYS_GPREG_MULTICAST_A_IDX,... */ 24 25 /* 26 * _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX, 27 * _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX,... 28 */ 29 #include "css_receiver_2400_defs.h" 30 31 #include "isp_capture_defs.h" 32 33 #include "isp_acquisition_defs.h" 34 #include "input_system_ctrl_defs.h" 35 36 typedef enum { 37 INPUT_SYSTEM_ERR_NO_ERROR = 0, 38 INPUT_SYSTEM_ERR_GENERIC, 39 INPUT_SYSTEM_ERR_CHANNEL_ALREADY_SET, 40 INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE, 41 INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED, 42 N_INPUT_SYSTEM_ERR 43 } input_system_error_t; 44 45 typedef enum { 46 INPUT_SYSTEM_PORT_A = 0, 47 INPUT_SYSTEM_PORT_B, 48 INPUT_SYSTEM_PORT_C, 49 N_INPUT_SYSTEM_PORTS 50 } input_system_csi_port_t; 51 52 typedef struct ctrl_unit_cfg_s ctrl_unit_cfg_t; 53 typedef struct input_system_network_cfg_s input_system_network_cfg_t; 54 typedef struct target_cfg2400_s target_cfg2400_t; 55 typedef struct channel_cfg_s channel_cfg_t; 56 typedef struct backend_channel_cfg_s backend_channel_cfg_t; 57 typedef struct input_system_cfg2400_s input_system_cfg2400_t; 58 typedef struct mipi_port_state_s mipi_port_state_t; 59 typedef struct rx_channel_state_s rx_channel_state_t; 60 typedef struct input_switch_cfg_channel_s input_switch_cfg_channel_t; 61 typedef struct input_switch_cfg_s input_switch_cfg_t; 62 63 struct ctrl_unit_cfg_s { 64 ib_buffer_t buffer_mipi[N_CAPTURE_UNIT_ID]; 65 ib_buffer_t buffer_acquire[N_ACQUISITION_UNIT_ID]; 66 }; 67 68 struct input_system_network_cfg_s { 69 input_system_connection_t multicast_cfg[N_CAPTURE_UNIT_ID]; 70 input_system_multiplex_t mux_cfg; 71 ctrl_unit_cfg_t ctrl_unit_cfg[N_CTRL_UNIT_ID]; 72 }; 73 74 typedef struct { 75 // TBD. 76 u32 dummy_parameter; 77 } target_isp_cfg_t; 78 79 typedef struct { 80 // TBD. 81 u32 dummy_parameter; 82 } target_sp_cfg_t; 83 84 typedef struct { 85 // TBD. 86 u32 dummy_parameter; 87 } target_strm2mem_cfg_t; 88 89 struct input_switch_cfg_channel_s { 90 u32 hsync_data_reg[2]; 91 u32 vsync_data_reg; 92 }; 93 94 struct target_cfg2400_s { 95 input_switch_cfg_channel_t input_switch_channel_cfg; 96 target_isp_cfg_t target_isp_cfg; 97 target_sp_cfg_t target_sp_cfg; 98 target_strm2mem_cfg_t target_strm2mem_cfg; 99 }; 100 101 struct backend_channel_cfg_s { 102 u32 fmt_control_word_1; // Format config. 103 u32 fmt_control_word_2; 104 u32 no_side_band; 105 }; 106 107 typedef union { 108 csi_cfg_t csi_cfg; 109 tpg_cfg_t tpg_cfg; 110 prbs_cfg_t prbs_cfg; 111 gpfifo_cfg_t gpfifo_cfg; 112 } source_cfg_t; 113 114 struct input_switch_cfg_s { 115 u32 hsync_data_reg[N_RX_CHANNEL_ID * 2]; 116 u32 vsync_data_reg; 117 }; 118 119 // Configuration of a channel. 120 struct channel_cfg_s { 121 u32 ch_id; 122 backend_channel_cfg_t backend_ch; 123 input_system_source_t source_type; 124 source_cfg_t source_cfg; 125 target_cfg2400_t target_cfg; 126 }; 127 128 // Complete configuration for input system. 129 struct input_system_cfg2400_s { 130 input_system_source_t source_type; 131 input_system_config_flags_t source_type_flags; 132 //channel_cfg_t channel[N_CHANNELS]; 133 input_system_config_flags_t ch_flags[N_CHANNELS]; 134 // This is the place where the buffers' settings are collected, as given. 135 csi_cfg_t csi_value[N_CSI_PORTS]; 136 input_system_config_flags_t csi_flags[N_CSI_PORTS]; 137 138 // Possible another struct for ib. 139 // This buffers set at the end, based on the all configurations. 140 ib_buffer_t csi_buffer[N_CSI_PORTS]; 141 input_system_config_flags_t csi_buffer_flags[N_CSI_PORTS]; 142 ib_buffer_t acquisition_buffer_unique; 143 input_system_config_flags_t acquisition_buffer_unique_flags; 144 u32 unallocated_ib_mem_words; // Used for check.DEFAULT = IB_CAPACITY_IN_WORDS. 145 //uint32_t acq_allocated_ib_mem_words; 146 147 input_system_connection_t multicast[N_CSI_PORTS]; 148 input_system_multiplex_t multiplexer; 149 input_system_config_flags_t multiplexer_flags; 150 151 tpg_cfg_t tpg_value; 152 input_system_config_flags_t tpg_flags; 153 prbs_cfg_t prbs_value; 154 input_system_config_flags_t prbs_flags; 155 gpfifo_cfg_t gpfifo_value; 156 input_system_config_flags_t gpfifo_flags; 157 158 input_switch_cfg_t input_switch_cfg; 159 160 target_isp_cfg_t target_isp[N_CHANNELS]; 161 input_system_config_flags_t target_isp_flags[N_CHANNELS]; 162 target_sp_cfg_t target_sp[N_CHANNELS]; 163 input_system_config_flags_t target_sp_flags[N_CHANNELS]; 164 target_strm2mem_cfg_t target_strm2mem[N_CHANNELS]; 165 input_system_config_flags_t target_strm2mem_flags[N_CHANNELS]; 166 167 input_system_config_flags_t session_flags; 168 169 }; 170 171 /* 172 * For each MIPI port 173 */ 174 #define _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 175 #define _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 176 #define _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 177 #define _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 178 #define _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 179 /* new regs for each MIPI port w.r.t. 2300 */ 180 #define _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 181 #define _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 182 #define _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 183 184 /* _HRT_CSS_RECEIVER_2400_COMP_FORMAT_REG_IDX is not defined per MIPI port but per channel */ 185 /* _HRT_CSS_RECEIVER_2400_COMP_PREDICT_REG_IDX is not defined per MIPI port but per channel */ 186 #define _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 187 #define _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 188 #define _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 189 #define _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 190 #define _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 191 #define _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 192 #define _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 193 #define _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 194 #define _HRT_CSS_RECEIVER_RAW18_REG_IDX _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 195 #define _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 196 #define _HRT_CSS_RECEIVER_RAW16_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 197 198 /* Previously MIPI port regs, now 2x2 logical channel regs */ 199 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 200 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 201 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 202 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 203 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 204 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 205 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 206 #define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 207 208 /* Second backend is at offset 0x0700 w.r.t. the first port at offset 0x0100 */ 209 #define _HRT_CSS_BE_OFFSET 448 210 #define _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX + _HRT_CSS_BE_OFFSET) 211 #define _HRT_CSS_RECEIVER_BE_SRST_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX + _HRT_CSS_BE_OFFSET) 212 #define _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX + _HRT_CSS_BE_OFFSET) 213 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX + _HRT_CSS_BE_OFFSET) 214 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX + _HRT_CSS_BE_OFFSET) 215 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX + _HRT_CSS_BE_OFFSET) 216 #define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX + _HRT_CSS_BE_OFFSET) 217 #define _HRT_CSS_RECEIVER_BE_SEL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX + _HRT_CSS_BE_OFFSET) 218 #define _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET) 219 #define _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET) 220 #define _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX + _HRT_CSS_BE_OFFSET) 221 #define _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX + _HRT_CSS_BE_OFFSET) 222 #define _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX + _HRT_CSS_BE_OFFSET) 223 224 #define _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 225 #define _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 226 #define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 227 #define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 228 #define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 229 #define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 230 #define _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 231 #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 232 #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 233 #define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 234 #define _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 235 #define _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 236 #define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 237 #define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 238 #define _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 239 #define _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 240 #define _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 241 242 #define _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 243 #define _HRT_CSS_RECEIVER_DATA_TIMEOUT_IDX _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 244 #define _HRT_CSS_RECEIVER_DATA_TIMEOUT_BITS _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 245 246 typedef struct capture_unit_state_s capture_unit_state_t; 247 typedef struct acquisition_unit_state_s acquisition_unit_state_t; 248 typedef struct ctrl_unit_state_s ctrl_unit_state_t; 249 250 /* 251 * In 2300 ports can be configured independently and stream 252 * formats need to be specified. In 2400, there are only 8 253 * supported configurations but the HW is fused to support 254 * only a single one. 255 * 256 * In 2300 the compressed format types are programmed by the 257 * user. In 2400 all stream formats are encoded on the stream. 258 * 259 * Use the enum to check validity of a user configuration 260 */ 261 typedef enum { 262 MONO_4L_1L_0L = 0, 263 MONO_3L_1L_0L, 264 MONO_2L_1L_0L, 265 MONO_1L_1L_0L, 266 STEREO_2L_1L_2L, 267 STEREO_3L_1L_1L, 268 STEREO_2L_1L_1L, 269 STEREO_1L_1L_1L, 270 N_RX_MODE 271 } rx_mode_t; 272 273 typedef enum { 274 MIPI_PREDICTOR_NONE = 0, 275 MIPI_PREDICTOR_TYPE1, 276 MIPI_PREDICTOR_TYPE2, 277 N_MIPI_PREDICTOR_TYPES 278 } mipi_predictor_t; 279 280 typedef enum { 281 MIPI_COMPRESSOR_NONE = 0, 282 MIPI_COMPRESSOR_10_6_10, 283 MIPI_COMPRESSOR_10_7_10, 284 MIPI_COMPRESSOR_10_8_10, 285 MIPI_COMPRESSOR_12_6_12, 286 MIPI_COMPRESSOR_12_7_12, 287 MIPI_COMPRESSOR_12_8_12, 288 N_MIPI_COMPRESSOR_METHODS 289 } mipi_compressor_t; 290 291 typedef enum { 292 MIPI_FORMAT_RGB888 = 0, 293 MIPI_FORMAT_RGB555, 294 MIPI_FORMAT_RGB444, 295 MIPI_FORMAT_RGB565, 296 MIPI_FORMAT_RGB666, 297 MIPI_FORMAT_RAW8, /* 5 */ 298 MIPI_FORMAT_RAW10, 299 MIPI_FORMAT_RAW6, 300 MIPI_FORMAT_RAW7, 301 MIPI_FORMAT_RAW12, 302 MIPI_FORMAT_RAW14, /* 10 */ 303 MIPI_FORMAT_YUV420_8, 304 MIPI_FORMAT_YUV420_10, 305 MIPI_FORMAT_YUV422_8, 306 MIPI_FORMAT_YUV422_10, 307 MIPI_FORMAT_CUSTOM0, /* 15 */ 308 MIPI_FORMAT_YUV420_8_LEGACY, 309 MIPI_FORMAT_EMBEDDED, 310 MIPI_FORMAT_CUSTOM1, 311 MIPI_FORMAT_CUSTOM2, 312 MIPI_FORMAT_CUSTOM3, /* 20 */ 313 MIPI_FORMAT_CUSTOM4, 314 MIPI_FORMAT_CUSTOM5, 315 MIPI_FORMAT_CUSTOM6, 316 MIPI_FORMAT_CUSTOM7, 317 MIPI_FORMAT_YUV420_8_SHIFT, /* 25 */ 318 MIPI_FORMAT_YUV420_10_SHIFT, 319 MIPI_FORMAT_RAW16, 320 MIPI_FORMAT_RAW18, 321 N_MIPI_FORMAT, 322 } mipi_format_t; 323 324 #define MIPI_FORMAT_JPEG MIPI_FORMAT_CUSTOM0 325 #define MIPI_FORMAT_BINARY_8 MIPI_FORMAT_CUSTOM0 326 #define N_MIPI_FORMAT_CUSTOM 8 327 328 /* The number of stores for compressed format types */ 329 #define N_MIPI_COMPRESSOR_CONTEXT (N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM) 330 331 typedef enum { 332 RX_IRQ_INFO_BUFFER_OVERRUN = 1UL << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT, 333 RX_IRQ_INFO_INIT_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT, 334 RX_IRQ_INFO_ENTER_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT, 335 RX_IRQ_INFO_EXIT_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT, 336 RX_IRQ_INFO_ECC_CORRECTED = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT, 337 RX_IRQ_INFO_ERR_SOT = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT, 338 RX_IRQ_INFO_ERR_SOT_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT, 339 RX_IRQ_INFO_ERR_CONTROL = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT, 340 RX_IRQ_INFO_ERR_ECC_DOUBLE = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT, 341 /* RX_IRQ_INFO_NO_ERR = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT, */ 342 RX_IRQ_INFO_ERR_CRC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT, 343 RX_IRQ_INFO_ERR_UNKNOWN_ID = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT, 344 RX_IRQ_INFO_ERR_FRAME_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT, 345 RX_IRQ_INFO_ERR_FRAME_DATA = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT, 346 RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT, 347 RX_IRQ_INFO_ERR_UNKNOWN_ESC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT, 348 RX_IRQ_INFO_ERR_LINE_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT, 349 } rx_irq_info_t; 350 351 typedef struct rx_cfg_s rx_cfg_t; 352 353 /* 354 * Applied per port 355 */ 356 struct rx_cfg_s { 357 rx_mode_t mode; /* The HW config */ 358 enum mipi_port_id port; /* The port ID to apply the control on */ 359 unsigned int timeout; 360 unsigned int initcount; 361 unsigned int synccount; 362 unsigned int rxcount; 363 mipi_predictor_t comp; /* Just for backward compatibility */ 364 bool is_two_ppc; 365 }; 366 367 /* NOTE: The base has already an offset of 0x0100 */ 368 static const hrt_address MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = { 369 0x00000000UL, 370 0x00000100UL, 371 0x00000200UL 372 }; 373 374 static const mipi_lane_cfg_t MIPI_PORT_MAXLANES[N_MIPI_PORT_ID] = { 375 MIPI_4LANE_CFG, 376 MIPI_1LANE_CFG, 377 MIPI_2LANE_CFG 378 }; 379 380 static const bool MIPI_PORT_ACTIVE[N_RX_MODE][N_MIPI_PORT_ID] = { 381 {true, true, false}, 382 {true, true, false}, 383 {true, true, false}, 384 {true, true, false}, 385 {true, true, true}, 386 {true, true, true}, 387 {true, true, true}, 388 {true, true, true} 389 }; 390 391 static const mipi_lane_cfg_t MIPI_PORT_LANES[N_RX_MODE][N_MIPI_PORT_ID] = { 392 {MIPI_4LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, 393 {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, 394 {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, 395 {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, 396 {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_2LANE_CFG}, 397 {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}, 398 {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}, 399 {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG} 400 }; 401 402 static const hrt_address SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = { 403 0x00001000UL, 404 0x00002000UL, 405 0x00003000UL, 406 0x00004000UL, 407 0x00005000UL, 408 0x00009000UL, 409 0x0000A000UL, 410 0x0000B000UL, 411 0x0000C000UL 412 }; 413 414 struct capture_unit_state_s { 415 int Packet_Length; 416 int Received_Length; 417 int Received_Short_Packets; 418 int Received_Long_Packets; 419 int Last_Command; 420 int Next_Command; 421 int Last_Acknowledge; 422 int Next_Acknowledge; 423 int FSM_State_Info; 424 int StartMode; 425 int Start_Addr; 426 int Mem_Region_Size; 427 int Num_Mem_Regions; 428 /* int Init; write-only registers 429 int Start; 430 int Stop; */ 431 }; 432 433 struct acquisition_unit_state_s { 434 /* int Init; write-only register */ 435 int Received_Short_Packets; 436 int Received_Long_Packets; 437 int Last_Command; 438 int Next_Command; 439 int Last_Acknowledge; 440 int Next_Acknowledge; 441 int FSM_State_Info; 442 int Int_Cntr_Info; 443 int Start_Addr; 444 int Mem_Region_Size; 445 int Num_Mem_Regions; 446 }; 447 448 struct ctrl_unit_state_s { 449 int last_cmd; 450 int next_cmd; 451 int last_ack; 452 int next_ack; 453 int top_fsm_state; 454 int captA_fsm_state; 455 int captB_fsm_state; 456 int captC_fsm_state; 457 int acq_fsm_state; 458 int captA_start_addr; 459 int captB_start_addr; 460 int captC_start_addr; 461 int captA_mem_region_size; 462 int captB_mem_region_size; 463 int captC_mem_region_size; 464 int captA_num_mem_regions; 465 int captB_num_mem_regions; 466 int captC_num_mem_regions; 467 int acq_start_addr; 468 int acq_mem_region_size; 469 int acq_num_mem_regions; 470 /* int ctrl_init; write only register */ 471 int capt_reserve_one_mem_region; 472 }; 473 474 struct input_system_state_s { 475 int str_multicastA_sel; 476 int str_multicastB_sel; 477 int str_multicastC_sel; 478 int str_mux_sel; 479 int str_mon_status; 480 int str_mon_irq_cond; 481 int str_mon_irq_en; 482 int isys_srst; 483 int isys_slv_reg_srst; 484 int str_deint_portA_cnt; 485 int str_deint_portB_cnt; 486 struct capture_unit_state_s capture_unit[N_CAPTURE_UNIT_ID]; 487 struct acquisition_unit_state_s acquisition_unit[N_ACQUISITION_UNIT_ID]; 488 struct ctrl_unit_state_s ctrl_unit_state[N_CTRL_UNIT_ID]; 489 }; 490 491 struct mipi_port_state_s { 492 int device_ready; 493 int irq_status; 494 int irq_enable; 495 u32 timeout_count; 496 u16 init_count; 497 u16 raw16_18; 498 u32 sync_count; /*4 x uint8_t */ 499 u32 rx_count; /*4 x uint8_t */ 500 u8 lane_sync_count[MIPI_4LANE_CFG]; 501 u8 lane_rx_count[MIPI_4LANE_CFG]; 502 }; 503 504 struct rx_channel_state_s { 505 u32 comp_scheme0; 506 u32 comp_scheme1; 507 mipi_predictor_t pred[N_MIPI_FORMAT_CUSTOM]; 508 mipi_compressor_t comp[N_MIPI_FORMAT_CUSTOM]; 509 }; 510 511 struct receiver_state_s { 512 u8 fs_to_ls_delay; 513 u8 ls_to_data_delay; 514 u8 data_to_le_delay; 515 u8 le_to_fe_delay; 516 u8 fe_to_fs_delay; 517 u8 le_to_fs_delay; 518 bool is_two_ppc; 519 int backend_rst; 520 u16 raw18; 521 bool force_raw8; 522 u16 raw16; 523 struct mipi_port_state_s mipi_port_state[N_MIPI_PORT_ID]; 524 struct rx_channel_state_s rx_channel_state[N_RX_CHANNEL_ID]; 525 int be_gsp_acc_ovl; 526 int be_srst; 527 int be_is_two_ppc; 528 int be_comp_format0; 529 int be_comp_format1; 530 int be_comp_format2; 531 int be_comp_format3; 532 int be_sel; 533 int be_raw16_config; 534 int be_raw18_config; 535 int be_force_raw8; 536 int be_irq_status; 537 int be_irq_clear; 538 }; 539 540 #endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */ 541