1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ 17 #define __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ 18 19 #define IS_INPUT_SYSTEM_VERSION_2 20 21 #include <type_support.h> 22 23 //CSI reveiver has 3 ports. 24 #define N_CSI_PORTS (3) 25 //AM: Use previous define for this. 26 27 //MIPI allows upto 4 channels. 28 #define N_CHANNELS (4) 29 // 12KB = 256bit x 384 words 30 #define IB_CAPACITY_IN_WORDS (384) 31 32 typedef enum { 33 MIPI_0LANE_CFG = 0, 34 MIPI_1LANE_CFG = 1, 35 MIPI_2LANE_CFG = 2, 36 MIPI_3LANE_CFG = 3, 37 MIPI_4LANE_CFG = 4 38 } mipi_lane_cfg_t; 39 40 typedef enum { 41 INPUT_SYSTEM_SOURCE_SENSOR = 0, 42 INPUT_SYSTEM_SOURCE_FIFO, 43 INPUT_SYSTEM_SOURCE_TPG, 44 INPUT_SYSTEM_SOURCE_PRBS, 45 INPUT_SYSTEM_SOURCE_MEMORY, 46 N_INPUT_SYSTEM_SOURCE 47 } input_system_source_t; 48 49 /* internal routing configuration */ 50 typedef enum { 51 INPUT_SYSTEM_DISCARD_ALL = 0, 52 INPUT_SYSTEM_CSI_BACKEND = 1, 53 INPUT_SYSTEM_INPUT_BUFFER = 2, 54 INPUT_SYSTEM_MULTICAST = 3, 55 N_INPUT_SYSTEM_CONNECTION 56 } input_system_connection_t; 57 58 typedef enum { 59 INPUT_SYSTEM_MIPI_PORT0, 60 INPUT_SYSTEM_MIPI_PORT1, 61 INPUT_SYSTEM_MIPI_PORT2, 62 INPUT_SYSTEM_ACQUISITION_UNIT, 63 N_INPUT_SYSTEM_MULTIPLEX 64 } input_system_multiplex_t; 65 66 typedef enum { 67 INPUT_SYSTEM_SINK_MEMORY = 0, 68 INPUT_SYSTEM_SINK_ISP, 69 INPUT_SYSTEM_SINK_SP, 70 N_INPUT_SYSTEM_SINK 71 } input_system_sink_t; 72 73 typedef enum { 74 INPUT_SYSTEM_FIFO_CAPTURE = 0, 75 INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING, 76 INPUT_SYSTEM_SRAM_BUFFERING, 77 INPUT_SYSTEM_XMEM_BUFFERING, 78 INPUT_SYSTEM_XMEM_CAPTURE, 79 INPUT_SYSTEM_XMEM_ACQUIRE, 80 N_INPUT_SYSTEM_BUFFERING_MODE 81 } buffering_mode_t; 82 83 typedef struct input_system_cfg_s input_system_cfg_t; 84 typedef struct sync_generator_cfg_s sync_generator_cfg_t; 85 typedef struct tpg_cfg_s tpg_cfg_t; 86 typedef struct prbs_cfg_s prbs_cfg_t; 87 88 /* MW: uint16_t should be sufficient */ 89 struct input_system_cfg_s { 90 u32 no_side_band; 91 u32 fmt_type; 92 u32 ch_id; 93 u32 input_mode; 94 }; 95 96 struct sync_generator_cfg_s { 97 u32 width; 98 u32 height; 99 u32 hblank_cycles; 100 u32 vblank_cycles; 101 }; 102 103 /* MW: tpg & prbs are exclusive */ 104 struct tpg_cfg_s { 105 u32 x_mask; 106 u32 y_mask; 107 u32 x_delta; 108 u32 y_delta; 109 u32 xy_mask; 110 sync_generator_cfg_t sync_gen_cfg; 111 }; 112 113 struct prbs_cfg_s { 114 u32 seed; 115 sync_generator_cfg_t sync_gen_cfg; 116 }; 117 118 struct gpfifo_cfg_s { 119 // TBD. 120 sync_generator_cfg_t sync_gen_cfg; 121 }; 122 123 typedef struct gpfifo_cfg_s gpfifo_cfg_t; 124 125 //ALX:Commented out to pass the compilation. 126 //typedef struct input_system_cfg_s input_system_cfg_t; 127 128 struct ib_buffer_s { 129 u32 mem_reg_size; 130 u32 nof_mem_regs; 131 u32 mem_reg_addr; 132 }; 133 134 typedef struct ib_buffer_s ib_buffer_t; 135 136 struct csi_cfg_s { 137 u32 csi_port; 138 buffering_mode_t buffering_mode; 139 ib_buffer_t csi_buffer; 140 ib_buffer_t acquisition_buffer; 141 u32 nof_xmem_buffers; 142 }; 143 144 typedef struct csi_cfg_s csi_cfg_t; 145 146 typedef enum { 147 INPUT_SYSTEM_CFG_FLAG_RESET = 0, 148 INPUT_SYSTEM_CFG_FLAG_SET = 1U << 0, 149 INPUT_SYSTEM_CFG_FLAG_BLOCKED = 1U << 1, 150 INPUT_SYSTEM_CFG_FLAG_REQUIRED = 1U << 2, 151 INPUT_SYSTEM_CFG_FLAG_CONFLICT = 1U << 3 // To mark a conflicting configuration. 152 } input_system_cfg_flag_t; 153 154 typedef u32 input_system_config_flags_t; 155 156 #endif /* __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ */ 157