19d4fa1a1SMauro Carvalho Chehab /* 29d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 39d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 49d4fa1a1SMauro Carvalho Chehab * 59d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 69d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 79d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 89d4fa1a1SMauro Carvalho Chehab * 99d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 109d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 119d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 129d4fa1a1SMauro Carvalho Chehab * more details. 139d4fa1a1SMauro Carvalho Chehab */ 149d4fa1a1SMauro Carvalho Chehab 159d4fa1a1SMauro Carvalho Chehab #ifndef _input_system_defs_h 169d4fa1a1SMauro Carvalho Chehab #define _input_system_defs_h 179d4fa1a1SMauro Carvalho Chehab 189d4fa1a1SMauro Carvalho Chehab /* csi controller modes */ 199d4fa1a1SMauro Carvalho Chehab #define HIVE_CSI_CONFIG_MAIN 0 209d4fa1a1SMauro Carvalho Chehab #define HIVE_CSI_CONFIG_STEREO1 4 219d4fa1a1SMauro Carvalho Chehab #define HIVE_CSI_CONFIG_STEREO2 8 229d4fa1a1SMauro Carvalho Chehab 239d4fa1a1SMauro Carvalho Chehab /* general purpose register IDs */ 249d4fa1a1SMauro Carvalho Chehab 259d4fa1a1SMauro Carvalho Chehab /* Stream Multicast select modes */ 269d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0 279d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1 289d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2 299d4fa1a1SMauro Carvalho Chehab 309d4fa1a1SMauro Carvalho Chehab /* Stream Mux select modes */ 319d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_MUX_IDX 3 329d4fa1a1SMauro Carvalho Chehab 339d4fa1a1SMauro Carvalho Chehab /* streaming monitor status and control */ 349d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4 359d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_STRMON_COND_IDX 5 369d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6 379d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_IDX 7 389d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8 399d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9 409d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10 419d4fa1a1SMauro Carvalho Chehab 429d4fa1a1SMauro Carvalho Chehab /* Bit numbers of the soft reset register */ 439d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0 449d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1 459d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2 469d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3 479d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4 489d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5 499d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6 509d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7 519d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8 529d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9 539d4fa1a1SMauro Carvalho Chehab /* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */ 549d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */ 559d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10 569d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11 579d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12 589d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13 599d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14 609d4fa1a1SMauro Carvalho Chehab /* -- */ 619d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15 629d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16 639d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17 649d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv 659d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_DMA_BIT 19 669d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20 679d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21 689d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22 699d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23 709d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24 719d4fa1a1SMauro Carvalho Chehab 729d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0 739d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1 749d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2 759d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3 769d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4 779d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5 789d4fa1a1SMauro Carvalho Chehab 799d4fa1a1SMauro Carvalho Chehab /* streaming monitor port id's */ 809d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_CAPA 0 819d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_CAPB 1 829d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_CAPC 2 839d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_ACQ 3 849d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4 859d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5 869d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6 879d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7 889d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_PIXA 8 899d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_PIXB 9 909d4fa1a1SMauro Carvalho Chehab 919d4fa1a1SMauro Carvalho Chehab /* interrupt bit ID's */ 929d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0 939d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1 949d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2 959d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3 969d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4 979d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5 989d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6 999d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7 1009d4fa1a1SMauro Carvalho Chehab /*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/ 1019d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8 1029d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9 1039d4fa1a1SMauro Carvalho Chehab /*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/ 1049d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10 1059d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11 1069d4fa1a1SMauro Carvalho Chehab /*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/ 1079d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12 1089d4fa1a1SMauro Carvalho Chehab /*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/ 1099d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13 1109d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14 1119d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15 1129d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CIO2AHB 16 1139d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_DMA_BIT_ID 17 1149d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18 1159d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_NUM_BITS 19 1169d4fa1a1SMauro Carvalho Chehab 1179d4fa1a1SMauro Carvalho Chehab /* DMA */ 1189d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_CHANNEL 0 1199d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_IBUF_DDR_CONN 0 1209d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_HEIGHT 1 1219d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */ 1229d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */ 1239d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_CROP 0 /* no cropping */ 1249d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */ 1259d4fa1a1SMauro Carvalho Chehab 1269d4fa1a1SMauro Carvalho Chehab #endif /* _input_system_defs_h */ 127