1f5fbb83fSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */ 29d4fa1a1SMauro Carvalho Chehab /* 39d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 49d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 59d4fa1a1SMauro Carvalho Chehab * 69d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 79d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 89d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 99d4fa1a1SMauro Carvalho Chehab * 109d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 119d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 129d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 139d4fa1a1SMauro Carvalho Chehab * more details. 149d4fa1a1SMauro Carvalho Chehab */ 159d4fa1a1SMauro Carvalho Chehab 169d4fa1a1SMauro Carvalho Chehab #ifndef _input_system_defs_h 179d4fa1a1SMauro Carvalho Chehab #define _input_system_defs_h 189d4fa1a1SMauro Carvalho Chehab 199d4fa1a1SMauro Carvalho Chehab /* csi controller modes */ 209d4fa1a1SMauro Carvalho Chehab #define HIVE_CSI_CONFIG_MAIN 0 219d4fa1a1SMauro Carvalho Chehab #define HIVE_CSI_CONFIG_STEREO1 4 229d4fa1a1SMauro Carvalho Chehab #define HIVE_CSI_CONFIG_STEREO2 8 239d4fa1a1SMauro Carvalho Chehab 249d4fa1a1SMauro Carvalho Chehab /* general purpose register IDs */ 259d4fa1a1SMauro Carvalho Chehab 269d4fa1a1SMauro Carvalho Chehab /* Stream Multicast select modes */ 279d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0 289d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1 299d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2 309d4fa1a1SMauro Carvalho Chehab 319d4fa1a1SMauro Carvalho Chehab /* Stream Mux select modes */ 329d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_MUX_IDX 3 339d4fa1a1SMauro Carvalho Chehab 349d4fa1a1SMauro Carvalho Chehab /* streaming monitor status and control */ 359d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4 369d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_STRMON_COND_IDX 5 379d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6 389d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_IDX 7 399d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8 409d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9 419d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10 429d4fa1a1SMauro Carvalho Chehab 439d4fa1a1SMauro Carvalho Chehab /* Bit numbers of the soft reset register */ 449d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0 459d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1 469d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2 479d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3 489d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4 499d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5 509d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6 519d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7 529d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8 539d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9 549d4fa1a1SMauro Carvalho Chehab /* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */ 559d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */ 569d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10 579d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11 589d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12 599d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13 609d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14 619d4fa1a1SMauro Carvalho Chehab /* -- */ 629d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15 639d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16 649d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17 659d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv 669d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_DMA_BIT 19 679d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20 689d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21 699d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22 709d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23 719d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24 729d4fa1a1SMauro Carvalho Chehab 739d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0 749d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1 759d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2 769d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3 779d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4 789d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5 799d4fa1a1SMauro Carvalho Chehab 809d4fa1a1SMauro Carvalho Chehab /* streaming monitor port id's */ 819d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_CAPA 0 829d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_CAPB 1 839d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_CAPC 2 849d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_ACQ 3 859d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4 869d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5 879d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6 889d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7 899d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_PIXA 8 909d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_STR_MON_PORT_PIXB 9 919d4fa1a1SMauro Carvalho Chehab 929d4fa1a1SMauro Carvalho Chehab /* interrupt bit ID's */ 939d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0 949d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1 959d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2 969d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3 979d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4 989d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5 999d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6 1009d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7 1019d4fa1a1SMauro Carvalho Chehab /*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/ 1029d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8 1039d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9 1049d4fa1a1SMauro Carvalho Chehab /*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/ 1059d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10 1069d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11 1079d4fa1a1SMauro Carvalho Chehab /*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/ 1089d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12 1099d4fa1a1SMauro Carvalho Chehab /*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/ 1109d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13 1119d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14 1129d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15 1139d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_CIO2AHB 16 1149d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_DMA_BIT_ID 17 1159d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18 1169d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_IRQ_NUM_BITS 19 1179d4fa1a1SMauro Carvalho Chehab 1189d4fa1a1SMauro Carvalho Chehab /* DMA */ 1199d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_CHANNEL 0 1209d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_IBUF_DDR_CONN 0 1219d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_HEIGHT 1 1229d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */ 1239d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */ 1249d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_CROP 0 /* no cropping */ 1259d4fa1a1SMauro Carvalho Chehab #define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */ 1269d4fa1a1SMauro Carvalho Chehab 1279d4fa1a1SMauro Carvalho Chehab #endif /* _input_system_defs_h */ 128