1f5fbb83fSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */ 29d4fa1a1SMauro Carvalho Chehab /* 39d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 49d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 59d4fa1a1SMauro Carvalho Chehab * 69d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 79d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 89d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 99d4fa1a1SMauro Carvalho Chehab * 109d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 119d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 129d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 139d4fa1a1SMauro Carvalho Chehab * more details. 149d4fa1a1SMauro Carvalho Chehab */ 159d4fa1a1SMauro Carvalho Chehab 169d4fa1a1SMauro Carvalho Chehab #ifndef _if_subsystem_defs_h__ 179d4fa1a1SMauro Carvalho Chehab #define _if_subsystem_defs_h__ 189d4fa1a1SMauro Carvalho Chehab 199d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 0 209d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1 1 219d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2 2 229d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3 3 239d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4 249d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5 259d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6 269d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7 279d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8 289d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_SRST_IDX 9 299d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10 309d4fa1a1SMauro Carvalho Chehab 319d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX 11 329d4fa1a1SMauro Carvalho Chehab 339d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 349d4fa1a1SMauro Carvalho Chehab 359d4fa1a1SMauro Carvalho Chehab /* order of the input bits for the ifmt irq controller */ 369d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID 0 379d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID 1 389d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID 2 399d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID 3 409d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID 4 419d4fa1a1SMauro Carvalho Chehab 429d4fa1a1SMauro Carvalho Chehab /* order of the input bits for the ifmt Soft reset register */ 439d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX 0 449d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX 1 459d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX 2 469d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX 3 479d4fa1a1SMauro Carvalho Chehab 489d4fa1a1SMauro Carvalho Chehab /* order of the input bits for the ifmt Soft reset register */ 499d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX 0 509d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX 1 519d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX 2 529d4fa1a1SMauro Carvalho Chehab #define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX 3 539d4fa1a1SMauro Carvalho Chehab 549d4fa1a1SMauro Carvalho Chehab #endif /* _if_subsystem_defs_h__ */ 55