19d4fa1a1SMauro Carvalho Chehab /* 29d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 39d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 49d4fa1a1SMauro Carvalho Chehab * 59d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 69d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 79d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 89d4fa1a1SMauro Carvalho Chehab * 99d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 109d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 119d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 129d4fa1a1SMauro Carvalho Chehab * more details. 139d4fa1a1SMauro Carvalho Chehab */ 149d4fa1a1SMauro Carvalho Chehab 159d4fa1a1SMauro Carvalho Chehab #ifndef _hive_isp_css_defs_h__ 169d4fa1a1SMauro Carvalho Chehab #define _hive_isp_css_defs_h__ 179d4fa1a1SMauro Carvalho Chehab 189d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_CTRL_DATA_WIDTH 32 199d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_CTRL_ADDRESS_WIDTH 32 209d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_CTRL_MAX_BURST_SIZE 1 219d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_DDR_ADDRESS_WIDTH 36 229d4fa1a1SMauro Carvalho Chehab 239d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_HOST_MAX_BURST_SIZE 8 /* host supports bursts in order to prevent repeating DDRAM accesses */ 249d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_NUM_GPIO_PINS 12 259d4fa1a1SMauro Carvalho Chehab 269d4fa1a1SMauro Carvalho Chehab /* This list of vector num_elems/elem_bits pairs is valid both in C as initializer 279d4fa1a1SMauro Carvalho Chehab and in the DMA parameter list */ 289d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}} 299d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_DDR_WORD_BITS 256 309d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS / 8) 319d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024) /* hss only */ 329d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024) /* RTL only */ 339d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8) 349d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_PAGE_SHIFT 12 359d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_PAGE_SIZE BIT(HIVE_ISP_PAGE_SHIFT) 369d4fa1a1SMauro Carvalho Chehab 379d4fa1a1SMauro Carvalho Chehab #define CSS_DDR_WORD_BITS HIVE_ISP_DDR_WORD_BITS 389d4fa1a1SMauro Carvalho Chehab #define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES 399d4fa1a1SMauro Carvalho Chehab 409d4fa1a1SMauro Carvalho Chehab /* If HIVE_ISP_DDR_BASE_OFFSET is set to a non-zero value, the wide bus just before the DDRAM gets an extra dummy port where */ 419d4fa1a1SMauro Carvalho Chehab /* address range 0 .. HIVE_ISP_DDR_BASE_OFFSET-1 maps onto. This effectively creates an offset for the DDRAM from system perspective */ 429d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_DDR_BASE_OFFSET 0x120000000 /* 0x200000 */ 439d4fa1a1SMauro Carvalho Chehab 449d4fa1a1SMauro Carvalho Chehab #define HIVE_DMA_ISP_BUS_CONN 0 459d4fa1a1SMauro Carvalho Chehab #define HIVE_DMA_ISP_DDR_CONN 1 469d4fa1a1SMauro Carvalho Chehab #define HIVE_DMA_BUS_DDR_CONN 2 479d4fa1a1SMauro Carvalho Chehab #define HIVE_DMA_ISP_MASTER master_port0 489d4fa1a1SMauro Carvalho Chehab #define HIVE_DMA_BUS_MASTER master_port1 499d4fa1a1SMauro Carvalho Chehab #define HIVE_DMA_DDR_MASTER master_port2 509d4fa1a1SMauro Carvalho Chehab 519d4fa1a1SMauro Carvalho Chehab #define HIVE_DMA_NUM_CHANNELS 32 /* old value was 8 */ 529d4fa1a1SMauro Carvalho Chehab #define HIVE_DMA_CMD_FIFO_DEPTH 24 /* old value was 12 */ 539d4fa1a1SMauro Carvalho Chehab 549d4fa1a1SMauro Carvalho Chehab #define HIVE_IF_PIXEL_WIDTH 12 559d4fa1a1SMauro Carvalho Chehab 569d4fa1a1SMauro Carvalho Chehab #define HIVE_MMU_TLB_SETS 8 579d4fa1a1SMauro Carvalho Chehab #define HIVE_MMU_TLB_SET_BLOCKS 8 589d4fa1a1SMauro Carvalho Chehab #define HIVE_MMU_TLB_BLOCK_ELEMENTS 8 599d4fa1a1SMauro Carvalho Chehab #define HIVE_MMU_PAGE_TABLE_LEVELS 2 609d4fa1a1SMauro Carvalho Chehab #define HIVE_MMU_PAGE_BYTES HIVE_ISP_PAGE_SIZE 619d4fa1a1SMauro Carvalho Chehab 629d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_CH_ID_BITS 2 639d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_FMT_TYPE_BITS 5 649d4fa1a1SMauro Carvalho Chehab #define HIVE_ISP_ISEL_SEL_BITS 2 659d4fa1a1SMauro Carvalho Chehab 669d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SDRAM_WAKEUP_IDX 0 679d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_IDLE_IDX 1 689d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_IRQ_0_IDX 2 699d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_IRQ_1_IDX 3 709d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SP_STREAM_STAT_IDX 4 719d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SP_STREAM_STAT_B_IDX 5 729d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_ISP_STREAM_STAT_IDX 6 739d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_MOD_STREAM_STAT_IDX 7 749d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_COND_IDX 8 759d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_COND_IDX 9 769d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_COND_IDX 10 779d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_COND_IDX 11 789d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_ENABLE_IDX 12 799d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_ENABLE_IDX 13 809d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_ENABLE_IDX 14 819d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_ENABLE_IDX 15 829d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SWITCH_PRIM_IF_IDX 16 839d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SWITCH_GDC1_IDX 17 849d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SWITCH_GDC2_IDX 18 859d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_IDX 19 869d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SLV_REG_SRST_IDX 20 879d4fa1a1SMauro Carvalho Chehab 889d4fa1a1SMauro Carvalho Chehab /* Bit numbers of the soft reset register */ 899d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_ISYS_CBUS 0 909d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_ISEL_CBUS 1 919d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_IFMT_CBUS 2 929d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_GPDEV_CBUS 3 939d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_GPIO 4 949d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_TC 5 959d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_GPTIMER 6 969d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_FACELLFIFOS 7 979d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_D_OSYS 8 989d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_IFT_SEC_PIPE 9 999d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_GDC1 10 1009d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_GDC2 11 1019d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_VEC_BUS 12 1029d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_ISP 13 1039d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_SLV_GRP_BUS 14 1049d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_DMA 15 1059d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_SF_ISP_SP 16 1069d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_SF_PIF_CELLS 17 1079d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_SF_SIF_SP 18 1089d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_SF_MC_SP 19 1099d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_SF_ISYS_SP 20 1109d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_SF_DMA_CELLS 21 1119d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_SF_GDC1_CELLS 22 1129d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_SF_GDC2_CELLS 23 1139d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_SP 24 1149d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_OCP2CIO 25 1159d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_NBUS 26 1169d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_HOST12BUS 27 1179d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_WBUS 28 1189d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_IC_OSYS 29 1199d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SRST_WBUS_IC 30 1209d4fa1a1SMauro Carvalho Chehab 1219d4fa1a1SMauro Carvalho Chehab /* Bit numbers of the slave register soft reset register */ 1229d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SLV_REG_SRST_DMA 0 1239d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SLV_REG_SRST_GDC1 1 1249d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_SLV_REG_SRST_GDC2 2 1259d4fa1a1SMauro Carvalho Chehab 1269d4fa1a1SMauro Carvalho Chehab /* order of the input bits for the irq controller */ 1279d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID 0 1289d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID 1 1299d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID 2 1309d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID 3 1319d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID 4 1329d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID 5 1339d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID 6 1349d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID 7 1359d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID 8 1369d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID 9 1379d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID 10 1389d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID 11 1399d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_SP_BIT_ID 12 1409d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_ISP_BIT_ID 13 1419d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_ISYS_BIT_ID 14 1429d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_ISEL_BIT_ID 15 1439d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_IFMT_BIT_ID 16 1449d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID 17 1459d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID 18 1469d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID 19 1479d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID 20 1489d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID 21 1499d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID 22 1509d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID 23 1519d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID 24 1529d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID 25 1539d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID 26 1549d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID 27 1559d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID 28 1569d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID 29 1579d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_DMA_BIT_ID 30 1589d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID 31 1599d4fa1a1SMauro Carvalho Chehab 1609d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_REGS_NUM_SW_IRQ_REGS 2 1619d4fa1a1SMauro Carvalho Chehab 1629d4fa1a1SMauro Carvalho Chehab /* order of the input bits for the timed controller */ 1639d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_0_BIT_ID 0 1649d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_1_BIT_ID 1 1659d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_2_BIT_ID 2 1669d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_3_BIT_ID 3 1679d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_4_BIT_ID 4 1689d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_5_BIT_ID 5 1699d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_6_BIT_ID 6 1709d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_7_BIT_ID 7 1719d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_8_BIT_ID 8 1729d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_9_BIT_ID 9 1739d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_10_BIT_ID 10 1749d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GPIO_PIN_11_BIT_ID 11 1759d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_SP_BIT_ID 12 1769d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_ISP_BIT_ID 13 1779d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_ISYS_BIT_ID 14 1789d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_ISEL_BIT_ID 15 1799d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_IFMT_BIT_ID 16 1809d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GP_TIMER_0_BIT_ID 17 1819d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_GP_TIMER_1_BIT_ID 18 1829d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_MIPI_SOL_BIT_ID 19 1839d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_MIPI_EOL_BIT_ID 20 1849d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_MIPI_SOF_BIT_ID 21 1859d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_MIPI_EOF_BIT_ID 22 1869d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_DEV_TC_INPSYS_SM 23 1879d4fa1a1SMauro Carvalho Chehab 1889d4fa1a1SMauro Carvalho Chehab /* definitions for the gp_timer block */ 1899d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_0 0 1909d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_1 1 1919d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_2 2 1929d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_3 3 1939d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_4 4 1949d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_5 5 1959d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_6 6 1969d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_7 7 1979d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_NUM_COUNTERS 8 1989d4fa1a1SMauro Carvalho Chehab 1999d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_IRQ_0 0 2009d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_IRQ_1 1 2019d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_NUM_IRQS 2 2029d4fa1a1SMauro Carvalho Chehab 2039d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_0_BIT_ID 0 2049d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_1_BIT_ID 1 2059d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_2_BIT_ID 2 2069d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_3_BIT_ID 3 2079d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_4_BIT_ID 4 2089d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_5_BIT_ID 5 2099d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_6_BIT_ID 6 2109d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_7_BIT_ID 7 2119d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_8_BIT_ID 8 2129d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_9_BIT_ID 9 2139d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_10_BIT_ID 10 2149d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_GPIO_11_BIT_ID 11 2159d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_INP_SYS_IRQ 12 2169d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISEL_IRQ 13 2179d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_IFMT_IRQ 14 2189d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_STRMON_IRQ 15 2199d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_B_STRMON_IRQ 16 2209d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_STRMON_IRQ 17 2219d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_MOD_STRMON_IRQ 18 2229d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_BAMEM_ERROR_IRQ 20 2239d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_DMEM_ERROR_IRQ 21 2249d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_ICACHE_MEM_ERROR_IRQ 22 2259d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ 23 2269d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_OUT_RUN_DP 24 2279d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 25 2289d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 26 2299d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I2 27 2309d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I3 28 2319d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I4 29 2329d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I5 30 2339d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I6 31 2349d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I7 32 2359d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I8 33 2369d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I9 34 2379d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I10 35 2389d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 36 2399d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 37 2409d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 38 2419d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_OUT_RUN_DP 39 2429d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 40 2439d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 41 2449d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 42 2459d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 43 2469d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I1 44 2479d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I2 45 2489d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I3 46 2499d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I4 47 2509d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I5 48 2519d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I6 49 2529d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 50 2539d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I4_I0 51 2549d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I5_I0 52 2559d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I6_I0 53 2569d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54 2579d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_MIPI_SOL_BIT_ID 55 2589d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_MIPI_EOL_BIT_ID 56 2599d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_MIPI_SOF_BIT_ID 57 2609d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_MIPI_EOF_BIT_ID 58 2619d4fa1a1SMauro Carvalho Chehab #define HIVE_GP_TIMER_INPSYS_SM 59 2629d4fa1a1SMauro Carvalho Chehab 2639d4fa1a1SMauro Carvalho Chehab /* port definitions for the streaming monitors */ 2649d4fa1a1SMauro Carvalho Chehab /* port definititions SP streaming monitor, monitors the status of streaming ports at the SP side of the streaming FIFO's */ 2659d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SP2SIF 0 2669d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SIF2SP 1 2679d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SP2MC 2 2689d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_MC2SP 3 2699d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SP2DMA 4 2709d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_DMA2SP 5 2719d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SP2ISP 6 2729d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_ISP2SP 7 2739d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SP2GPD 8 2749d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_FA2SP 9 2759d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SP2ISYS 10 2769d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_ISYS2SP 11 2779d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SP2PIFA 12 2789d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_PIFA2SP 13 2799d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SP2PIFB 14 2809d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_PIFB2SP 15 2819d4fa1a1SMauro Carvalho Chehab 2829d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_B_SP2GDC1 0 2839d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_B_GDC12SP 1 2849d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_B_SP2GDC2 2 2859d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_B_GDC22SP 3 2869d4fa1a1SMauro Carvalho Chehab 2879d4fa1a1SMauro Carvalho Chehab /* previously used SP streaming monitor port identifiers, kept for backward compatibility */ 2889d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SND_SIF SP_STR_MON_PORT_SP2SIF 2899d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_RCV_SIF SP_STR_MON_PORT_SIF2SP 2909d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SND_MC SP_STR_MON_PORT_SP2MC 2919d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_RCV_MC SP_STR_MON_PORT_MC2SP 2929d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SND_DMA SP_STR_MON_PORT_SP2DMA 2939d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_RCV_DMA SP_STR_MON_PORT_DMA2SP 2949d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SND_ISP SP_STR_MON_PORT_SP2ISP 2959d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_RCV_ISP SP_STR_MON_PORT_ISP2SP 2969d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SND_GPD SP_STR_MON_PORT_SP2GPD 2979d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_RCV_GPD SP_STR_MON_PORT_FA2SP 2989d4fa1a1SMauro Carvalho Chehab /* Deprecated */ 2999d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SND_PIF SP_STR_MON_PORT_SP2PIFA 3009d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_RCV_PIF SP_STR_MON_PORT_PIFA2SP 3019d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SND_PIFB SP_STR_MON_PORT_SP2PIFB 3029d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_RCV_PIFB SP_STR_MON_PORT_PIFB2SP 3039d4fa1a1SMauro Carvalho Chehab 3049d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SND_PIF_A SP_STR_MON_PORT_SP2PIFA 3059d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_RCV_PIF_A SP_STR_MON_PORT_PIFA2SP 3069d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_SND_PIF_B SP_STR_MON_PORT_SP2PIFB 3079d4fa1a1SMauro Carvalho Chehab #define SP_STR_MON_PORT_RCV_PIF_B SP_STR_MON_PORT_PIFB2SP 3089d4fa1a1SMauro Carvalho Chehab 3099d4fa1a1SMauro Carvalho Chehab /* port definititions ISP streaming monitor, monitors the status of streaming ports at the ISP side of the streaming FIFO's */ 3109d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_ISP2PIFA 0 3119d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_PIFA2ISP 1 3129d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_ISP2PIFB 2 3139d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_PIFB2ISP 3 3149d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_ISP2DMA 4 3159d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_DMA2ISP 5 3169d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_ISP2GDC1 6 3179d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_GDC12ISP 7 3189d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_ISP2GDC2 8 3199d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_GDC22ISP 9 3209d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_ISP2GPD 10 3219d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_FA2ISP 11 3229d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_ISP2SP 12 3239d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_SP2ISP 13 3249d4fa1a1SMauro Carvalho Chehab 3259d4fa1a1SMauro Carvalho Chehab /* previously used ISP streaming monitor port identifiers, kept for backward compatibility */ 3269d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_SND_PIF_A ISP_STR_MON_PORT_ISP2PIFA 3279d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_RCV_PIF_A ISP_STR_MON_PORT_PIFA2ISP 3289d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB 3299d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_RCV_PIF_B ISP_STR_MON_PORT_PIFB2ISP 3309d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA 3319d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP 3329d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1 3339d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_RCV_GDC ISP_STR_MON_PORT_GDC12ISP 3349d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD 3359d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_RCV_GPD ISP_STR_MON_PORT_FA2ISP 3369d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_SND_SP ISP_STR_MON_PORT_ISP2SP 3379d4fa1a1SMauro Carvalho Chehab #define ISP_STR_MON_PORT_RCV_SP ISP_STR_MON_PORT_SP2ISP 3389d4fa1a1SMauro Carvalho Chehab 3399d4fa1a1SMauro Carvalho Chehab /* port definititions MOD streaming monitor, monitors the status of streaming ports at the module side of the streaming FIFO's */ 3409d4fa1a1SMauro Carvalho Chehab 3419d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_PIFA2CELLS 0 3429d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_CELLS2PIFA 1 3439d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_PIFB2CELLS 2 3449d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_CELLS2PIFB 3 3459d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SIF2SP 4 3469d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SP2SIF 5 3479d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_MC2SP 6 3489d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SP2MC 7 3499d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_DMA2ISP 8 3509d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_ISP2DMA 9 3519d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_DMA2SP 10 3529d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SP2DMA 11 3539d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_GDC12CELLS 12 3549d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_CELLS2GDC1 13 3559d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_GDC22CELLS 14 3569d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_CELLS2GDC2 15 3579d4fa1a1SMauro Carvalho Chehab 3589d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SND_PIF_A 0 3599d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_RCV_PIF_A 1 3609d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SND_PIF_B 2 3619d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_RCV_PIF_B 3 3629d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SND_SIF 4 3639d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_RCV_SIF 5 3649d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SND_MC 6 3659d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_RCV_MC 7 3669d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SND_DMA2ISP 8 3679d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_RCV_DMA_FR_ISP 9 3689d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SND_DMA2SP 10 3699d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_RCV_DMA_FR_SP 11 3709d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_SND_GDC 12 3719d4fa1a1SMauro Carvalho Chehab #define MOD_STR_MON_PORT_RCV_GDC 13 3729d4fa1a1SMauro Carvalho Chehab 3739d4fa1a1SMauro Carvalho Chehab /* testbench signals: */ 3749d4fa1a1SMauro Carvalho Chehab 3759d4fa1a1SMauro Carvalho Chehab /* testbench GP adapter register ids */ 3769d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_GPIO_DATA_OUT_REG_IDX 0 3779d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_GPIO_DIR_OUT_REG_IDX 1 3789d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_IRQ_REG_IDX 2 3799d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SDRAM_WAKEUP_REG_IDX 3 3809d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_IDLE_REG_IDX 4 3819d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_GPIO_DATA_IN_REG_IDX 5 3829d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_MIPI_BFM_EN_REG_IDX 6 3839d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_CSI_CONFIG_REG_IDX 7 3849d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_DDR_STALL_EN_REG_IDX 8 3859d4fa1a1SMauro Carvalho Chehab 3869d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_ISP_PMEM_ERROR_IRQ_REG_IDX 9 3879d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_ISP_BAMEM_ERROR_IRQ_REG_IDX 10 3889d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_ISP_DMEM_ERROR_IRQ_REG_IDX 11 3899d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SP_ICACHE_MEM_ERROR_IRQ_REG_IDX 12 3909d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SP_DMEM_ERROR_IRQ_REG_IDX 13 3919d4fa1a1SMauro Carvalho Chehab 3929d4fa1a1SMauro Carvalho Chehab /* Signal monitor input bit ids */ 3939d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_O_BIT_ID 0 3949d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_1_BIT_ID 1 3959d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_2_BIT_ID 2 3969d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_3_BIT_ID 3 3979d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_4_BIT_ID 4 3989d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_5_BIT_ID 5 3999d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_6_BIT_ID 6 4009d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_7_BIT_ID 7 4019d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_8_BIT_ID 8 4029d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_9_BIT_ID 9 4039d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_10_BIT_ID 10 4049d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_11_BIT_ID 11 4059d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_IRQ_PIN_BIT_ID 12 4069d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_SDRAM_WAKEUP_PIN_BIT_ID 13 4079d4fa1a1SMauro Carvalho Chehab #define HIVE_TESTBENCH_SIG_MON_IDLE_PIN_BIT_ID 14 4089d4fa1a1SMauro Carvalho Chehab 4099d4fa1a1SMauro Carvalho Chehab #define ISP2400_DEBUG_NETWORK 1 4109d4fa1a1SMauro Carvalho Chehab 4119d4fa1a1SMauro Carvalho Chehab #endif /* _hive_isp_css_defs_h__ */ 412