19d4fa1a1SMauro Carvalho Chehab /* 29d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 39d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 49d4fa1a1SMauro Carvalho Chehab * 59d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 69d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 79d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 89d4fa1a1SMauro Carvalho Chehab * 99d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 109d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 119d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 129d4fa1a1SMauro Carvalho Chehab * more details. 139d4fa1a1SMauro Carvalho Chehab */ 149d4fa1a1SMauro Carvalho Chehab 159d4fa1a1SMauro Carvalho Chehab #ifndef __TIMED_CTRL_GLOBAL_H_INCLUDED__ 169d4fa1a1SMauro Carvalho Chehab #define __TIMED_CTRL_GLOBAL_H_INCLUDED__ 179d4fa1a1SMauro Carvalho Chehab 189d4fa1a1SMauro Carvalho Chehab #define IS_TIMED_CTRL_VERSION_1 199d4fa1a1SMauro Carvalho Chehab 209d4fa1a1SMauro Carvalho Chehab #include "timed_controller_defs.h" 219d4fa1a1SMauro Carvalho Chehab 229d4fa1a1SMauro Carvalho Chehab /** 239d4fa1a1SMauro Carvalho Chehab * Order of the input bits for the timed controller taken from 249d4fa1a1SMauro Carvalho Chehab * ISP_CSS_2401 System Architecture Description valid for 259d4fa1a1SMauro Carvalho Chehab * 2400, 2401. 269d4fa1a1SMauro Carvalho Chehab * 279d4fa1a1SMauro Carvalho Chehab * Check for other systems. 289d4fa1a1SMauro Carvalho Chehab */ 299d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_0_BIT_ID 0 309d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_1_BIT_ID 1 319d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_2_BIT_ID 2 329d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_3_BIT_ID 3 339d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_4_BIT_ID 4 349d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_5_BIT_ID 5 359d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_6_BIT_ID 6 369d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_7_BIT_ID 7 379d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_8_BIT_ID 8 389d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_9_BIT_ID 9 399d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_10_BIT_ID 10 409d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_11_BIT_ID 11 419d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_SP_BIT_ID 12 429d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_ISP_BIT_ID 13 439d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_INPUT_SYSTEM_BIT_ID 14 449d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_INPUT_SELECTOR_BIT_ID 15 459d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_IF_BLOCK_BIT_ID 16 469d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_GP_TIMER_0_BIT_ID 17 479d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_GP_TIMER_1_BIT_ID 18 489d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_CSI_SOL_BIT_ID 19 499d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_CSI_EOL_BIT_ID 20 509d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_CSI_SOF_BIT_ID 21 519d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_CSI_EOF_BIT_ID 22 529d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_IS_STREAMING_MONITOR_BIT_ID 23 539d4fa1a1SMauro Carvalho Chehab 549d4fa1a1SMauro Carvalho Chehab #endif /* __TIMED_CTRL_GLOBAL_H_INCLUDED__ */ 55