1f5fbb83fSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */ 29d4fa1a1SMauro Carvalho Chehab /* 39d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 49d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 59d4fa1a1SMauro Carvalho Chehab * 69d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 79d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 89d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 99d4fa1a1SMauro Carvalho Chehab * 109d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 119d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 129d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 139d4fa1a1SMauro Carvalho Chehab * more details. 149d4fa1a1SMauro Carvalho Chehab */ 159d4fa1a1SMauro Carvalho Chehab 169d4fa1a1SMauro Carvalho Chehab #ifndef __TIMED_CTRL_GLOBAL_H_INCLUDED__ 179d4fa1a1SMauro Carvalho Chehab #define __TIMED_CTRL_GLOBAL_H_INCLUDED__ 189d4fa1a1SMauro Carvalho Chehab 199d4fa1a1SMauro Carvalho Chehab #define IS_TIMED_CTRL_VERSION_1 209d4fa1a1SMauro Carvalho Chehab 219d4fa1a1SMauro Carvalho Chehab #include "timed_controller_defs.h" 229d4fa1a1SMauro Carvalho Chehab 239d4fa1a1SMauro Carvalho Chehab /** 249d4fa1a1SMauro Carvalho Chehab * Order of the input bits for the timed controller taken from 259d4fa1a1SMauro Carvalho Chehab * ISP_CSS_2401 System Architecture Description valid for 269d4fa1a1SMauro Carvalho Chehab * 2400, 2401. 279d4fa1a1SMauro Carvalho Chehab * 289d4fa1a1SMauro Carvalho Chehab * Check for other systems. 299d4fa1a1SMauro Carvalho Chehab */ 309d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_0_BIT_ID 0 319d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_1_BIT_ID 1 329d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_2_BIT_ID 2 339d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_3_BIT_ID 3 349d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_4_BIT_ID 4 359d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_5_BIT_ID 5 369d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_6_BIT_ID 6 379d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_7_BIT_ID 7 389d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_8_BIT_ID 8 399d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_9_BIT_ID 9 409d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_10_BIT_ID 10 419d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_GPIO_PIN_11_BIT_ID 11 429d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_SP_BIT_ID 12 439d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_ISP_BIT_ID 13 449d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_INPUT_SYSTEM_BIT_ID 14 459d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_INPUT_SELECTOR_BIT_ID 15 469d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_IF_BLOCK_BIT_ID 16 479d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_GP_TIMER_0_BIT_ID 17 489d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_GP_TIMER_1_BIT_ID 18 499d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_CSI_SOL_BIT_ID 19 509d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_CSI_EOL_BIT_ID 20 519d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_CSI_SOF_BIT_ID 21 529d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_CSI_EOF_BIT_ID 22 539d4fa1a1SMauro Carvalho Chehab #define HIVE_TIMED_CTRL_IRQ_IS_STREAMING_MONITOR_BIT_ID 23 549d4fa1a1SMauro Carvalho Chehab 559d4fa1a1SMauro Carvalho Chehab #endif /* __TIMED_CTRL_GLOBAL_H_INCLUDED__ */ 56