1 /* 2 * Support for Intel Camera Imaging ISP subsystem. 3 * Copyright (c) 2015, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef __SP_GLOBAL_H_INCLUDED__ 16 #define __SP_GLOBAL_H_INCLUDED__ 17 18 #include <system_local.h> 19 20 #if defined(HAS_SP_2401) 21 #define IS_SP_2401 22 /* 2401 uses 2400 */ 23 #include <scalar_processor_2400_params.h> 24 #elif defined(HAS_SP_2400) 25 #define IS_SP_2400 26 27 #include <scalar_processor_2400_params.h> 28 #else 29 #error "sp_global.h: SP_2400 must be one of {2400, 2401 }" 30 #endif 31 32 #define SP_PMEM_WIDTH_LOG2 SP_PMEM_LOG_WIDTH_BITS 33 #define SP_PMEM_SIZE SP_PMEM_DEPTH 34 35 #define SP_DMEM_SIZE 0x4000 36 37 /* SP Registers */ 38 #define SP_PC_REG 0x09 39 #define SP_SC_REG 0x00 40 #define SP_START_ADDR_REG 0x01 41 #define SP_ICACHE_ADDR_REG 0x05 42 #define SP_IRQ_READY_REG 0x00 43 #define SP_IRQ_CLEAR_REG 0x00 44 #define SP_ICACHE_INV_REG 0x00 45 #define SP_CTRL_SINK_REG 0x0A 46 47 /* SP Register bits */ 48 #define SP_RST_BIT 0x00 49 #define SP_START_BIT 0x01 50 #define SP_BREAK_BIT 0x02 51 #define SP_RUN_BIT 0x03 52 #define SP_BROKEN_BIT 0x04 53 #define SP_IDLE_BIT 0x05 /* READY */ 54 #define SP_SLEEPING_BIT 0x06 55 #define SP_STALLING_BIT 0x07 56 #define SP_IRQ_CLEAR_BIT 0x08 57 #define SP_IRQ_READY_BIT 0x0A 58 #define SP_IRQ_SLEEPING_BIT 0x0B 59 60 #define SP_ICACHE_INV_BIT 0x0C 61 #define SP_IPREFETCH_EN_BIT 0x0D 62 63 #define SP_FIFO0_SINK_BIT 0x00 64 #define SP_FIFO1_SINK_BIT 0x01 65 #define SP_FIFO2_SINK_BIT 0x02 66 #define SP_FIFO3_SINK_BIT 0x03 67 #define SP_FIFO4_SINK_BIT 0x04 68 #define SP_FIFO5_SINK_BIT 0x05 69 #define SP_FIFO6_SINK_BIT 0x06 70 #define SP_FIFO7_SINK_BIT 0x07 71 #define SP_FIFO8_SINK_BIT 0x08 72 #define SP_FIFO9_SINK_BIT 0x09 73 #define SP_FIFOA_SINK_BIT 0x0A 74 #define SP_DMEM_SINK_BIT 0x0B 75 #define SP_CTRL_MT_SINK_BIT 0x0C 76 #define SP_ICACHE_MT_SINK_BIT 0x0D 77 78 #define SP_FIFO0_SINK_REG 0x0A 79 #define SP_FIFO1_SINK_REG 0x0A 80 #define SP_FIFO2_SINK_REG 0x0A 81 #define SP_FIFO3_SINK_REG 0x0A 82 #define SP_FIFO4_SINK_REG 0x0A 83 #define SP_FIFO5_SINK_REG 0x0A 84 #define SP_FIFO6_SINK_REG 0x0A 85 #define SP_FIFO7_SINK_REG 0x0A 86 #define SP_FIFO8_SINK_REG 0x0A 87 #define SP_FIFO9_SINK_REG 0x0A 88 #define SP_FIFOA_SINK_REG 0x0A 89 #define SP_DMEM_SINK_REG 0x0A 90 #define SP_CTRL_MT_SINK_REG 0x0A 91 #define SP_ICACHE_MT_SINK_REG 0x0A 92 93 #endif /* __SP_GLOBAL_H_INCLUDED__ */ 94