1f5fbb83fSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */ 29d4fa1a1SMauro Carvalho Chehab /* 39d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 49d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 59d4fa1a1SMauro Carvalho Chehab * 69d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 79d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 89d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 99d4fa1a1SMauro Carvalho Chehab * 109d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 119d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 129d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 139d4fa1a1SMauro Carvalho Chehab * more details. 149d4fa1a1SMauro Carvalho Chehab */ 159d4fa1a1SMauro Carvalho Chehab 169d4fa1a1SMauro Carvalho Chehab #ifndef __SP_GLOBAL_H_INCLUDED__ 179d4fa1a1SMauro Carvalho Chehab #define __SP_GLOBAL_H_INCLUDED__ 189d4fa1a1SMauro Carvalho Chehab 19f90e73ceSMauro Carvalho Chehab #include <system_local.h> 209d4fa1a1SMauro Carvalho Chehab 219d4fa1a1SMauro Carvalho Chehab #include <scalar_processor_2400_params.h> 229d4fa1a1SMauro Carvalho Chehab 239d4fa1a1SMauro Carvalho Chehab #define SP_PMEM_WIDTH_LOG2 SP_PMEM_LOG_WIDTH_BITS 249d4fa1a1SMauro Carvalho Chehab #define SP_PMEM_SIZE SP_PMEM_DEPTH 259d4fa1a1SMauro Carvalho Chehab 269d4fa1a1SMauro Carvalho Chehab #define SP_DMEM_SIZE 0x4000 279d4fa1a1SMauro Carvalho Chehab 289d4fa1a1SMauro Carvalho Chehab /* SP Registers */ 299d4fa1a1SMauro Carvalho Chehab #define SP_PC_REG 0x09 309d4fa1a1SMauro Carvalho Chehab #define SP_SC_REG 0x00 319d4fa1a1SMauro Carvalho Chehab #define SP_START_ADDR_REG 0x01 329d4fa1a1SMauro Carvalho Chehab #define SP_ICACHE_ADDR_REG 0x05 339d4fa1a1SMauro Carvalho Chehab #define SP_IRQ_READY_REG 0x00 349d4fa1a1SMauro Carvalho Chehab #define SP_IRQ_CLEAR_REG 0x00 359d4fa1a1SMauro Carvalho Chehab #define SP_ICACHE_INV_REG 0x00 369d4fa1a1SMauro Carvalho Chehab #define SP_CTRL_SINK_REG 0x0A 379d4fa1a1SMauro Carvalho Chehab 389d4fa1a1SMauro Carvalho Chehab /* SP Register bits */ 399d4fa1a1SMauro Carvalho Chehab #define SP_RST_BIT 0x00 409d4fa1a1SMauro Carvalho Chehab #define SP_START_BIT 0x01 419d4fa1a1SMauro Carvalho Chehab #define SP_BREAK_BIT 0x02 429d4fa1a1SMauro Carvalho Chehab #define SP_RUN_BIT 0x03 439d4fa1a1SMauro Carvalho Chehab #define SP_BROKEN_BIT 0x04 449d4fa1a1SMauro Carvalho Chehab #define SP_IDLE_BIT 0x05 /* READY */ 459d4fa1a1SMauro Carvalho Chehab #define SP_SLEEPING_BIT 0x06 469d4fa1a1SMauro Carvalho Chehab #define SP_STALLING_BIT 0x07 479d4fa1a1SMauro Carvalho Chehab #define SP_IRQ_CLEAR_BIT 0x08 489d4fa1a1SMauro Carvalho Chehab #define SP_IRQ_READY_BIT 0x0A 499d4fa1a1SMauro Carvalho Chehab #define SP_IRQ_SLEEPING_BIT 0x0B 509d4fa1a1SMauro Carvalho Chehab 519d4fa1a1SMauro Carvalho Chehab #define SP_ICACHE_INV_BIT 0x0C 529d4fa1a1SMauro Carvalho Chehab #define SP_IPREFETCH_EN_BIT 0x0D 539d4fa1a1SMauro Carvalho Chehab 549d4fa1a1SMauro Carvalho Chehab #define SP_FIFO0_SINK_BIT 0x00 559d4fa1a1SMauro Carvalho Chehab #define SP_FIFO1_SINK_BIT 0x01 569d4fa1a1SMauro Carvalho Chehab #define SP_FIFO2_SINK_BIT 0x02 579d4fa1a1SMauro Carvalho Chehab #define SP_FIFO3_SINK_BIT 0x03 589d4fa1a1SMauro Carvalho Chehab #define SP_FIFO4_SINK_BIT 0x04 599d4fa1a1SMauro Carvalho Chehab #define SP_FIFO5_SINK_BIT 0x05 609d4fa1a1SMauro Carvalho Chehab #define SP_FIFO6_SINK_BIT 0x06 619d4fa1a1SMauro Carvalho Chehab #define SP_FIFO7_SINK_BIT 0x07 629d4fa1a1SMauro Carvalho Chehab #define SP_FIFO8_SINK_BIT 0x08 639d4fa1a1SMauro Carvalho Chehab #define SP_FIFO9_SINK_BIT 0x09 649d4fa1a1SMauro Carvalho Chehab #define SP_FIFOA_SINK_BIT 0x0A 659d4fa1a1SMauro Carvalho Chehab #define SP_DMEM_SINK_BIT 0x0B 669d4fa1a1SMauro Carvalho Chehab #define SP_CTRL_MT_SINK_BIT 0x0C 679d4fa1a1SMauro Carvalho Chehab #define SP_ICACHE_MT_SINK_BIT 0x0D 689d4fa1a1SMauro Carvalho Chehab 699d4fa1a1SMauro Carvalho Chehab #define SP_FIFO0_SINK_REG 0x0A 709d4fa1a1SMauro Carvalho Chehab #define SP_FIFO1_SINK_REG 0x0A 719d4fa1a1SMauro Carvalho Chehab #define SP_FIFO2_SINK_REG 0x0A 729d4fa1a1SMauro Carvalho Chehab #define SP_FIFO3_SINK_REG 0x0A 739d4fa1a1SMauro Carvalho Chehab #define SP_FIFO4_SINK_REG 0x0A 749d4fa1a1SMauro Carvalho Chehab #define SP_FIFO5_SINK_REG 0x0A 759d4fa1a1SMauro Carvalho Chehab #define SP_FIFO6_SINK_REG 0x0A 769d4fa1a1SMauro Carvalho Chehab #define SP_FIFO7_SINK_REG 0x0A 779d4fa1a1SMauro Carvalho Chehab #define SP_FIFO8_SINK_REG 0x0A 789d4fa1a1SMauro Carvalho Chehab #define SP_FIFO9_SINK_REG 0x0A 799d4fa1a1SMauro Carvalho Chehab #define SP_FIFOA_SINK_REG 0x0A 809d4fa1a1SMauro Carvalho Chehab #define SP_DMEM_SINK_REG 0x0A 819d4fa1a1SMauro Carvalho Chehab #define SP_CTRL_MT_SINK_REG 0x0A 829d4fa1a1SMauro Carvalho Chehab #define SP_ICACHE_MT_SINK_REG 0x0A 839d4fa1a1SMauro Carvalho Chehab 849d4fa1a1SMauro Carvalho Chehab #endif /* __SP_GLOBAL_H_INCLUDED__ */ 85