1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef __ISP_GLOBAL_H_INCLUDED__ 17 #define __ISP_GLOBAL_H_INCLUDED__ 18 19 #include <system_local.h> 20 21 #ifdef ISP2401 22 #include "isp2401_mamoiada_params.h" 23 #else 24 #include "isp2400_mamoiada_params.h" 25 #endif 26 27 #define ISP_PMEM_WIDTH_LOG2 ISP_LOG2_PMEM_WIDTH 28 #define ISP_PMEM_SIZE ISP_PMEM_DEPTH 29 30 #define ISP_NWAY_LOG2 6 31 #define ISP_VEC_NELEMS_LOG2 ISP_NWAY_LOG2 32 33 #ifdef PIPE_GENERATION 34 #define PIPEMEM(x) MEM(x) 35 #define ISP_NWAY BIT(ISP_NWAY_LOG2) 36 #else 37 #define PIPEMEM(x) 38 #endif 39 40 /* The number of data bytes in a vector disregarding the reduced precision */ 41 #define ISP_VEC_BYTES (ISP_VEC_NELEMS * sizeof(uint16_t)) 42 43 /* ISP SC Registers */ 44 #define ISP_SC_REG 0x00 45 #define ISP_PC_REG 0x07 46 #define ISP_IRQ_READY_REG 0x00 47 #define ISP_IRQ_CLEAR_REG 0x00 48 49 /* ISP SC Register bits */ 50 #define ISP_RST_BIT 0x00 51 #define ISP_START_BIT 0x01 52 #define ISP_BREAK_BIT 0x02 53 #define ISP_RUN_BIT 0x03 54 #define ISP_BROKEN_BIT 0x04 55 #define ISP_IDLE_BIT 0x05 /* READY */ 56 #define ISP_SLEEPING_BIT 0x06 57 #define ISP_STALLING_BIT 0x07 58 #define ISP_IRQ_CLEAR_BIT 0x08 59 #define ISP_IRQ_READY_BIT 0x0A 60 #define ISP_IRQ_SLEEPING_BIT 0x0B 61 62 /* ISP Register bits */ 63 #define ISP_CTRL_SINK_BIT 0x00 64 #define ISP_PMEM_SINK_BIT 0x01 65 #define ISP_DMEM_SINK_BIT 0x02 66 #define ISP_FIFO0_SINK_BIT 0x03 67 #define ISP_FIFO1_SINK_BIT 0x04 68 #define ISP_FIFO2_SINK_BIT 0x05 69 #define ISP_FIFO3_SINK_BIT 0x06 70 #define ISP_FIFO4_SINK_BIT 0x07 71 #define ISP_FIFO5_SINK_BIT 0x08 72 #define ISP_FIFO6_SINK_BIT 0x09 73 #define ISP_VMEM_SINK_BIT 0x0A 74 #define ISP_VAMEM1_SINK_BIT 0x0B 75 #define ISP_VAMEM2_SINK_BIT 0x0C 76 #define ISP_VAMEM3_SINK_BIT 0x0D 77 #define ISP_HMEM_SINK_BIT 0x0E 78 79 #define ISP_CTRL_SINK_REG 0x08 80 #define ISP_PMEM_SINK_REG 0x08 81 #define ISP_DMEM_SINK_REG 0x08 82 #define ISP_FIFO0_SINK_REG 0x08 83 #define ISP_FIFO1_SINK_REG 0x08 84 #define ISP_FIFO2_SINK_REG 0x08 85 #define ISP_FIFO3_SINK_REG 0x08 86 #define ISP_FIFO4_SINK_REG 0x08 87 #define ISP_FIFO5_SINK_REG 0x08 88 #define ISP_FIFO6_SINK_REG 0x08 89 #define ISP_VMEM_SINK_REG 0x08 90 #define ISP_VAMEM1_SINK_REG 0x08 91 #define ISP_VAMEM2_SINK_REG 0x08 92 #define ISP_VAMEM3_SINK_REG 0x08 93 #define ISP_HMEM_SINK_REG 0x08 94 95 /* ISP2401 */ 96 #define BAMEM VMEM 97 #define XNR3_DOWN_BAMEM_BASE_ADDRESS (0x16880) 98 #define XNR3_UP_BAMEM_BASE_ADDRESS (0x12880) 99 #define bmem_ldrow(fu, pid, offset, data) bmem_ldrow_s(fu, pid, offset, data) 100 #define bmem_strow(fu, pid, offset, data) bmem_strow_s(fu, pid, offset, data) 101 #define bmem_ldblk(fu, pid, offset, data) bmem_ldblk_s(fu, pid, offset, data) 102 #define bmem_stblk(fu, pid, offset, data) bmem_stblk_s(fu, pid, offset, data) 103 104 #endif /* __ISP_GLOBAL_H_INCLUDED__ */ 105