19d4fa1a1SMauro Carvalho Chehab /* 29d4fa1a1SMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 39d4fa1a1SMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 49d4fa1a1SMauro Carvalho Chehab * 59d4fa1a1SMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 69d4fa1a1SMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 79d4fa1a1SMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 89d4fa1a1SMauro Carvalho Chehab * 99d4fa1a1SMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 109d4fa1a1SMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 119d4fa1a1SMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 129d4fa1a1SMauro Carvalho Chehab * more details. 139d4fa1a1SMauro Carvalho Chehab */ 149d4fa1a1SMauro Carvalho Chehab 159d4fa1a1SMauro Carvalho Chehab #ifndef _gpio_block_defs_h_ 169d4fa1a1SMauro Carvalho Chehab #define _gpio_block_defs_h_ 179d4fa1a1SMauro Carvalho Chehab 189d4fa1a1SMauro Carvalho Chehab #define _HRT_GPIO_BLOCK_REG_ALIGN 4 199d4fa1a1SMauro Carvalho Chehab 209d4fa1a1SMauro Carvalho Chehab /* R/W registers */ 219d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_e 0 229d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_select 1 239d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_0 2 249d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_1 3 259d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_cnt_0 4 269d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_cnt_1 5 279d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_cnt_2 6 289d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_cnt_3 7 299d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_main_cnt 8 309d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_enable 9 319d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_debounce_sel 10 329d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_debounce_cnt_0 11 339d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_debounce_cnt_1 12 349d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_debounce_cnt_2 13 359d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_debounce_cnt_3 14 369d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_active_level 15 379d4fa1a1SMauro Carvalho Chehab 389d4fa1a1SMauro Carvalho Chehab /* read-only registers */ 399d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di 16 409d4fa1a1SMauro Carvalho Chehab 419d4fa1a1SMauro Carvalho Chehab #endif /* _gpio_block_defs_h_ */ 42