1f5fbb83fSMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */
29d4fa1a1SMauro Carvalho Chehab /*
39d4fa1a1SMauro Carvalho Chehab  * Support for Intel Camera Imaging ISP subsystem.
49d4fa1a1SMauro Carvalho Chehab  * Copyright (c) 2015, Intel Corporation.
59d4fa1a1SMauro Carvalho Chehab  *
69d4fa1a1SMauro Carvalho Chehab  * This program is free software; you can redistribute it and/or modify it
79d4fa1a1SMauro Carvalho Chehab  * under the terms and conditions of the GNU General Public License,
89d4fa1a1SMauro Carvalho Chehab  * version 2, as published by the Free Software Foundation.
99d4fa1a1SMauro Carvalho Chehab  *
109d4fa1a1SMauro Carvalho Chehab  * This program is distributed in the hope it will be useful, but WITHOUT
119d4fa1a1SMauro Carvalho Chehab  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
129d4fa1a1SMauro Carvalho Chehab  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
139d4fa1a1SMauro Carvalho Chehab  * more details.
149d4fa1a1SMauro Carvalho Chehab  */
159d4fa1a1SMauro Carvalho Chehab 
169d4fa1a1SMauro Carvalho Chehab #ifndef _gpio_block_defs_h_
179d4fa1a1SMauro Carvalho Chehab #define _gpio_block_defs_h_
189d4fa1a1SMauro Carvalho Chehab 
199d4fa1a1SMauro Carvalho Chehab #define _HRT_GPIO_BLOCK_REG_ALIGN 4
209d4fa1a1SMauro Carvalho Chehab 
219d4fa1a1SMauro Carvalho Chehab /* R/W registers */
229d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_e				 0
239d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_select		       1
249d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_0				 2
259d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_1				 3
269d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_cnt_0	     4
279d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_cnt_1	     5
289d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_cnt_2	     6
299d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_cnt_3	     7
309d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_main_cnt    8
319d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_do_pwm_enable      9
329d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_debounce_sel	  10
339d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_debounce_cnt_0	11
349d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_debounce_cnt_1	12
359d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_debounce_cnt_2	13
369d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_debounce_cnt_3	14
379d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di_active_level	  15
389d4fa1a1SMauro Carvalho Chehab 
399d4fa1a1SMauro Carvalho Chehab /* read-only registers */
409d4fa1a1SMauro Carvalho Chehab #define _gpio_block_reg_di				  16
419d4fa1a1SMauro Carvalho Chehab 
429d4fa1a1SMauro Carvalho Chehab #endif /* _gpio_block_defs_h_ */
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