1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef _csi_rx_defs_h 17 #define _csi_rx_defs_h 18 19 //#include "rx_csi_common_defs.h" 20 21 #define MIPI_PKT_DATA_WIDTH 32 22 //#define CLK_CROSSING_FIFO_DEPTH 16 23 #define _CSI_RX_REG_ALIGN 4 24 25 //define number of IRQ (see below for definition of each IRQ bits) 26 #define CSI_RX_NOF_IRQS_BYTE_DOMAIN 11 27 #define CSI_RX_NOF_IRQS_ISP_DOMAIN 15 // CSI_RX_NOF_IRQS_BYTE_DOMAIN + remaining from Dphy_rx already on ISP clock domain 28 29 // REGISTER DESCRIPTION 30 //#define _HRT_CSI_RX_SOFTRESET_REG_IDX 0 31 #define _HRT_CSI_RX_ENABLE_REG_IDX 0 32 #define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX 1 33 #define _HRT_CSI_RX_ERROR_HANDLING_REG_IDX 2 34 #define _HRT_CSI_RX_STATUS_REG_IDX 3 35 #define _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 4 36 #define _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 5 37 //#define _HRT_CSI_RX_IRQ_CONFIG_REG_IDX 6 38 #define _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX 6 39 #define _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX 7 40 #define _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane_idx) (8 + (2 * lane_idx)) 41 #define _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane_idx) (8 + (2 * lane_idx) + 1) 42 43 #define _HRT_CSI_RX_NOF_REGISTERS(nof_dlanes) (8 + 2 * (nof_dlanes)) 44 45 //#define _HRT_CSI_RX_SOFTRESET_REG_WIDTH 1 46 #define _HRT_CSI_RX_ENABLE_REG_WIDTH 1 47 #define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_WIDTH 3 48 #define _HRT_CSI_RX_ERROR_HANDLING_REG_WIDTH 4 49 #define _HRT_CSI_RX_STATUS_REG_WIDTH 1 50 #define _HRT_CSI_RX_STATUS_DLANE_HS_REG_WIDTH 8 51 #define _HRT_CSI_RX_STATUS_DLANE_LP_REG_WIDTH 24 52 #define _HRT_CSI_RX_IRQ_CONFIG_REG_WIDTH (CSI_RX_NOF_IRQS_ISP_DOMAIN) 53 #define _HRT_CSI_RX_DLY_CNT_REG_WIDTH 24 54 //#define _HRT_CSI_RX_IRQ_STATUS_REG_WIDTH NOF_IRQS 55 //#define _HRT_CSI_RX_IRQ_CLEAR_REG_WIDTH 0 56 57 #define ONE_LANE_ENABLED 0 58 #define TWO_LANES_ENABLED 1 59 #define THREE_LANES_ENABLED 2 60 #define FOUR_LANES_ENABLED 3 61 62 // Error handling reg bit positions 63 #define ERR_DECISION_BIT 0 64 #define DISC_RESERVED_SP_BIT 1 65 #define DISC_RESERVED_LP_BIT 2 66 #define DIS_INCOMP_PKT_CHK_BIT 3 67 68 #define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_POSEDGE 0 69 #define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_ORIGINAL 1 70 71 // Interrupt bits 72 #define _HRT_RX_CSI_IRQ_SINGLE_PH_ERROR_CORRECTED 0 73 #define _HRT_RX_CSI_IRQ_MULTIPLE_PH_ERROR_DETECTED 1 74 #define _HRT_RX_CSI_IRQ_PAYLOAD_CHECKSUM_ERROR 2 75 #define _HRT_RX_CSI_IRQ_FIFO_FULL_ERROR 3 76 #define _HRT_RX_CSI_IRQ_RESERVED_SP_DETECTED 4 77 #define _HRT_RX_CSI_IRQ_RESERVED_LP_DETECTED 5 78 //#define _HRT_RX_CSI_IRQ_PREMATURE_SOP 6 79 #define _HRT_RX_CSI_IRQ_INCOMPLETE_PACKET 6 80 #define _HRT_RX_CSI_IRQ_FRAME_SYNC_ERROR 7 81 #define _HRT_RX_CSI_IRQ_LINE_SYNC_ERROR 8 82 #define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_ERROR 9 83 #define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_SYNC_ERROR 10 84 85 #define _HRT_RX_CSI_IRQ_DLANE_ESC_ERROR 11 86 #define _HRT_RX_CSI_IRQ_DLANE_TRIGGERESC 12 87 #define _HRT_RX_CSI_IRQ_DLANE_ULPSESC 13 88 #define _HRT_RX_CSI_IRQ_CLANE_ULPSCLKNOT 14 89 90 /* OLD ARASAN FRONTEND IRQs 91 #define _HRT_RX_CSI_IRQ_OVERRUN_BIT 0 92 #define _HRT_RX_CSI_IRQ_RESERVED_BIT 1 93 #define _HRT_RX_CSI_IRQ_SLEEP_MODE_ENTRY_BIT 2 94 #define _HRT_RX_CSI_IRQ_SLEEP_MODE_EXIT_BIT 3 95 #define _HRT_RX_CSI_IRQ_ERR_SOT_HS_BIT 4 96 #define _HRT_RX_CSI_IRQ_ERR_SOT_SYNC_HS_BIT 5 97 #define _HRT_RX_CSI_IRQ_ERR_CONTROL_BIT 6 98 #define _HRT_RX_CSI_IRQ_ERR_ECC_DOUBLE_BIT 7 99 #define _HRT_RX_CSI_IRQ_ERR_ECC_CORRECTED_BIT 8 100 #define _HRT_RX_CSI_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 101 #define _HRT_RX_CSI_IRQ_ERR_CRC_BIT 10 102 #define _HRT_RX_CSI_IRQ_ERR_ID_BIT 11 103 #define _HRT_RX_CSI_IRQ_ERR_FRAME_SYNC_BIT 12 104 #define _HRT_RX_CSI_IRQ_ERR_FRAME_DATA_BIT 13 105 #define _HRT_RX_CSI_IRQ_DATA_TIMEOUT_BIT 14 106 #define _HRT_RX_CSI_IRQ_ERR_ESCAPE_BIT 15 107 #define _HRT_RX_CSI_IRQ_ERR_LINE_SYNC_BIT 16 108 */ 109 110 ////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 111 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE0 0 112 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE1 1 113 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE2 2 114 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE3 3 115 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE0 4 116 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE1 5 117 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE2 6 118 #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE3 7 119 120 ////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 121 #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE0 0 122 #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE1 1 123 #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE2 2 124 #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE3 3 125 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE0 4 126 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE0 5 127 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE0 6 128 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE0 7 129 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE1 8 130 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE1 9 131 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE1 10 132 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE1 11 133 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE2 12 134 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE2 13 135 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE2 14 136 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE2 15 137 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE3 16 138 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE3 17 139 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE3 18 140 #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE3 19 141 #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE0 20 142 #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE1 21 143 #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE2 22 144 #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE3 23 145 146 /*********************************************************/ 147 /*** Relevant declarations from rx_csi_common_defs.h *****/ 148 /*********************************************************/ 149 /* packet bit definition */ 150 #define _HRT_RX_CSI_PKT_SOP_BITPOS 32 151 #define _HRT_RX_CSI_PKT_EOP_BITPOS 33 152 #define _HRT_RX_CSI_PKT_PAYLOAD_BITPOS 0 153 #define _HRT_RX_CSI_PH_CH_ID_BITPOS 22 154 #define _HRT_RX_CSI_PH_FMT_ID_BITPOS 16 155 #define _HRT_RX_CSI_PH_DATA_FIELD_BITPOS 0 156 157 #define _HRT_RX_CSI_PKT_SOP_BITS 1 158 #define _HRT_RX_CSI_PKT_EOP_BITS 1 159 #define _HRT_RX_CSI_PKT_PAYLOAD_BITS 32 160 #define _HRT_RX_CSI_PH_CH_ID_BITS 2 161 #define _HRT_RX_CSI_PH_FMT_ID_BITS 6 162 #define _HRT_RX_CSI_PH_DATA_FIELD_BITS 16 163 164 /* Definition of data format ID at the interface CSS_receiver units */ 165 #define _HRT_RX_CSI_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ 166 #define _HRT_RX_CSI_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ 167 #define _HRT_RX_CSI_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ 168 #define _HRT_RX_CSI_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ 169 170 #endif /* _csi_rx_defs_h */ 171