10057131fSMauro Carvalho Chehab /* 20057131fSMauro Carvalho Chehab * Support for Intel Camera Imaging ISP subsystem. 30057131fSMauro Carvalho Chehab * Copyright (c) 2015, Intel Corporation. 40057131fSMauro Carvalho Chehab * 50057131fSMauro Carvalho Chehab * This program is free software; you can redistribute it and/or modify it 60057131fSMauro Carvalho Chehab * under the terms and conditions of the GNU General Public License, 70057131fSMauro Carvalho Chehab * version 2, as published by the Free Software Foundation. 80057131fSMauro Carvalho Chehab * 90057131fSMauro Carvalho Chehab * This program is distributed in the hope it will be useful, but WITHOUT 100057131fSMauro Carvalho Chehab * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 110057131fSMauro Carvalho Chehab * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 120057131fSMauro Carvalho Chehab * more details. 130057131fSMauro Carvalho Chehab */ 140057131fSMauro Carvalho Chehab 150057131fSMauro Carvalho Chehab #ifndef _csi_rx_defs_h 160057131fSMauro Carvalho Chehab #define _csi_rx_defs_h 170057131fSMauro Carvalho Chehab 180057131fSMauro Carvalho Chehab //#include "rx_csi_common_defs.h" 190057131fSMauro Carvalho Chehab 200057131fSMauro Carvalho Chehab #define MIPI_PKT_DATA_WIDTH 32 210057131fSMauro Carvalho Chehab //#define CLK_CROSSING_FIFO_DEPTH 16 220057131fSMauro Carvalho Chehab #define _CSI_RX_REG_ALIGN 4 230057131fSMauro Carvalho Chehab 240057131fSMauro Carvalho Chehab //define number of IRQ (see below for definition of each IRQ bits) 250057131fSMauro Carvalho Chehab #define CSI_RX_NOF_IRQS_BYTE_DOMAIN 11 260057131fSMauro Carvalho Chehab #define CSI_RX_NOF_IRQS_ISP_DOMAIN 15 // CSI_RX_NOF_IRQS_BYTE_DOMAIN + remaining from Dphy_rx already on ISP clock domain 270057131fSMauro Carvalho Chehab 280057131fSMauro Carvalho Chehab // REGISTER DESCRIPTION 290057131fSMauro Carvalho Chehab //#define _HRT_CSI_RX_SOFTRESET_REG_IDX 0 300057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_ENABLE_REG_IDX 0 310057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX 1 320057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_ERROR_HANDLING_REG_IDX 2 330057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_REG_IDX 3 340057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 4 350057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 5 360057131fSMauro Carvalho Chehab //#define _HRT_CSI_RX_IRQ_CONFIG_REG_IDX 6 370057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX 6 380057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX 7 390057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane_idx) (8 + (2 * lane_idx)) 400057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane_idx) (8 + (2 * lane_idx) + 1) 410057131fSMauro Carvalho Chehab 420057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_NOF_REGISTERS(nof_dlanes) (8 + 2 * (nof_dlanes)) 430057131fSMauro Carvalho Chehab 440057131fSMauro Carvalho Chehab //#define _HRT_CSI_RX_SOFTRESET_REG_WIDTH 1 450057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_ENABLE_REG_WIDTH 1 460057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_WIDTH 3 470057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_ERROR_HANDLING_REG_WIDTH 4 480057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_REG_WIDTH 1 490057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_HS_REG_WIDTH 8 500057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_REG_WIDTH 24 510057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_IRQ_CONFIG_REG_WIDTH (CSI_RX_NOF_IRQS_ISP_DOMAIN) 520057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_DLY_CNT_REG_WIDTH 24 530057131fSMauro Carvalho Chehab //#define _HRT_CSI_RX_IRQ_STATUS_REG_WIDTH NOF_IRQS 540057131fSMauro Carvalho Chehab //#define _HRT_CSI_RX_IRQ_CLEAR_REG_WIDTH 0 550057131fSMauro Carvalho Chehab 560057131fSMauro Carvalho Chehab #define ONE_LANE_ENABLED 0 570057131fSMauro Carvalho Chehab #define TWO_LANES_ENABLED 1 580057131fSMauro Carvalho Chehab #define THREE_LANES_ENABLED 2 590057131fSMauro Carvalho Chehab #define FOUR_LANES_ENABLED 3 600057131fSMauro Carvalho Chehab 610057131fSMauro Carvalho Chehab // Error handling reg bit positions 620057131fSMauro Carvalho Chehab #define ERR_DECISION_BIT 0 630057131fSMauro Carvalho Chehab #define DISC_RESERVED_SP_BIT 1 640057131fSMauro Carvalho Chehab #define DISC_RESERVED_LP_BIT 2 650057131fSMauro Carvalho Chehab #define DIS_INCOMP_PKT_CHK_BIT 3 660057131fSMauro Carvalho Chehab 670057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_POSEDGE 0 680057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_ORIGINAL 1 690057131fSMauro Carvalho Chehab 700057131fSMauro Carvalho Chehab // Interrupt bits 710057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_SINGLE_PH_ERROR_CORRECTED 0 720057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_MULTIPLE_PH_ERROR_DETECTED 1 730057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_PAYLOAD_CHECKSUM_ERROR 2 740057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_FIFO_FULL_ERROR 3 750057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_RESERVED_SP_DETECTED 4 760057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_RESERVED_LP_DETECTED 5 770057131fSMauro Carvalho Chehab //#define _HRT_RX_CSI_IRQ_PREMATURE_SOP 6 780057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_INCOMPLETE_PACKET 6 790057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_FRAME_SYNC_ERROR 7 800057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_LINE_SYNC_ERROR 8 810057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_ERROR 9 820057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_SYNC_ERROR 10 830057131fSMauro Carvalho Chehab 840057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_DLANE_ESC_ERROR 11 850057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_DLANE_TRIGGERESC 12 860057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_DLANE_ULPSESC 13 870057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_CLANE_ULPSCLKNOT 14 880057131fSMauro Carvalho Chehab 890057131fSMauro Carvalho Chehab /* OLD ARASAN FRONTEND IRQs 900057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_OVERRUN_BIT 0 910057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_RESERVED_BIT 1 920057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_SLEEP_MODE_ENTRY_BIT 2 930057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_SLEEP_MODE_EXIT_BIT 3 940057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_SOT_HS_BIT 4 950057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_SOT_SYNC_HS_BIT 5 960057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_CONTROL_BIT 6 970057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_ECC_DOUBLE_BIT 7 980057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_ECC_CORRECTED_BIT 8 990057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 1000057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_CRC_BIT 10 1010057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_ID_BIT 11 1020057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_FRAME_SYNC_BIT 12 1030057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_FRAME_DATA_BIT 13 1040057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_DATA_TIMEOUT_BIT 14 1050057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_ESCAPE_BIT 15 1060057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_IRQ_ERR_LINE_SYNC_BIT 16 1070057131fSMauro Carvalho Chehab */ 1080057131fSMauro Carvalho Chehab 1090057131fSMauro Carvalho Chehab ////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 1100057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE0 0 1110057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE1 1 1120057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE2 2 1130057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE3 3 1140057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE0 4 1150057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE1 5 1160057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE2 6 1170057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE3 7 1180057131fSMauro Carvalho Chehab 1190057131fSMauro Carvalho Chehab ////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 1200057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE0 0 1210057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE1 1 1220057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE2 2 1230057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE3 3 1240057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE0 4 1250057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE0 5 1260057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE0 6 1270057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE0 7 1280057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE1 8 1290057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE1 9 1300057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE1 10 1310057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE1 11 1320057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE2 12 1330057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE2 13 1340057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE2 14 1350057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE2 15 1360057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE3 16 1370057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE3 17 1380057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE3 18 1390057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE3 19 1400057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE0 20 1410057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE1 21 1420057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE2 22 1430057131fSMauro Carvalho Chehab #define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE3 23 1440057131fSMauro Carvalho Chehab 1450057131fSMauro Carvalho Chehab /*********************************************************/ 1460057131fSMauro Carvalho Chehab /*** Relevant declarations from rx_csi_common_defs.h *****/ 1470057131fSMauro Carvalho Chehab /*********************************************************/ 1480057131fSMauro Carvalho Chehab /* packet bit definition */ 1490057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PKT_SOP_BITPOS 32 1500057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PKT_EOP_BITPOS 33 1510057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PKT_PAYLOAD_BITPOS 0 1520057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PH_CH_ID_BITPOS 22 1530057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PH_FMT_ID_BITPOS 16 1540057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PH_DATA_FIELD_BITPOS 0 1550057131fSMauro Carvalho Chehab 1560057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PKT_SOP_BITS 1 1570057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PKT_EOP_BITS 1 1580057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PKT_PAYLOAD_BITS 32 1590057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PH_CH_ID_BITS 2 1600057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PH_FMT_ID_BITS 6 1610057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_PH_DATA_FIELD_BITS 16 1620057131fSMauro Carvalho Chehab 1630057131fSMauro Carvalho Chehab /* Definition of data format ID at the interface CSS_receiver units */ 1640057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ 1650057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ 1660057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ 1670057131fSMauro Carvalho Chehab #define _HRT_RX_CSI_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ 1680057131fSMauro Carvalho Chehab 1690057131fSMauro Carvalho Chehab #endif /* _csi_rx_defs_h */ 170