1 /* 2 * Support for Intel Camera Imaging ISP subsystem. 3 * Copyright (c) 2015, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #ifndef _mipi_backend_defs_h 16 #define _mipi_backend_defs_h 17 18 #include "mipi_backend_common_defs.h" 19 20 #define MIPI_BACKEND_REG_ALIGN 4 // assuming 32 bit control bus width 21 22 #define _HRT_MIPI_BACKEND_NOF_IRQS 3 // sid_lut 23 24 // SH Backend Register IDs 25 #define _HRT_MIPI_BACKEND_ENABLE_REG_IDX 0 26 #define _HRT_MIPI_BACKEND_STATUS_REG_IDX 1 27 //#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_IDX 2 28 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX 2 29 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG1_IDX 3 30 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG2_IDX 4 31 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG3_IDX 5 32 #define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX 6 33 #define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX 7 34 #define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX 8 35 #define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX 9 36 #define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_IDX 10 37 //// 38 #define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX 11 39 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX 12 40 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX 13 41 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P1_REG_IDX 14 42 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P2_REG_IDX 15 43 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P3_REG_IDX 16 44 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P0_REG_IDX 17 45 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P1_REG_IDX 18 46 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P2_REG_IDX 19 47 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P3_REG_IDX 20 48 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P0_REG_IDX 21 49 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P1_REG_IDX 22 50 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P2_REG_IDX 23 51 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P3_REG_IDX 24 52 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX 25 53 //// 54 #define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX 26 55 #define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX 27 56 //#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_IDX 28 57 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX 28 58 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX 29 59 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX 30 60 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX 31 61 62 #define _HRT_MIPI_BACKEND_NOF_REGISTERS 32 // excluding the LP LUT entries 63 64 #define _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX 32 65 66 ///////////////////////////////////////////////////////////////////////////////////////////////////// 67 #define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH 1 68 #define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH 1 69 //#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_WIDTH 1 70 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG_WIDTH 32 71 #define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH 7 72 #define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_WIDTH 9 73 #define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_WIDTH 8 74 #define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_WIDTH _HRT_MIPI_BACKEND_NOF_IRQS 75 #define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH 0 76 #define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_WIDTH 1 77 #define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH 1 + 2 + 6 78 //#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_WIDTH 1 79 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH 7 80 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH 7 81 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH 7 82 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH 7 83 84 ///////////////////////////////////////////////////////////////////////////////////////////////////// 85 86 #define _HRT_MIPI_BACKEND_NOF_SP_LUT_ENTRIES 4 87 88 //#define _HRT_MIPI_BACKEND_MAX_NOF_LP_LUT_ENTRIES 16 // to satisfy hss model static array declaration 89 90 #define _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH 2 91 #define _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 6 92 #define _HRT_MIPI_BACKEND_PACKET_ID_WIDTH _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 93 94 #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB 0 95 #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB + (pix_width) - 1) 96 #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) + 1) 97 #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) + 1) 98 #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) + (pix_width) - 1) 99 #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) + 1) 100 #define _HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) + 1) 101 #define _HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) + 1) 102 #define _HRT_MIPI_BACKEND_STREAMING_WIDTH(pix_width) (_HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) + 1) 103 104 /*************************************************************************************************/ 105 /* Custom Decoding */ 106 /* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ 107 /*************************************************************************************************/ 108 #define _HRT_MIPI_BACKEND_CUST_EN_IDX 0 /* 2bits */ 109 #define _HRT_MIPI_BACKEND_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ 110 #define _HRT_MIPI_BACKEND_CUST_EN_HIGH_PREC_IDX 8 // 1 bit 111 #define _HRT_MIPI_BACKEND_CUST_EN_WIDTH 9 112 #define _HRT_MIPI_BACKEND_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ 113 #define _HRT_MIPI_BACKEND_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ 114 115 #define _HRT_MIPI_BACKEND_CUST_EN_OPTION_IDX 1 116 117 /* Data State config = {get_bits(6bits), valid(1bit)} */ 118 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ 119 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S1_IDX 8 /* 7bits */ 120 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S2_IDX 16 /* was 14 7bits */ 121 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_WIDTH 24 /* was 21*/ 122 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ 123 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ 124 125 /* Pixel Extractor config */ 126 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 6bits */ 127 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_ALIGN_IDX 6 /* 5bits */ 128 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_MASK_IDX 11 /* was 10 18bits */ 129 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_EN_IDX 29 /* was 28 1bits */ 130 131 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_WIDTH 30 /* was 29 */ 132 133 /* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ 134 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ 135 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ 136 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ 137 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ 138 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_WIDTH 16 139 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ 140 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ 141 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ 142 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ 143 144 /*************************************************************************************************/ 145 /* MIPI backend output streaming interface definition */ 146 /* These parameters define the fields within the streaming bus. These should also be used by the */ 147 /* subsequent block, ie stream2mmio. */ 148 /*************************************************************************************************/ 149 /* The pipe backend - stream2mmio should be design time configurable in */ 150 /* PixWidth - Number of bits per pixel */ 151 /* PPC - Pixel per Clocks */ 152 /* NumSids - Max number of source Ids (ifc's) and derived from that: */ 153 /* SidWidth - Number of bits required for the sid parameter */ 154 /* In order to keep this configurability, below Macro's have these as a parameter */ 155 /*************************************************************************************************/ 156 157 #define HRT_MIPI_BACKEND_STREAM_EOP_BIT 0 158 #define HRT_MIPI_BACKEND_STREAM_SOP_BIT 1 159 #define HRT_MIPI_BACKEND_STREAM_EOF_BIT 2 160 #define HRT_MIPI_BACKEND_STREAM_SOF_BIT 3 161 #define HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT 4 162 #define HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT + (sid_width) - 1) 163 #define HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, p) (HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) + 1 + p) 164 165 #define HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, ppc) + ((pix_width) * p)) 166 #define HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) + (pix_width) - 1) 167 168 #if 0 169 //#define HRT_MIPI_BACKEND_STREAM_PIX_BITS 14 170 //#define HRT_MIPI_BACKEND_STREAM_CHID_BITS 4 171 //#define HRT_MIPI_BACKEND_STREAM_PPC 4 172 #endif 173 174 #define HRT_MIPI_BACKEND_STREAM_BITS(sid_width, ppc, pix_width) (HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, (ppc - 1)) + 1) 175 176 /* SP and LP LUT BIT POSITIONS */ 177 #define HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT 0 // 0 178 #define HRT_MIPI_BACKEND_LUT_SID_LS_BIT HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT + 1 // 1 179 #define HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_LUT_SID_LS_BIT + (sid_width) - 1) // 1 + (4) - 1 = 4 180 #define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 // 5 181 #define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH - 1 // 6 182 #define HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 183 #define HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH - 1 // 12 184 185 /* #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 */ 186 187 #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 188 #define HRT_MIPI_BACKEND_LP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) + 1 // 13 189 190 // temp solution 191 //#define HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT + 1 // 8 192 //#define HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT + 1 // 9 193 //#define HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT + 1 // 10 194 //#define HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT + 1 // 11 195 //#define HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT + 1 // 12 196 //#define HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 25 197 //#define HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT + 1 // 26 198 //#define HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 39 199 //#define HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT + 1 // 40 200 //#define HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 53 201 //#define HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT + 1 // 54 202 //#define HRT_MIPI_BACKEND_STREAM_PIXD_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 67 203 204 // vc hidden in pixb data (passed as raw12 the pipe) 205 #define HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, 1) + 10 //HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + 10 // 36 206 #define HRT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) + 1 // 37 207 208 #endif /* _mipi_backend_defs_h */ 209